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1/*
2 * (C) Copyright 2006-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <libfdt.h>
27#include <fdt_support.h>
28#include <ppc4xx.h>
29#include <asm/gpio.h>
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <asm/bitops.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
36#if !defined(CONFIG_SYS_NO_FLASH)
37extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
38#endif
39
40extern void __ft_board_setup(void *blob, bd_t *bd);
41ulong flash_get_size(ulong base, int banknum);
42
43static inline u32 get_async_pci_freq(void)
44{
45 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
46 CONFIG_SYS_BCSR5_PCI66EN)
47 return 66666666;
48 else
49 return 33333333;
50}
51
52int board_early_init_f(void)
53{
54 u32 sdr0_cust0;
55 u32 sdr0_pfc1, sdr0_pfc2;
56 u32 reg;
57
58 mtdcr(EBC0_CFGADDR, EBC0_CFG);
59 mtdcr(EBC0_CFGDATA, 0xb8400000);
60
61 /*
62 * Setup the interrupt controller polarities, triggers, etc.
63 */
64 mtdcr(UIC0SR, 0xffffffff); /* clear all */
65 mtdcr(UIC0ER, 0x00000000); /* disable all */
66 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
67 mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
68 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
69 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
70 mtdcr(UIC0SR, 0xffffffff); /* clear all */
71
72 mtdcr(UIC1SR, 0xffffffff); /* clear all */
73 mtdcr(UIC1ER, 0x00000000); /* disable all */
74 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
75 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
76 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
77 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
78 mtdcr(UIC1SR, 0xffffffff); /* clear all */
79
80 mtdcr(UIC2SR, 0xffffffff); /* clear all */
81 mtdcr(UIC2ER, 0x00000000); /* disable all */
82 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
83 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
84 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
85 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
86 mtdcr(UIC2SR, 0xffffffff); /* clear all */
87
88 /* Check and reconfigure the PCI sync clock if necessary */
89 ppc4xx_pci_sync_clock_config(get_async_pci_freq());
90
91 /* 50MHz tmrclk */
92 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
93
94 /* clear write protects */
95 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
96
97 /* enable Ethernet */
98 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
99
100 /* enable USB device */
101 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
102
103 /* select Ethernet (and optionally IIC1) pins */
104 mfsdr(SDR0_PFC1, sdr0_pfc1);
105 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
106 SDR0_PFC1_SELECT_CONFIG_4;
107#ifdef CONFIG_I2C_MULTI_BUS
108 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
109#endif
110 /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
111 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
112 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
113 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
114
115 mfsdr(SDR0_PFC2, sdr0_pfc2);
116 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
117 SDR0_PFC2_SELECT_CONFIG_4;
118 mtsdr(SDR0_PFC2, sdr0_pfc2);
119 mtsdr(SDR0_PFC1, sdr0_pfc1);
120
121 /* PCI arbiter enabled */
122 mfsdr(SDR0_PCI0, reg);
123 mtsdr(SDR0_PCI0, 0x80000000 | reg);
124
125 /* setup NAND FLASH */
126 mfsdr(SDR0_CUST0, sdr0_cust0);
127 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
128 SDR0_CUST0_NDFC_ENABLE |
129 SDR0_CUST0_NDFC_BW_8_BIT |
130 SDR0_CUST0_NDFC_ARE_MASK |
131 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
132 mtsdr(SDR0_CUST0, sdr0_cust0);
133
134 return 0;
135}
136
137int misc_init_r(void)
138{
139#if !defined(CONFIG_SYS_NO_FLASH)
140 uint pbcr;
141 int size_val = 0;
142#endif
143#ifdef CONFIG_440EPX
144 unsigned long usb2d0cr = 0;
145 unsigned long usb2phy0cr, usb2h0cr = 0;
146 unsigned long sdr0_pfc1;
147 char *act = getenv("usbact");
148#endif
149 u32 reg;
150
151#if !defined(CONFIG_SYS_NO_FLASH)
152 /* Re-do flash sizing to get full correct info */
153
154 /* adjust flash start and offset */
155 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
156 gd->bd->bi_flashoffset = 0;
157
158#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
159 mtdcr(EBC0_CFGADDR, PB3CR);
160#else
161 mtdcr(EBC0_CFGADDR, PB0CR);
162#endif
163 pbcr = mfdcr(EBC0_CFGDATA);
164 size_val = ffs(gd->bd->bi_flashsize) - 21;
165 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
166#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
167 mtdcr(EBC0_CFGADDR, PB3CR);
168#else
169 mtdcr(EBC0_CFGADDR, PB0CR);
170#endif
171 mtdcr(EBC0_CFGDATA, pbcr);
172
173 /*
174 * Re-check to get correct base address
175 */
176 flash_get_size(gd->bd->bi_flashstart, 0);
177
178#ifdef CONFIG_ENV_IS_IN_FLASH
179 /* Monitor protection ON by default */
180 (void)flash_protect(FLAG_PROTECT_SET,
181 -CONFIG_SYS_MONITOR_LEN,
182 0xffffffff,
183 &flash_info[0]);
184
185 /* Env protection ON by default */
186 (void)flash_protect(FLAG_PROTECT_SET,
187 CONFIG_ENV_ADDR_REDUND,
188 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
189 &flash_info[0]);
190#endif
191#endif /* CONFIG_SYS_NO_FLASH */
192
193 /*
194 * USB suff...
195 */
196#ifdef CONFIG_440EPX
197 if (act == NULL || strcmp(act, "hostdev") == 0) {
198 /* SDR Setting */
199 mfsdr(SDR0_PFC1, sdr0_pfc1);
200 mfsdr(SDR0_USB2D0CR, usb2d0cr);
201 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
202 mfsdr(SDR0_USB2H0CR, usb2h0cr);
203
204 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
205 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
210 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
211 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
212 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
213 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
214
215 /*
216 * An 8-bit/60MHz interface is the only possible alternative
217 * when connecting the Device to the PHY
218 */
219 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
220 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
221
222 /*
223 * To enable the USB 2.0 Device function
224 * through the UTMI interface
225 */
226 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
227 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
228
229 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
230 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
231
232 mtsdr(SDR0_PFC1, sdr0_pfc1);
233 mtsdr(SDR0_USB2D0CR, usb2d0cr);
234 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
235 mtsdr(SDR0_USB2H0CR, usb2h0cr);
236
237 /*clear resets*/
238 udelay (1000);
239 mtsdr(SDR0_SRST1, 0x00000000);
240 udelay (1000);
241 mtsdr(SDR0_SRST0, 0x00000000);
242
243 printf("USB: Host(int phy) Device(ext phy)\n");
244
245 } else if (strcmp(act, "dev") == 0) {
246 /*-------------------PATCH-------------------------------*/
247 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
248
249 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
250 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
251 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
252 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
253 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
254 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
255 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
256 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
257 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
258
259 udelay (1000);
260 mtsdr(SDR0_SRST1, 0x672c6000);
261
262 udelay (1000);
263 mtsdr(SDR0_SRST0, 0x00000080);
264
265 udelay (1000);
266 mtsdr(SDR0_SRST1, 0x60206000);
267
268 *(unsigned int *)(0xe0000350) = 0x00000001;
269
270 udelay (1000);
271 mtsdr(SDR0_SRST1, 0x60306000);
272 /*-------------------PATCH-------------------------------*/
273
274 /* SDR Setting */
275 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
276 mfsdr(SDR0_USB2H0CR, usb2h0cr);
277 mfsdr(SDR0_USB2D0CR, usb2d0cr);
278 mfsdr(SDR0_PFC1, sdr0_pfc1);
279
280 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
281 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
282 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
283 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
284 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
285 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
286 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
287 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
288 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
289 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
290
291 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
292 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
293
294 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
295 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
296
297 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
298 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
299
300 mtsdr(SDR0_USB2H0CR, usb2h0cr);
301 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
302 mtsdr(SDR0_USB2D0CR, usb2d0cr);
303 mtsdr(SDR0_PFC1, sdr0_pfc1);
304
305 /* clear resets */
306 udelay (1000);
307 mtsdr(SDR0_SRST1, 0x00000000);
308 udelay (1000);
309 mtsdr(SDR0_SRST0, 0x00000000);
310
311 printf("USB: Device(int phy)\n");
312 }
313#endif /* CONFIG_440EPX */
314
315 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
316 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
317 mtsdr(SDR0_SRST1, reg);
318
319 /*
320 * Clear PLB4A0_ACR[WRP]
321 * This fix will make the MAL burst disabling patch for the Linux
322 * EMAC driver obsolete.
323 */
324 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
325 mtdcr(PLB4_ACR, reg);
326
327 return 0;
328}
329
330int checkboard(void)
331{
332 char *s = getenv("serial#");
333 u8 rev;
334 u32 clock = get_async_pci_freq();
335
336#ifdef CONFIG_440EPX
337 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
338#else
339 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
340#endif
341
342 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
343 printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
344
345 if (s != NULL) {
346 puts(", serial# ");
347 puts(s);
348 }
349 putc('\n');
350
351 /*
352 * Reconfiguration of the PCI sync clock is already done,
353 * now check again if everything is in range:
354 */
355 if (ppc4xx_pci_sync_clock_config(clock)) {
356 printf("ERROR: PCI clocking incorrect (async=%d "
357 "sync=%ld)!\n", clock, get_PCI_freq());
358 }
359
360 return (0);
361}
362
363#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
364/*
365 * Assign interrupts to PCI devices.
366 */
367void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
368{
369 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
370}
371#endif
372
373#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
374/*
375 * On NAND-booting sequoia, we need to patch the chips select numbers
376 * in the dtb (CS0 - NAND, CS3 - NOR)
377 */
378void ft_board_setup(void *blob, bd_t *bd)
379{
380 int rc;
381 int len;
382 int nodeoffset;
383 struct fdt_property *prop;
384 u32 *reg;
385 char path[32];
386
387 /* First do common fdt setup */
388 __ft_board_setup(blob, bd);
389
390 /* And now configure NOR chip select to 3 instead of 0 */
391 strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
392 nodeoffset = fdt_path_offset(blob, path);
393 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
394 if (prop == NULL) {
395 printf("Unable to update NOR chip select for NAND booting\n");
396 return;
397 }
398 reg = (u32 *)&prop->data[0];
399 reg[0] = 3;
400 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
401 if (rc) {
402 printf("Unable to update property NOR mappings, err=%s\n",
403 fdt_strerror(rc));
404 return;
405 }
406
407 /* And now configure NAND chip select to 0 instead of 3 */
408 strcpy(path, "/plb/opb/ebc/ndfc@3,0");
409 nodeoffset = fdt_path_offset(blob, path);
410 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
411 if (prop == NULL) {
412 printf("Unable to update NDFC chip select for NAND booting\n");
413 return;
414 }
415 reg = (u32 *)&prop->data[0];
416 reg[0] = 0;
417 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
418 if (rc) {
419 printf("Unable to update property NDFC mappings, err=%s\n",
420 fdt_strerror(rc));
421 return;
422 }
423}
424#endif /* CONFIG_NAND_U_BOOT */