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1 | /* | |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <mmc.h> | |
11 | ||
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <linux/sizes.h> | |
15 | ||
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/crm_regs.h> | |
18 | #include <asm/arch/iomux.h> | |
19 | #include <asm/arch/mx6-pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/mach-imx/iomux-v3.h> | |
22 | ||
23 | #include "../common/board.h" | |
24 | ||
25 | DECLARE_GLOBAL_DATA_PTR; | |
26 | ||
27 | #ifdef CONFIG_NAND_MXS | |
28 | ||
29 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
30 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
31 | PAD_CTL_SRE_FAST) | |
32 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
33 | ||
34 | static iomux_v3_cfg_t const nand_pads[] = { | |
35 | IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
36 | IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
37 | IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
38 | IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
39 | IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
40 | IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
41 | IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
42 | IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
43 | IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
44 | IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
45 | IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
46 | IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
47 | IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
48 | IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
49 | IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
50 | }; | |
51 | ||
52 | void setup_gpmi_nand(void) | |
53 | { | |
54 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
55 | ||
56 | /* config gpmi nand iomux */ | |
57 | SETUP_IOMUX_PADS(nand_pads); | |
58 | ||
59 | clrbits_le32(&mxc_ccm->CCGR4, | |
60 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
61 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
62 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
63 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
64 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
65 | ||
66 | /* | |
67 | * config gpmi and bch clock to 100 MHz | |
68 | * bch/gpmi select PLL2 PFD2 400M | |
69 | * 100M = 400M / 4 | |
70 | */ | |
71 | clrbits_le32(&mxc_ccm->cscmr1, | |
72 | MXC_CCM_CSCMR1_BCH_CLK_SEL | | |
73 | MXC_CCM_CSCMR1_GPMI_CLK_SEL); | |
74 | clrsetbits_le32(&mxc_ccm->cscdr1, | |
75 | MXC_CCM_CSCDR1_BCH_PODF_MASK | | |
76 | MXC_CCM_CSCDR1_GPMI_PODF_MASK, | |
77 | (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | | |
78 | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); | |
79 | ||
80 | /* enable gpmi and bch clock gating */ | |
81 | setbits_le32(&mxc_ccm->CCGR4, | |
82 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
83 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
84 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
85 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
86 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); | |
87 | ||
88 | /* enable apbh clock gating */ | |
89 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
90 | } | |
91 | #endif /* CONFIG_NAND_MXS */ | |
92 | ||
93 | #ifdef CONFIG_ENV_IS_IN_MMC | |
94 | int board_mmc_get_env_dev(int devno) | |
95 | { | |
96 | /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ | |
97 | return (devno == 0) ? 0 : 1; | |
98 | } | |
99 | #endif | |
100 | ||
101 | #ifdef CONFIG_SPL_BUILD | |
102 | #include <spl.h> | |
103 | ||
104 | #ifdef CONFIG_ENV_IS_IN_MMC | |
105 | void board_boot_order(u32 *spl_boot_list) | |
106 | { | |
107 | u32 bmode = imx6_src_get_boot_mode(); | |
108 | u8 boot_dev = BOOT_DEVICE_MMC1; | |
109 | ||
110 | switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { | |
111 | case IMX6_BMODE_SD: | |
112 | case IMX6_BMODE_ESD: | |
113 | /* SD/eSD - BOOT_DEVICE_MMC1 */ | |
114 | break; | |
115 | case IMX6_BMODE_MMC: | |
116 | case IMX6_BMODE_EMMC: | |
117 | /* MMC/eMMC */ | |
118 | boot_dev = BOOT_DEVICE_MMC2; | |
119 | break; | |
120 | default: | |
121 | /* Default - BOOT_DEVICE_MMC1 */ | |
122 | printf("Wrong board boot order\n"); | |
123 | break; | |
124 | } | |
125 | ||
126 | spl_boot_list[0] = boot_dev; | |
127 | } | |
128 | #endif | |
129 | #endif /* CONFIG_SPL_BUILD */ |