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1 | /* | |
2 | * (C) Copyright 2009 DENX Software Engineering | |
3 | * Author: John Rigby <jrigby@gmail.com> | |
4 | * | |
5 | * Based on imx27lite.c: | |
6 | * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net> | |
7 | * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com> | |
8 | * And: | |
9 | * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | #include <common.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/arch/imx-regs.h> | |
30 | #include <asm/arch/imx25-pinmux.h> | |
31 | #include <asm/gpio.h> | |
32 | #include <asm/arch/sys_proto.h> | |
33 | ||
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | #ifdef CONFIG_FEC_MXC | |
37 | #define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) | |
38 | #define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) | |
39 | void tx25_fec_init(void) | |
40 | { | |
41 | struct iomuxc_mux_ctl *muxctl; | |
42 | struct iomuxc_pad_ctl *padctl; | |
43 | u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); | |
44 | u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; | |
45 | ||
46 | debug("tx25_fec_init\n"); | |
47 | /* | |
48 | * fec pin init is generic | |
49 | */ | |
50 | mx25_fec_init_pins(); | |
51 | ||
52 | /* | |
53 | * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. | |
54 | * | |
55 | * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13 | |
56 | * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11 | |
57 | */ | |
58 | muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; | |
59 | padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; | |
60 | ||
61 | writel(gpio_mux_mode, &muxctl->pad_d13); | |
62 | writel(gpio_mux_mode, &muxctl->pad_d11); | |
63 | ||
64 | writel(0x0, &padctl->pad_d13); | |
65 | writel(0x0, &padctl->pad_d11); | |
66 | ||
67 | /* drop PHY power and assert reset (low) */ | |
68 | gpio_direction_output(GPIO_FEC_RESET_B, 0); | |
69 | gpio_direction_output(GPIO_FEC_ENABLE_B, 0); | |
70 | ||
71 | mdelay(5); | |
72 | ||
73 | debug("resetting phy\n"); | |
74 | ||
75 | /* turn on PHY power leaving reset asserted */ | |
76 | gpio_set_value(GPIO_FEC_ENABLE_B, 1); | |
77 | ||
78 | mdelay(10); | |
79 | ||
80 | /* | |
81 | * Setup some strapping pins that are latched by the PHY | |
82 | * as reset goes high. | |
83 | * | |
84 | * Set PHY mode to 111 | |
85 | * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5 | |
86 | * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5 | |
87 | * mode2 is tied high so nothing to do | |
88 | * | |
89 | * Turn on RMII mode | |
90 | * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode | |
91 | */ | |
92 | /* | |
93 | * save three current mux modes and set each to gpio mode | |
94 | */ | |
95 | saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0); | |
96 | saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1); | |
97 | saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv); | |
98 | ||
99 | writel(gpio_mux_mode, &muxctl->pad_fec_rdata0); | |
100 | writel(gpio_mux_mode, &muxctl->pad_fec_rdata1); | |
101 | writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv); | |
102 | ||
103 | /* | |
104 | * set each to 1 and make each an output | |
105 | */ | |
106 | gpio_direction_output(IMX_GPIO_NR(3, 10), 1); | |
107 | gpio_direction_output(IMX_GPIO_NR(3, 11), 1); | |
108 | gpio_direction_output(IMX_GPIO_NR(3, 12), 1); | |
109 | ||
110 | mdelay(22); /* this value came from RedBoot */ | |
111 | ||
112 | /* | |
113 | * deassert PHY reset | |
114 | */ | |
115 | gpio_set_value(GPIO_FEC_RESET_B, 1); | |
116 | ||
117 | mdelay(5); | |
118 | ||
119 | /* | |
120 | * set FEC pins back | |
121 | */ | |
122 | writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0); | |
123 | writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1); | |
124 | writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv); | |
125 | } | |
126 | #else | |
127 | #define tx25_fec_init() | |
128 | #endif | |
129 | ||
130 | int board_init() | |
131 | { | |
132 | #ifdef CONFIG_MXC_UART | |
133 | mx25_uart1_init_pins(); | |
134 | #endif | |
135 | /* board id for linux */ | |
136 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; | |
137 | return 0; | |
138 | } | |
139 | ||
140 | int board_late_init(void) | |
141 | { | |
142 | tx25_fec_init(); | |
143 | return 0; | |
144 | } | |
145 | ||
146 | int dram_init(void) | |
147 | { | |
148 | /* dram_init must store complete ramsize in gd->ram_size */ | |
149 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, | |
150 | PHYS_SDRAM_1_SIZE); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | void dram_init_banksize(void) | |
155 | { | |
156 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
157 | gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, | |
158 | PHYS_SDRAM_1_SIZE); | |
159 | #if CONFIG_NR_DRAM_BANKS > 1 | |
160 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
161 | gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, | |
162 | PHYS_SDRAM_2_SIZE); | |
163 | #else | |
164 | ||
165 | #endif | |
166 | } | |
167 | ||
168 | int checkboard(void) | |
169 | { | |
170 | printf("KARO TX25\n"); | |
171 | return 0; | |
172 | } |