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1 | /* | |
2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <asm/arch/clock.h> | |
10 | #include <asm/arch/crm_regs.h> | |
11 | #include <asm/arch/iomux.h> | |
12 | #include <asm/arch/imx-regs.h> | |
13 | #include <asm/arch/mx6-pins.h> | |
14 | #include <asm/arch/mxc_hdmi.h> | |
15 | #include <asm/arch/sys_proto.h> | |
16 | #include <asm/gpio.h> | |
17 | #include <asm/imx-common/iomux-v3.h> | |
18 | #include <asm/imx-common/boot_mode.h> | |
19 | #include <asm/io.h> | |
20 | #include <asm/sizes.h> | |
21 | #include <common.h> | |
22 | #include <fsl_esdhc.h> | |
23 | #include <ipu_pixfmt.h> | |
24 | #include <mmc.h> | |
25 | #include <miiphy.h> | |
26 | #include <netdev.h> | |
27 | #include <linux/fb.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
32 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
33 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
34 | ||
35 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | |
36 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | |
37 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
38 | ||
39 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
40 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
41 | ||
42 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) | |
43 | #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) | |
44 | #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) | |
45 | ||
46 | int dram_init(void) | |
47 | { | |
48 | gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; | |
49 | ||
50 | return 0; | |
51 | } | |
52 | ||
53 | static iomux_v3_cfg_t const uart1_pads[] = { | |
54 | MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
55 | MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
56 | }; | |
57 | ||
58 | iomux_v3_cfg_t const usdhc1_pads[] = { | |
59 | MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
60 | MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
61 | MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
62 | MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
63 | MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
64 | MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
65 | /* Carrier MicroSD Card Detect */ | |
66 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
67 | }; | |
68 | ||
69 | static iomux_v3_cfg_t const usdhc3_pads[] = { | |
70 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
71 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
72 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
73 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
74 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
75 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
76 | /* SOM MicroSD Card Detect */ | |
77 | MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
78 | }; | |
79 | ||
80 | static iomux_v3_cfg_t const enet_pads[] = { | |
81 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
82 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
83 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
84 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
85 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
86 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
87 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
88 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
89 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
90 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
91 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
92 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
93 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
94 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
95 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
96 | /* AR8031 PHY Reset */ | |
97 | MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
98 | }; | |
99 | ||
100 | static void setup_iomux_uart(void) | |
101 | { | |
102 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | |
103 | } | |
104 | ||
105 | static void setup_iomux_enet(void) | |
106 | { | |
107 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
108 | ||
109 | /* Reset AR8031 PHY */ | |
110 | gpio_direction_output(ETH_PHY_RESET, 0); | |
111 | udelay(500); | |
112 | gpio_set_value(ETH_PHY_RESET, 1); | |
113 | } | |
114 | ||
115 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { | |
116 | {USDHC3_BASE_ADDR}, | |
117 | {USDHC1_BASE_ADDR}, | |
118 | }; | |
119 | ||
120 | int board_mmc_getcd(struct mmc *mmc) | |
121 | { | |
122 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
123 | int ret = 0; | |
124 | ||
125 | switch (cfg->esdhc_base) { | |
126 | case USDHC1_BASE_ADDR: | |
127 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
128 | break; | |
129 | case USDHC3_BASE_ADDR: | |
130 | ret = !gpio_get_value(USDHC3_CD_GPIO); | |
131 | break; | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
137 | int board_mmc_init(bd_t *bis) | |
138 | { | |
139 | s32 status = 0; | |
140 | u32 index = 0; | |
141 | ||
142 | /* | |
143 | * Following map is done: | |
144 | * (U-boot device node) (Physical Port) | |
145 | * mmc0 SOM MicroSD | |
146 | * mmc1 Carrier board MicroSD | |
147 | */ | |
148 | for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { | |
149 | switch (index) { | |
150 | case 0: | |
151 | imx_iomux_v3_setup_multiple_pads( | |
152 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | |
153 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
154 | usdhc_cfg[0].max_bus_width = 4; | |
155 | gpio_direction_input(USDHC3_CD_GPIO); | |
156 | break; | |
157 | case 1: | |
158 | imx_iomux_v3_setup_multiple_pads( | |
159 | usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); | |
160 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
161 | usdhc_cfg[1].max_bus_width = 4; | |
162 | gpio_direction_input(USDHC1_CD_GPIO); | |
163 | break; | |
164 | default: | |
165 | printf("Warning: you configured more USDHC controllers" | |
166 | "(%d) then supported by the board (%d)\n", | |
167 | index + 1, CONFIG_SYS_FSL_USDHC_NUM); | |
168 | return status; | |
169 | } | |
170 | ||
171 | status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); | |
172 | } | |
173 | ||
174 | return status; | |
175 | } | |
176 | ||
177 | static int mx6_rgmii_rework(struct phy_device *phydev) | |
178 | { | |
179 | unsigned short val; | |
180 | ||
181 | /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ | |
182 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); | |
183 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); | |
184 | phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); | |
185 | ||
186 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); | |
187 | val &= 0xffe3; | |
188 | val |= 0x18; | |
189 | phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); | |
190 | ||
191 | /* introduce tx clock delay */ | |
192 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); | |
193 | val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); | |
194 | val |= 0x0100; | |
195 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | int board_phy_config(struct phy_device *phydev) | |
201 | { | |
202 | mx6_rgmii_rework(phydev); | |
203 | ||
204 | if (phydev->drv->config) | |
205 | phydev->drv->config(phydev); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | #if defined(CONFIG_VIDEO_IPUV3) | |
211 | static struct fb_videomode const hdmi = { | |
212 | .name = "HDMI", | |
213 | .refresh = 60, | |
214 | .xres = 1024, | |
215 | .yres = 768, | |
216 | .pixclock = 15385, | |
217 | .left_margin = 220, | |
218 | .right_margin = 40, | |
219 | .upper_margin = 21, | |
220 | .lower_margin = 7, | |
221 | .hsync_len = 60, | |
222 | .vsync_len = 10, | |
223 | .sync = FB_SYNC_EXT, | |
224 | .vmode = FB_VMODE_NONINTERLACED | |
225 | }; | |
226 | ||
227 | int board_video_skip(void) | |
228 | { | |
229 | int ret; | |
230 | ||
231 | ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); | |
232 | ||
233 | if (ret) { | |
234 | printf("HDMI cannot be configured: %d\n", ret); | |
235 | return ret; | |
236 | } | |
237 | ||
238 | imx_enable_hdmi_phy(); | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | static void setup_display(void) | |
244 | { | |
245 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
246 | int reg; | |
247 | ||
248 | enable_ipu_clock(); | |
249 | imx_setup_hdmi(); | |
250 | ||
251 | reg = readl(&mxc_ccm->chsccdr); | |
252 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | |
253 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
254 | writel(reg, &mxc_ccm->chsccdr); | |
255 | } | |
256 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
257 | ||
258 | int board_eth_init(bd_t *bis) | |
259 | { | |
260 | setup_iomux_enet(); | |
261 | ||
262 | return cpu_eth_init(bis); | |
263 | } | |
264 | ||
265 | int board_early_init_f(void) | |
266 | { | |
267 | setup_iomux_uart(); | |
268 | #if defined(CONFIG_VIDEO_IPUV3) | |
269 | setup_display(); | |
270 | #endif | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Do not overwrite the console | |
276 | * Use always serial for U-Boot console | |
277 | */ | |
278 | int overwrite_console(void) | |
279 | { | |
280 | return 1; | |
281 | } | |
282 | ||
283 | #ifdef CONFIG_CMD_BMODE | |
284 | static const struct boot_mode board_boot_modes[] = { | |
285 | /* 4 bit bus width */ | |
286 | {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
287 | {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, | |
288 | {NULL, 0}, | |
289 | }; | |
290 | #endif | |
291 | ||
292 | int board_late_init(void) | |
293 | { | |
294 | #ifdef CONFIG_CMD_BMODE | |
295 | add_board_boot_modes(board_boot_modes); | |
296 | #endif | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | int board_init(void) | |
302 | { | |
303 | /* address of boot parameters */ | |
304 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | int checkboard(void) | |
310 | { | |
311 | puts("Board: Wandboard\n"); | |
312 | ||
313 | return 0; | |
314 | } |