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Commit | Line | Data |
---|---|---|
1 | CONFIG_PPC=y | |
2 | CONFIG_SYS_TEXT_BASE=0xF0000000 | |
3 | CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 | |
4 | CONFIG_SYS_CLK_FREQ=66000000 | |
5 | CONFIG_MPC83xx=y | |
6 | CONFIG_HIGH_BATS=y | |
7 | CONFIG_TARGET_KMETER1=y | |
8 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y | |
9 | CONFIG_SYSTEM_PLL_VCO_DIV_4=y | |
10 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y | |
11 | CONFIG_CORE_PLL_RATIO_2_1=y | |
12 | CONFIG_QUICC_MULT_FACTOR_6=y | |
13 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
14 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
15 | CONFIG_LALE_TIMING_EARLIER=y | |
16 | CONFIG_LDP_PIN_MUX_STATE_0=y | |
17 | CONFIG_BAT0=y | |
18 | CONFIG_BAT0_NAME="SDRAM" | |
19 | CONFIG_BAT0_BASE=0x00000000 | |
20 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
21 | CONFIG_BAT0_ACCESS_RW=y | |
22 | CONFIG_BAT0_ICACHE_INHIBITED=y | |
23 | CONFIG_BAT0_ICACHE_GUARDED=y | |
24 | CONFIG_BAT0_DCACHE_INHIBITED=y | |
25 | CONFIG_BAT0_DCACHE_GUARDED=y | |
26 | CONFIG_BAT0_USER_MODE_VALID=y | |
27 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
28 | CONFIG_BAT1=y | |
29 | CONFIG_BAT1_NAME="IMMR" | |
30 | CONFIG_BAT1_BASE=0xE0000000 | |
31 | CONFIG_BAT1_LENGTH_4_MBYTES=y | |
32 | CONFIG_BAT1_ACCESS_RW=y | |
33 | CONFIG_BAT1_ICACHE_INHIBITED=y | |
34 | CONFIG_BAT1_ICACHE_GUARDED=y | |
35 | CONFIG_BAT1_DCACHE_INHIBITED=y | |
36 | CONFIG_BAT1_DCACHE_GUARDED=y | |
37 | CONFIG_BAT1_USER_MODE_VALID=y | |
38 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
39 | CONFIG_BAT2=y | |
40 | CONFIG_BAT2_NAME="KMBEC_FPGA" | |
41 | CONFIG_BAT2_BASE=0xE8000000 | |
42 | CONFIG_BAT2_LENGTH_128_MBYTES=y | |
43 | CONFIG_BAT2_ACCESS_RW=y | |
44 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y | |
45 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
46 | CONFIG_BAT2_DCACHE_GUARDED=y | |
47 | CONFIG_BAT2_USER_MODE_VALID=y | |
48 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
49 | CONFIG_BAT3=y | |
50 | CONFIG_BAT3_NAME="FLASH" | |
51 | CONFIG_BAT3_BASE=0xF0000000 | |
52 | CONFIG_BAT3_LENGTH_256_MBYTES=y | |
53 | CONFIG_BAT3_ACCESS_RW=y | |
54 | CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y | |
55 | CONFIG_BAT3_DCACHE_INHIBITED=y | |
56 | CONFIG_BAT3_DCACHE_GUARDED=y | |
57 | CONFIG_BAT3_USER_MODE_VALID=y | |
58 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
59 | CONFIG_BAT5=y | |
60 | CONFIG_BAT5_NAME="PAXE" | |
61 | CONFIG_BAT5_BASE=0xA0000000 | |
62 | CONFIG_BAT5_LENGTH_256_MBYTES=y | |
63 | CONFIG_BAT5_ACCESS_RW=y | |
64 | CONFIG_BAT5_ICACHE_MEMORYCOHERENCE=y | |
65 | CONFIG_BAT5_DCACHE_INHIBITED=y | |
66 | CONFIG_BAT5_DCACHE_GUARDED=y | |
67 | CONFIG_BAT5_USER_MODE_VALID=y | |
68 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y | |
69 | CONFIG_LBLAW0=y | |
70 | CONFIG_LBLAW0_BASE=0xF0000000 | |
71 | CONFIG_LBLAW0_NAME="FLASH" | |
72 | CONFIG_LBLAW0_LENGTH_256_MBYTES=y | |
73 | CONFIG_LBLAW1=y | |
74 | CONFIG_LBLAW1_BASE=0xE8000000 | |
75 | CONFIG_LBLAW1_NAME="KMBEC_FPGA" | |
76 | CONFIG_LBLAW1_LENGTH_128_MBYTES=y | |
77 | CONFIG_LBLAW3=y | |
78 | CONFIG_LBLAW3_BASE=0xA0000000 | |
79 | CONFIG_LBLAW3_NAME="PAXE" | |
80 | CONFIG_LBLAW3_LENGTH_512_MBYTES=y | |
81 | CONFIG_ELBC_BR0_OR0=y | |
82 | CONFIG_BR0_OR0_NAME="FLASH" | |
83 | CONFIG_BR0_OR0_BASE=0xF0000000 | |
84 | CONFIG_BR0_PORTSIZE_16BIT=y | |
85 | CONFIG_OR0_AM_256_MBYTES=y | |
86 | CONFIG_OR0_SCY_5=y | |
87 | CONFIG_OR0_CSNT_EARLIER=y | |
88 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y | |
89 | CONFIG_OR0_TRLX_RELAXED=y | |
90 | CONFIG_OR0_EAD_EXTRA=y | |
91 | CONFIG_ELBC_BR1_OR1=y | |
92 | CONFIG_BR1_OR1_NAME="KMBEC_FPGA" | |
93 | CONFIG_BR1_OR1_BASE=0xE8000000 | |
94 | CONFIG_OR1_AM_64_MBYTES=y | |
95 | CONFIG_OR1_SCY_2=y | |
96 | CONFIG_OR1_CSNT_EARLIER=y | |
97 | CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y | |
98 | CONFIG_OR1_TRLX_RELAXED=y | |
99 | CONFIG_OR1_EAD_EXTRA=y | |
100 | CONFIG_ELBC_BR3_OR3=y | |
101 | CONFIG_BR3_OR3_NAME="PAXE" | |
102 | CONFIG_BR3_OR3_BASE=0xA0000000 | |
103 | CONFIG_OR3_AM_256_MBYTES=y | |
104 | CONFIG_OR3_SCY_2=y | |
105 | CONFIG_OR3_CSNT_EARLIER=y | |
106 | CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y | |
107 | CONFIG_OR3_TRLX_RELAXED=y | |
108 | CONFIG_OR3_EAD_EXTRA=y | |
109 | CONFIG_HID0_FINAL_EMCP=y | |
110 | CONFIG_HID0_FINAL_ICE=y | |
111 | CONFIG_HID2_HBE=y | |
112 | CONFIG_ACR_PIPE_DEP_4=y | |
113 | CONFIG_ACR_RPTCNT_4=y | |
114 | CONFIG_ACR_APARK_MASTER=y | |
115 | CONFIG_ACR_PARKM_USB_I2C1_BOOT=y | |
116 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y | |
117 | CONFIG_LCRR_EADC_2=y | |
118 | CONFIG_LCRR_CLKDIV_4=y | |
119 | CONFIG_OF_BOARD_SETUP=y | |
120 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
121 | CONFIG_MISC_INIT_R=y | |
122 | CONFIG_VERSION_VARIABLE=y | |
123 | CONFIG_BOARD_EARLY_INIT_R=y | |
124 | CONFIG_LAST_STAGE_INIT=y | |
125 | CONFIG_HUSH_PARSER=y | |
126 | CONFIG_AUTOBOOT_KEYED=y | |
127 | CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" | |
128 | CONFIG_AUTOBOOT_STOP_STR=" " | |
129 | CONFIG_CMD_IMLS=y | |
130 | CONFIG_CMD_ASKENV=y | |
131 | CONFIG_CMD_GREPENV=y | |
132 | CONFIG_CMD_EEPROM=y | |
133 | CONFIG_CMD_I2C=y | |
134 | CONFIG_CMD_DHCP=y | |
135 | CONFIG_CMD_MII=y | |
136 | CONFIG_CMD_PING=y | |
137 | CONFIG_CMD_JFFS2=y | |
138 | CONFIG_CMD_MTDPARTS=y | |
139 | CONFIG_MTDIDS_DEFAULT="nor0=boot" | |
140 | CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" | |
141 | CONFIG_CMD_UBI=y | |
142 | # CONFIG_CMD_UBIFS is not set | |
143 | CONFIG_BOOTCOUNT_LIMIT=y | |
144 | CONFIG_BOOTCOUNT_BOOTLIMIT=3 | |
145 | # CONFIG_MMC is not set | |
146 | CONFIG_MTD_NOR_FLASH=y | |
147 | CONFIG_MTD_DEVICE=y | |
148 | CONFIG_FLASH_CFI_DRIVER=y | |
149 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
150 | CONFIG_FLASH_CFI_MTD=y | |
151 | CONFIG_SYS_FLASH_PROTECTION=y | |
152 | CONFIG_SYS_FLASH_CFI=y | |
153 | # CONFIG_PCI is not set | |
154 | CONFIG_QE=y | |
155 | CONFIG_SYS_NS16550=y | |
156 | CONFIG_OF_LIBFDT=y |