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Commit | Line | Data |
---|---|---|
1 | CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. | |
2 | CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. | |
3 | CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V. | |
4 | ||
5 | Accessing ESDHC registers can be determined by ESDHC IP's endian | |
6 | mode or processor's endian mode. |