]> git.ipfire.org Git - thirdparty/u-boot.git/blame_incremental - drivers/clk/rockchip/clk_rk3288.c
projects / thirdparty / u-boot.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
common: Drop linux/stringify.h from common header
[thirdparty/u-boot.git] / drivers / clk / rockchip / clk_rk3288.c
... / ...
CommitLineData
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2015 Google, Inc
4 */
5
6#include <common.h>
7#include <bitfield.h>
8#include <clk-uclass.h>
9#include <div64.h>
10#include <dm.h>
11#include <dt-structs.h>
12#include <errno.h>
13#include <log.h>
14#include <malloc.h>
15#include <mapmem.h>
16#include <syscon.h>
17#include <asm/io.h>
18#include <asm/arch-rockchip/clock.h>
19#include <asm/arch-rockchip/cru.h>
20#include <asm/arch-rockchip/grf_rk3288.h>
21#include <asm/arch-rockchip/hardware.h>
22#include <dt-bindings/clock/rk3288-cru.h>
23#include <dm/device-internal.h>
24#include <dm/lists.h>
25#include <dm/uclass-internal.h>
26#include <linux/err.h>
27#include <linux/log2.h>
28#include <linux/stringify.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32struct rk3288_clk_plat {
33#if CONFIG_IS_ENABLED(OF_PLATDATA)
34 struct dtd_rockchip_rk3288_cru dtd;
35#endif
36};
37
38struct pll_div {
39 u32 nr;
40 u32 nf;
41 u32 no;
42};
43
44enum {
45 VCO_MAX_HZ = 2200U * 1000000,
46 VCO_MIN_HZ = 440 * 1000000,
47 OUTPUT_MAX_HZ = 2200U * 1000000,
48 OUTPUT_MIN_HZ = 27500000,
49 FREF_MAX_HZ = 2200U * 1000000,
50 FREF_MIN_HZ = 269 * 1000,
51};
52
53enum {
54 /* PLL CON0 */
55 PLL_OD_MASK = 0x0f,
56
57 /* PLL CON1 */
58 PLL_NF_MASK = 0x1fff,
59
60 /* PLL CON2 */
61 PLL_BWADJ_MASK = 0x0fff,
62
63 /* PLL CON3 */
64 PLL_RESET_SHIFT = 5,
65
66 /* CLKSEL0 */
67 CORE_SEL_PLL_SHIFT = 15,
68 CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
69 A17_DIV_SHIFT = 8,
70 A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
71 MP_DIV_SHIFT = 4,
72 MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
73 M0_DIV_SHIFT = 0,
74 M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
75
76 /* CLKSEL1: pd bus clk pll sel: codec or general */
77 PD_BUS_SEL_PLL_MASK = 15,
78 PD_BUS_SEL_CPLL = 0,
79 PD_BUS_SEL_GPLL,
80
81 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
82 PD_BUS_PCLK_DIV_SHIFT = 12,
83 PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
84
85 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
86 PD_BUS_HCLK_DIV_SHIFT = 8,
87 PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
88
89 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
90 PD_BUS_ACLK_DIV0_SHIFT = 3,
91 PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
92 PD_BUS_ACLK_DIV1_SHIFT = 0,
93 PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
94
95 /*
96 * CLKSEL10
97 * peripheral bus pclk div:
98 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
99 */
100 PERI_SEL_PLL_SHIFT = 15,
101 PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
102 PERI_SEL_CPLL = 0,
103 PERI_SEL_GPLL,
104
105 PERI_PCLK_DIV_SHIFT = 12,
106 PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
107
108 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
109 PERI_HCLK_DIV_SHIFT = 8,
110 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
111
112 /*
113 * peripheral bus aclk div:
114 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
115 */
116 PERI_ACLK_DIV_SHIFT = 0,
117 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
118
119 /*
120 * CLKSEL24
121 * saradc_div_con:
122 * clk_saradc=24MHz/(saradc_div_con+1)
123 */
124 CLK_SARADC_DIV_CON_SHIFT = 8,
125 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
126 CLK_SARADC_DIV_CON_WIDTH = 8,
127
128 SOCSTS_DPLL_LOCK = 1 << 5,
129 SOCSTS_APLL_LOCK = 1 << 6,
130 SOCSTS_CPLL_LOCK = 1 << 7,
131 SOCSTS_GPLL_LOCK = 1 << 8,
132 SOCSTS_NPLL_LOCK = 1 << 9,
133};
134
135#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
136
137#define PLL_DIVISORS(hz, _nr, _no) {\
138 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
139 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
140 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
141 "divisors on line " __stringify(__LINE__));
142
143/* Keep divisors as low as possible to reduce jitter and power usage */
144static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
145static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
146static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
147
148static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
149 const struct pll_div *div)
150{
151 int pll_id = rk_pll_id(clk_id);
152 struct rk3288_pll *pll = &cru->pll[pll_id];
153 /* All PLLs have same VCO and output frequency range restrictions. */
154 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
155 uint output_hz = vco_hz / div->no;
156
157 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
158 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
159 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
160 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
161 (div->no == 1 || !(div->no % 2)));
162
163 /* enter reset */
164 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
165
166 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
167 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
168 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
169 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
170
171 udelay(10);
172
173 /* return from reset */
174 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
175
176 return 0;
177}
178
179static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
180 unsigned int hz)
181{
182 static const struct pll_div dpll_cfg[] = {
183 {.nf = 25, .nr = 2, .no = 1},
184 {.nf = 400, .nr = 9, .no = 2},
185 {.nf = 500, .nr = 9, .no = 2},
186 {.nf = 100, .nr = 3, .no = 1},
187 };
188 int cfg;
189
190 switch (hz) {
191 case 300000000:
192 cfg = 0;
193 break;
194 case 533000000: /* actually 533.3P MHz */
195 cfg = 1;
196 break;
197 case 666000000: /* actually 666.6P MHz */
198 cfg = 2;
199 break;
200 case 800000000:
201 cfg = 3;
202 break;
203 default:
204 debug("Unsupported SDRAM frequency");
205 return -EINVAL;
206 }
207
208 /* pll enter slow-mode */
209 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
210 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
211
212 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
213
214 /* wait for pll lock */
215 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
216 udelay(1);
217
218 /* PLL enter normal-mode */
219 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
220 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
221
222 return 0;
223}
224
225#ifndef CONFIG_SPL_BUILD
226#define VCO_MAX_KHZ 2200000
227#define VCO_MIN_KHZ 440000
228#define FREF_MAX_KHZ 2200000
229#define FREF_MIN_KHZ 269
230
231static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
232{
233 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
234 uint fref_khz;
235 uint diff_khz, best_diff_khz;
236 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
237 uint vco_khz;
238 uint no = 1;
239 uint freq_khz = freq_hz / 1000;
240
241 if (!freq_hz) {
242 printf("%s: the frequency can not be 0 Hz\n", __func__);
243 return -EINVAL;
244 }
245
246 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
247 if (ext_div) {
248 *ext_div = DIV_ROUND_UP(no, max_no);
249 no = DIV_ROUND_UP(no, *ext_div);
250 }
251
252 /* only even divisors (and 1) are supported */
253 if (no > 1)
254 no = DIV_ROUND_UP(no, 2) * 2;
255
256 vco_khz = freq_khz * no;
257 if (ext_div)
258 vco_khz *= *ext_div;
259
260 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
261 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
262 __func__, freq_hz);
263 return -1;
264 }
265
266 div->no = no;
267
268 best_diff_khz = vco_khz;
269 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
270 fref_khz = ref_khz / nr;
271 if (fref_khz < FREF_MIN_KHZ)
272 break;
273 if (fref_khz > FREF_MAX_KHZ)
274 continue;
275
276 nf = vco_khz / fref_khz;
277 if (nf >= max_nf)
278 continue;
279 diff_khz = vco_khz - nf * fref_khz;
280 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
281 nf++;
282 diff_khz = fref_khz - diff_khz;
283 }
284
285 if (diff_khz >= best_diff_khz)
286 continue;
287
288 best_diff_khz = diff_khz;
289 div->nr = nr;
290 div->nf = nf;
291 }
292
293 if (best_diff_khz > 4 * 1000) {
294 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
295 __func__, freq_hz, best_diff_khz * 1000);
296 return -EINVAL;
297 }
298
299 return 0;
300}
301
302static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
303{
304 ulong ret;
305
306 /*
307 * The gmac clock can be derived either from an external clock
308 * or can be generated from internally by a divider from SCLK_MAC.
309 */
310 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
311 /* An external clock will always generate the right rate... */
312 ret = freq;
313 } else {
314 u32 con = readl(&cru->cru_clksel_con[21]);
315 ulong pll_rate;
316 u8 div;
317
318 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
319 EMAC_PLL_SELECT_GENERAL)
320 pll_rate = GPLL_HZ;
321 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
322 EMAC_PLL_SELECT_CODEC)
323 pll_rate = CPLL_HZ;
324 else
325 pll_rate = NPLL_HZ;
326
327 div = DIV_ROUND_UP(pll_rate, freq) - 1;
328 if (div <= 0x1f)
329 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
330 div << MAC_DIV_CON_SHIFT);
331 else
332 debug("Unsupported div for gmac:%d\n", div);
333
334 return DIV_TO_RATE(pll_rate, div);
335 }
336
337 return ret;
338}
339
340static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
341 int periph, unsigned int rate_hz)
342{
343 struct pll_div npll_config = {0};
344 u32 lcdc_div;
345 int ret;
346
347 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
348 if (ret)
349 return ret;
350
351 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
352 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
353 rkclk_set_pll(cru, CLK_NEW, &npll_config);
354
355 /* waiting for pll lock */
356 while (1) {
357 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
358 break;
359 udelay(1);
360 }
361
362 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
363 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
364
365 /* vop dclk source clk: npll,dclk_div: 1 */
366 switch (periph) {
367 case DCLK_VOP0:
368 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
369 (lcdc_div - 1) << 8 | 2 << 0);
370 break;
371 case DCLK_VOP1:
372 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
373 (lcdc_div - 1) << 8 | 2 << 6);
374 break;
375 }
376
377 return 0;
378}
379
380static u32 rockchip_clk_gcd(u32 a, u32 b)
381{
382 while (b != 0) {
383 int r = b;
384
385 b = a % b;
386 a = r;
387 }
388 return a;
389}
390
391static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
392{
393 unsigned long long rate;
394 uint val;
395 int n, d;
396
397 val = readl(&cru->cru_clksel_con[8]);
398 n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
399 d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
400
401 rate = (unsigned long long)gclk_rate * n;
402 do_div(rate, d);
403
404 return (ulong)rate;
405}
406
407static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
408 uint freq)
409{
410 int n, d;
411 int v;
412
413 /* set frac divider */
414 v = rockchip_clk_gcd(gclk_rate, freq);
415 n = gclk_rate / v;
416 d = freq / v;
417 assert(freq == gclk_rate / n * d);
418 writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
419 &cru->cru_clksel_con[8]);
420
421 return rockchip_i2s_get_clk(cru, gclk_rate);
422}
423#endif /* CONFIG_SPL_BUILD */
424
425static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
426{
427 u32 aclk_div;
428 u32 hclk_div;
429 u32 pclk_div;
430
431 /* pll enter slow-mode */
432 rk_clrsetreg(&cru->cru_mode_con,
433 GPLL_MODE_MASK | CPLL_MODE_MASK,
434 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
435 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
436
437 /* init pll */
438 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
439 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
440
441 /* waiting for pll lock */
442 while ((readl(&grf->soc_status[1]) &
443 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
444 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
445 udelay(1);
446
447 /*
448 * pd_bus clock pll source selection and
449 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
450 */
451 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
452 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
453 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
454 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
455 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
456
457 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
458 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
459 PD_BUS_ACLK_HZ && pclk_div < 0x7);
460
461 rk_clrsetreg(&cru->cru_clksel_con[1],
462 PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
463 PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
464 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
465 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
466 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
467 0 << 0);
468
469 /*
470 * peri clock pll source selection and
471 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
472 */
473 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
474 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
475
476 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
477 assert((1 << hclk_div) * PERI_HCLK_HZ ==
478 PERI_ACLK_HZ && (hclk_div < 0x4));
479
480 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
481 assert((1 << pclk_div) * PERI_PCLK_HZ ==
482 PERI_ACLK_HZ && (pclk_div < 0x4));
483
484 rk_clrsetreg(&cru->cru_clksel_con[10],
485 PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
486 PERI_ACLK_DIV_MASK,
487 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
488 pclk_div << PERI_PCLK_DIV_SHIFT |
489 hclk_div << PERI_HCLK_DIV_SHIFT |
490 aclk_div << PERI_ACLK_DIV_SHIFT);
491
492 /* PLL enter normal-mode */
493 rk_clrsetreg(&cru->cru_mode_con,
494 GPLL_MODE_MASK | CPLL_MODE_MASK,
495 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
496 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
497}
498
499void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
500{
501 /* pll enter slow-mode */
502 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
503 APLL_MODE_SLOW << APLL_MODE_SHIFT);
504
505 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
506
507 /* waiting for pll lock */
508 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
509 udelay(1);
510
511 /*
512 * core clock pll source selection and
513 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
514 * core clock select apll, apll clk = 1800MHz
515 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
516 */
517 rk_clrsetreg(&cru->cru_clksel_con[0],
518 CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
519 M0_DIV_MASK,
520 0 << A17_DIV_SHIFT |
521 3 << MP_DIV_SHIFT |
522 1 << M0_DIV_SHIFT);
523
524 /*
525 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
526 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
527 */
528 rk_clrsetreg(&cru->cru_clksel_con[37],
529 CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
530 PCLK_CORE_DBG_DIV_MASK,
531 1 << CLK_L2RAM_DIV_SHIFT |
532 3 << ATCLK_CORE_DIV_CON_SHIFT |
533 3 << PCLK_CORE_DBG_DIV_SHIFT);
534
535 /* PLL enter normal-mode */
536 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
537 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
538}
539
540/* Get pll rate by id */
541static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
542 enum rk_clk_id clk_id)
543{
544 uint32_t nr, no, nf;
545 uint32_t con;
546 int pll_id = rk_pll_id(clk_id);
547 struct rk3288_pll *pll = &cru->pll[pll_id];
548 static u8 clk_shift[CLK_COUNT] = {
549 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
550 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
551 };
552 uint shift;
553
554 con = readl(&cru->cru_mode_con);
555 shift = clk_shift[clk_id];
556 switch ((con >> shift) & CRU_MODE_MASK) {
557 case APLL_MODE_SLOW:
558 return OSC_HZ;
559 case APLL_MODE_NORMAL:
560 /* normal mode */
561 con = readl(&pll->con0);
562 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
563 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
564 con = readl(&pll->con1);
565 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
566
567 return (24 * nf / (nr * no)) * 1000000;
568 case APLL_MODE_DEEP:
569 default:
570 return 32768;
571 }
572}
573
574static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
575 int periph)
576{
577 uint src_rate;
578 uint div, mux;
579 u32 con;
580
581 switch (periph) {
582 case HCLK_EMMC:
583 case SCLK_EMMC:
584 con = readl(&cru->cru_clksel_con[12]);
585 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
586 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
587 break;
588 case HCLK_SDMMC:
589 case SCLK_SDMMC:
590 con = readl(&cru->cru_clksel_con[11]);
591 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
592 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
593 break;
594 case HCLK_SDIO0:
595 case SCLK_SDIO0:
596 con = readl(&cru->cru_clksel_con[12]);
597 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
598 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
599 break;
600 default:
601 return -EINVAL;
602 }
603
604 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
605 return DIV_TO_RATE(src_rate, div);
606}
607
608static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
609 int periph, uint freq)
610{
611 int src_clk_div;
612 int mux;
613
614 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
615 /* mmc clock default div 2 internal, need provide double in cru */
616 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
617
618 if (src_clk_div > 0x3f) {
619 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
620 assert(src_clk_div < 0x40);
621 mux = EMMC_PLL_SELECT_24MHZ;
622 assert((int)EMMC_PLL_SELECT_24MHZ ==
623 (int)MMC0_PLL_SELECT_24MHZ);
624 } else {
625 mux = EMMC_PLL_SELECT_GENERAL;
626 assert((int)EMMC_PLL_SELECT_GENERAL ==
627 (int)MMC0_PLL_SELECT_GENERAL);
628 }
629 switch (periph) {
630 case HCLK_EMMC:
631 case SCLK_EMMC:
632 rk_clrsetreg(&cru->cru_clksel_con[12],
633 EMMC_PLL_MASK | EMMC_DIV_MASK,
634 mux << EMMC_PLL_SHIFT |
635 (src_clk_div - 1) << EMMC_DIV_SHIFT);
636 break;
637 case HCLK_SDMMC:
638 case SCLK_SDMMC:
639 rk_clrsetreg(&cru->cru_clksel_con[11],
640 MMC0_PLL_MASK | MMC0_DIV_MASK,
641 mux << MMC0_PLL_SHIFT |
642 (src_clk_div - 1) << MMC0_DIV_SHIFT);
643 break;
644 case HCLK_SDIO0:
645 case SCLK_SDIO0:
646 rk_clrsetreg(&cru->cru_clksel_con[12],
647 SDIO0_PLL_MASK | SDIO0_DIV_MASK,
648 mux << SDIO0_PLL_SHIFT |
649 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
650 break;
651 default:
652 return -EINVAL;
653 }
654
655 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
656}
657
658static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
659 int periph)
660{
661 uint div, mux;
662 u32 con;
663
664 switch (periph) {
665 case SCLK_SPI0:
666 con = readl(&cru->cru_clksel_con[25]);
667 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
668 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
669 break;
670 case SCLK_SPI1:
671 con = readl(&cru->cru_clksel_con[25]);
672 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
673 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
674 break;
675 case SCLK_SPI2:
676 con = readl(&cru->cru_clksel_con[39]);
677 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
678 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
679 break;
680 default:
681 return -EINVAL;
682 }
683 assert(mux == SPI0_PLL_SELECT_GENERAL);
684
685 return DIV_TO_RATE(gclk_rate, div);
686}
687
688static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
689 int periph, uint freq)
690{
691 int src_clk_div;
692
693 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
694 src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
695 assert(src_clk_div < 128);
696 switch (periph) {
697 case SCLK_SPI0:
698 rk_clrsetreg(&cru->cru_clksel_con[25],
699 SPI0_PLL_MASK | SPI0_DIV_MASK,
700 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
701 src_clk_div << SPI0_DIV_SHIFT);
702 break;
703 case SCLK_SPI1:
704 rk_clrsetreg(&cru->cru_clksel_con[25],
705 SPI1_PLL_MASK | SPI1_DIV_MASK,
706 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
707 src_clk_div << SPI1_DIV_SHIFT);
708 break;
709 case SCLK_SPI2:
710 rk_clrsetreg(&cru->cru_clksel_con[39],
711 SPI2_PLL_MASK | SPI2_DIV_MASK,
712 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
713 src_clk_div << SPI2_DIV_SHIFT);
714 break;
715 default:
716 return -EINVAL;
717 }
718
719 return rockchip_spi_get_clk(cru, gclk_rate, periph);
720}
721
722static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
723{
724 u32 div, val;
725
726 val = readl(&cru->cru_clksel_con[24]);
727 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
728 CLK_SARADC_DIV_CON_WIDTH);
729
730 return DIV_TO_RATE(OSC_HZ, div);
731}
732
733static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
734{
735 int src_clk_div;
736
737 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
738 assert(src_clk_div < 128);
739
740 rk_clrsetreg(&cru->cru_clksel_con[24],
741 CLK_SARADC_DIV_CON_MASK,
742 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
743
744 return rockchip_saradc_get_clk(cru);
745}
746
747static ulong rk3288_clk_get_rate(struct clk *clk)
748{
749 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
750 ulong new_rate, gclk_rate;
751
752 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
753 switch (clk->id) {
754 case 0 ... 63:
755 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
756 break;
757 case HCLK_EMMC:
758 case HCLK_SDMMC:
759 case HCLK_SDIO0:
760 case SCLK_EMMC:
761 case SCLK_SDMMC:
762 case SCLK_SDIO0:
763 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
764 break;
765 case SCLK_SPI0:
766 case SCLK_SPI1:
767 case SCLK_SPI2:
768 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
769 break;
770 case PCLK_I2C0:
771 case PCLK_I2C1:
772 case PCLK_I2C2:
773 case PCLK_I2C3:
774 case PCLK_I2C4:
775 case PCLK_I2C5:
776 return gclk_rate;
777 case PCLK_PWM:
778 return PD_BUS_PCLK_HZ;
779 case SCLK_SARADC:
780 new_rate = rockchip_saradc_get_clk(priv->cru);
781 break;
782 default:
783 return -ENOENT;
784 }
785
786 return new_rate;
787}
788
789static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
790{
791 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
792 struct rockchip_cru *cru = priv->cru;
793 ulong new_rate, gclk_rate;
794
795 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
796 switch (clk->id) {
797 case PLL_APLL:
798 /* We only support a fixed rate here */
799 if (rate != 1800000000)
800 return -EINVAL;
801 rk3288_clk_configure_cpu(priv->cru, priv->grf);
802 new_rate = rate;
803 break;
804 case CLK_DDR:
805 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
806 break;
807 case HCLK_EMMC:
808 case HCLK_SDMMC:
809 case HCLK_SDIO0:
810 case SCLK_EMMC:
811 case SCLK_SDMMC:
812 case SCLK_SDIO0:
813 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
814 break;
815 case SCLK_SPI0:
816 case SCLK_SPI1:
817 case SCLK_SPI2:
818 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
819 break;
820#ifndef CONFIG_SPL_BUILD
821 case SCLK_I2S0:
822 new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
823 break;
824 case SCLK_MAC:
825 new_rate = rockchip_mac_set_clk(priv->cru, rate);
826 break;
827 case DCLK_VOP0:
828 case DCLK_VOP1:
829 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
830 break;
831 case SCLK_EDP_24M:
832 /* clk_edp_24M source: 24M */
833 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
834
835 /* rst edp */
836 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
837 udelay(1);
838 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
839 new_rate = rate;
840 break;
841 case ACLK_VOP0:
842 case ACLK_VOP1: {
843 u32 div;
844
845 /* vop aclk source clk: cpll */
846 div = CPLL_HZ / rate;
847 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
848
849 switch (clk->id) {
850 case ACLK_VOP0:
851 rk_clrsetreg(&cru->cru_clksel_con[31],
852 3 << 6 | 0x1f << 0,
853 0 << 6 | (div - 1) << 0);
854 break;
855 case ACLK_VOP1:
856 rk_clrsetreg(&cru->cru_clksel_con[31],
857 3 << 14 | 0x1f << 8,
858 0 << 14 | (div - 1) << 8);
859 break;
860 }
861 new_rate = rate;
862 break;
863 }
864 case PCLK_HDMI_CTRL:
865 /* enable pclk hdmi ctrl */
866 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
867
868 /* software reset hdmi */
869 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
870 udelay(1);
871 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
872 new_rate = rate;
873 break;
874#endif
875 case SCLK_SARADC:
876 new_rate = rockchip_saradc_set_clk(priv->cru, rate);
877 break;
878 case PLL_GPLL:
879 case PLL_CPLL:
880 case PLL_NPLL:
881 case ACLK_CPU:
882 case HCLK_CPU:
883 case PCLK_CPU:
884 case ACLK_PERI:
885 case HCLK_PERI:
886 case PCLK_PERI:
887 case SCLK_UART0:
888 return 0;
889 default:
890 return -ENOENT;
891 }
892
893 return new_rate;
894}
895
896static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
897{
898 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
899 struct rockchip_cru *cru = priv->cru;
900 const char *clock_output_name;
901 int ret;
902
903 /*
904 * If the requested parent is in the same clock-controller and
905 * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
906 * clock.
907 */
908 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
909 debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
910 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
911 return 0;
912 }
913
914 /*
915 * Otherwise, we need to check the clock-output-names of the
916 * requested parent to see if the requested id is "ext_gmac".
917 */
918 ret = dev_read_string_index(parent->dev, "clock-output-names",
919 parent->id, &clock_output_name);
920 if (ret < 0)
921 return -ENODATA;
922
923 /* If this is "ext_gmac", switch to the external clock input */
924 if (!strcmp(clock_output_name, "ext_gmac")) {
925 debug("%s: switching GMAC to external clock\n", __func__);
926 rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
927 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
928 return 0;
929 }
930
931 return -EINVAL;
932}
933
934static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
935{
936 switch (clk->id) {
937 case SCLK_MAC:
938 return rk3288_gmac_set_parent(clk, parent);
939 case SCLK_USBPHY480M_SRC:
940 return 0;
941 }
942
943 debug("%s: unsupported clk %ld\n", __func__, clk->id);
944 return -ENOENT;
945}
946
947static struct clk_ops rk3288_clk_ops = {
948 .get_rate = rk3288_clk_get_rate,
949 .set_rate = rk3288_clk_set_rate,
950#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
951 .set_parent = rk3288_clk_set_parent,
952#endif
953};
954
955static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
956{
957#if !CONFIG_IS_ENABLED(OF_PLATDATA)
958 struct rk3288_clk_priv *priv = dev_get_priv(dev);
959
960 priv->cru = dev_read_addr_ptr(dev);
961#endif
962
963 return 0;
964}
965
966static int rk3288_clk_probe(struct udevice *dev)
967{
968 struct rk3288_clk_priv *priv = dev_get_priv(dev);
969 bool init_clocks = false;
970
971 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
972 if (IS_ERR(priv->grf))
973 return PTR_ERR(priv->grf);
974#ifdef CONFIG_SPL_BUILD
975#if CONFIG_IS_ENABLED(OF_PLATDATA)
976 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
977
978 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
979#endif
980 init_clocks = true;
981#endif
982 if (!(gd->flags & GD_FLG_RELOC)) {
983 u32 reg;
984
985 /*
986 * Init clocks in U-Boot proper if the NPLL is runnning. This
987 * indicates that a previous boot loader set up the clocks, so
988 * we need to redo it. U-Boot's SPL does not set this clock.
989 */
990 reg = readl(&priv->cru->cru_mode_con);
991 if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
992 NPLL_MODE_NORMAL)
993 init_clocks = true;
994 }
995
996 if (init_clocks)
997 rkclk_init(priv->cru, priv->grf);
998
999 return 0;
1000}
1001
1002static int rk3288_clk_bind(struct udevice *dev)
1003{
1004 int ret;
1005 struct udevice *sys_child;
1006 struct sysreset_reg *priv;
1007
1008 /* The reset driver does not have a device node, so bind it here */
1009 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1010 &sys_child);
1011 if (ret) {
1012 debug("Warning: No sysreset driver: ret=%d\n", ret);
1013 } else {
1014 priv = malloc(sizeof(struct sysreset_reg));
1015 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
1016 cru_glb_srst_fst_value);
1017 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
1018 cru_glb_srst_snd_value);
1019 sys_child->priv = priv;
1020 }
1021
1022#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
1023 ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
1024 ret = rockchip_reset_bind(dev, ret, 12);
1025 if (ret)
1026 debug("Warning: software reset driver bind faile\n");
1027#endif
1028
1029 return 0;
1030}
1031
1032static const struct udevice_id rk3288_clk_ids[] = {
1033 { .compatible = "rockchip,rk3288-cru" },
1034 { }
1035};
1036
1037U_BOOT_DRIVER(rockchip_rk3288_cru) = {
1038 .name = "rockchip_rk3288_cru",
1039 .id = UCLASS_CLK,
1040 .of_match = rk3288_clk_ids,
1041 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
1042 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
1043 .ops = &rk3288_clk_ops,
1044 .bind = rk3288_clk_bind,
1045 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
1046 .probe = rk3288_clk_probe,
1047};
"Das U-Boot" Source Tree