]> git.ipfire.org Git - thirdparty/linux.git/blame_incremental - drivers/iommu/amd_iommu_init.c
projects / thirdparty / linux.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
iommu/amd: Set exclusion range correctly
[thirdparty/linux.git] / drivers / iommu / amd_iommu_init.c
... / ...
CommitLineData
1/*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#define pr_fmt(fmt) "AMD-Vi: " fmt
21#define dev_fmt(fmt) pr_fmt(fmt)
22
23#include <linux/pci.h>
24#include <linux/acpi.h>
25#include <linux/list.h>
26#include <linux/bitmap.h>
27#include <linux/slab.h>
28#include <linux/syscore_ops.h>
29#include <linux/interrupt.h>
30#include <linux/msi.h>
31#include <linux/amd-iommu.h>
32#include <linux/export.h>
33#include <linux/iommu.h>
34#include <linux/kmemleak.h>
35#include <linux/mem_encrypt.h>
36#include <asm/pci-direct.h>
37#include <asm/iommu.h>
38#include <asm/gart.h>
39#include <asm/x86_init.h>
40#include <asm/iommu_table.h>
41#include <asm/io_apic.h>
42#include <asm/irq_remapping.h>
43
44#include <linux/crash_dump.h>
45#include "amd_iommu_proto.h"
46#include "amd_iommu_types.h"
47#include "irq_remapping.h"
48
49/*
50 * definitions for the ACPI scanning code
51 */
52#define IVRS_HEADER_LENGTH 48
53
54#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
55#define ACPI_IVMD_TYPE_ALL 0x20
56#define ACPI_IVMD_TYPE 0x21
57#define ACPI_IVMD_TYPE_RANGE 0x22
58
59#define IVHD_DEV_ALL 0x01
60#define IVHD_DEV_SELECT 0x02
61#define IVHD_DEV_SELECT_RANGE_START 0x03
62#define IVHD_DEV_RANGE_END 0x04
63#define IVHD_DEV_ALIAS 0x42
64#define IVHD_DEV_ALIAS_RANGE 0x43
65#define IVHD_DEV_EXT_SELECT 0x46
66#define IVHD_DEV_EXT_SELECT_RANGE 0x47
67#define IVHD_DEV_SPECIAL 0x48
68#define IVHD_DEV_ACPI_HID 0xf0
69
70#define UID_NOT_PRESENT 0
71#define UID_IS_INTEGER 1
72#define UID_IS_CHARACTER 2
73
74#define IVHD_SPECIAL_IOAPIC 1
75#define IVHD_SPECIAL_HPET 2
76
77#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
78#define IVHD_FLAG_PASSPW_EN_MASK 0x02
79#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
80#define IVHD_FLAG_ISOC_EN_MASK 0x08
81
82#define IVMD_FLAG_EXCL_RANGE 0x08
83#define IVMD_FLAG_UNITY_MAP 0x01
84
85#define ACPI_DEVFLAG_INITPASS 0x01
86#define ACPI_DEVFLAG_EXTINT 0x02
87#define ACPI_DEVFLAG_NMI 0x04
88#define ACPI_DEVFLAG_SYSMGT1 0x10
89#define ACPI_DEVFLAG_SYSMGT2 0x20
90#define ACPI_DEVFLAG_LINT0 0x40
91#define ACPI_DEVFLAG_LINT1 0x80
92#define ACPI_DEVFLAG_ATSDIS 0x10000000
93
94#define LOOP_TIMEOUT 100000
95/*
96 * ACPI table definitions
97 *
98 * These data structures are laid over the table to parse the important values
99 * out of it.
100 */
101
102extern const struct iommu_ops amd_iommu_ops;
103
104/*
105 * structure describing one IOMMU in the ACPI table. Typically followed by one
106 * or more ivhd_entrys.
107 */
108struct ivhd_header {
109 u8 type;
110 u8 flags;
111 u16 length;
112 u16 devid;
113 u16 cap_ptr;
114 u64 mmio_phys;
115 u16 pci_seg;
116 u16 info;
117 u32 efr_attr;
118
119 /* Following only valid on IVHD type 11h and 40h */
120 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
121 u64 res;
122} __attribute__((packed));
123
124/*
125 * A device entry describing which devices a specific IOMMU translates and
126 * which requestor ids they use.
127 */
128struct ivhd_entry {
129 u8 type;
130 u16 devid;
131 u8 flags;
132 u32 ext;
133 u32 hidh;
134 u64 cid;
135 u8 uidf;
136 u8 uidl;
137 u8 uid;
138} __attribute__((packed));
139
140/*
141 * An AMD IOMMU memory definition structure. It defines things like exclusion
142 * ranges for devices and regions that should be unity mapped.
143 */
144struct ivmd_header {
145 u8 type;
146 u8 flags;
147 u16 length;
148 u16 devid;
149 u16 aux;
150 u64 resv;
151 u64 range_start;
152 u64 range_length;
153} __attribute__((packed));
154
155bool amd_iommu_dump;
156bool amd_iommu_irq_remap __read_mostly;
157
158int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
159static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
160
161static bool amd_iommu_detected;
162static bool __initdata amd_iommu_disabled;
163static int amd_iommu_target_ivhd_type;
164
165u16 amd_iommu_last_bdf; /* largest PCI device id we have
166 to handle */
167LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
168 we find in ACPI */
169bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
170
171LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
172 system */
173
174/* Array to assign indices to IOMMUs*/
175struct amd_iommu *amd_iommus[MAX_IOMMUS];
176
177/* Number of IOMMUs present in the system */
178static int amd_iommus_present;
179
180/* IOMMUs have a non-present cache? */
181bool amd_iommu_np_cache __read_mostly;
182bool amd_iommu_iotlb_sup __read_mostly = true;
183
184u32 amd_iommu_max_pasid __read_mostly = ~0;
185
186bool amd_iommu_v2_present __read_mostly;
187static bool amd_iommu_pc_present __read_mostly;
188
189bool amd_iommu_force_isolation __read_mostly;
190
191/*
192 * List of protection domains - used during resume
193 */
194LIST_HEAD(amd_iommu_pd_list);
195spinlock_t amd_iommu_pd_lock;
196
197/*
198 * Pointer to the device table which is shared by all AMD IOMMUs
199 * it is indexed by the PCI device id or the HT unit id and contains
200 * information about the domain the device belongs to as well as the
201 * page table root pointer.
202 */
203struct dev_table_entry *amd_iommu_dev_table;
204/*
205 * Pointer to a device table which the content of old device table
206 * will be copied to. It's only be used in kdump kernel.
207 */
208static struct dev_table_entry *old_dev_tbl_cpy;
209
210/*
211 * The alias table is a driver specific data structure which contains the
212 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
213 * More than one device can share the same requestor id.
214 */
215u16 *amd_iommu_alias_table;
216
217/*
218 * The rlookup table is used to find the IOMMU which is responsible
219 * for a specific device. It is also indexed by the PCI device id.
220 */
221struct amd_iommu **amd_iommu_rlookup_table;
222EXPORT_SYMBOL(amd_iommu_rlookup_table);
223
224/*
225 * This table is used to find the irq remapping table for a given device id
226 * quickly.
227 */
228struct irq_remap_table **irq_lookup_table;
229
230/*
231 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
232 * to know which ones are already in use.
233 */
234unsigned long *amd_iommu_pd_alloc_bitmap;
235
236static u32 dev_table_size; /* size of the device table */
237static u32 alias_table_size; /* size of the alias table */
238static u32 rlookup_table_size; /* size if the rlookup table */
239
240enum iommu_init_state {
241 IOMMU_START_STATE,
242 IOMMU_IVRS_DETECTED,
243 IOMMU_ACPI_FINISHED,
244 IOMMU_ENABLED,
245 IOMMU_PCI_INIT,
246 IOMMU_INTERRUPTS_EN,
247 IOMMU_DMA_OPS,
248 IOMMU_INITIALIZED,
249 IOMMU_NOT_FOUND,
250 IOMMU_INIT_ERROR,
251 IOMMU_CMDLINE_DISABLED,
252};
253
254/* Early ioapic and hpet maps from kernel command line */
255#define EARLY_MAP_SIZE 4
256static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
257static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
258static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
259
260static int __initdata early_ioapic_map_size;
261static int __initdata early_hpet_map_size;
262static int __initdata early_acpihid_map_size;
263
264static bool __initdata cmdline_maps;
265
266static enum iommu_init_state init_state = IOMMU_START_STATE;
267
268static int amd_iommu_enable_interrupts(void);
269static int __init iommu_go_to_state(enum iommu_init_state state);
270static void init_device_table_dma(void);
271
272static bool amd_iommu_pre_enabled = true;
273
274bool translation_pre_enabled(struct amd_iommu *iommu)
275{
276 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
277}
278EXPORT_SYMBOL(translation_pre_enabled);
279
280static void clear_translation_pre_enabled(struct amd_iommu *iommu)
281{
282 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
283}
284
285static void init_translation_status(struct amd_iommu *iommu)
286{
287 u64 ctrl;
288
289 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
290 if (ctrl & (1<<CONTROL_IOMMU_EN))
291 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
292}
293
294static inline void update_last_devid(u16 devid)
295{
296 if (devid > amd_iommu_last_bdf)
297 amd_iommu_last_bdf = devid;
298}
299
300static inline unsigned long tbl_size(int entry_size)
301{
302 unsigned shift = PAGE_SHIFT +
303 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
304
305 return 1UL << shift;
306}
307
308int amd_iommu_get_num_iommus(void)
309{
310 return amd_iommus_present;
311}
312
313/* Access to l1 and l2 indexed register spaces */
314
315static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
316{
317 u32 val;
318
319 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
320 pci_read_config_dword(iommu->dev, 0xfc, &val);
321 return val;
322}
323
324static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
325{
326 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
327 pci_write_config_dword(iommu->dev, 0xfc, val);
328 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
329}
330
331static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
332{
333 u32 val;
334
335 pci_write_config_dword(iommu->dev, 0xf0, address);
336 pci_read_config_dword(iommu->dev, 0xf4, &val);
337 return val;
338}
339
340static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
341{
342 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
343 pci_write_config_dword(iommu->dev, 0xf4, val);
344}
345
346/****************************************************************************
347 *
348 * AMD IOMMU MMIO register space handling functions
349 *
350 * These functions are used to program the IOMMU device registers in
351 * MMIO space required for that driver.
352 *
353 ****************************************************************************/
354
355/*
356 * This function set the exclusion range in the IOMMU. DMA accesses to the
357 * exclusion range are passed through untranslated
358 */
359static void iommu_set_exclusion_range(struct amd_iommu *iommu)
360{
361 u64 start = iommu->exclusion_start & PAGE_MASK;
362 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
363 u64 entry;
364
365 if (!iommu->exclusion_start)
366 return;
367
368 entry = start | MMIO_EXCL_ENABLE_MASK;
369 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
370 &entry, sizeof(entry));
371
372 entry = limit;
373 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
374 &entry, sizeof(entry));
375}
376
377/* Programs the physical address of the device table into the IOMMU hardware */
378static void iommu_set_device_table(struct amd_iommu *iommu)
379{
380 u64 entry;
381
382 BUG_ON(iommu->mmio_base == NULL);
383
384 entry = iommu_virt_to_phys(amd_iommu_dev_table);
385 entry |= (dev_table_size >> 12) - 1;
386 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
387 &entry, sizeof(entry));
388}
389
390/* Generic functions to enable/disable certain features of the IOMMU. */
391static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
392{
393 u64 ctrl;
394
395 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
396 ctrl |= (1ULL << bit);
397 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
398}
399
400static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
401{
402 u64 ctrl;
403
404 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
405 ctrl &= ~(1ULL << bit);
406 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
407}
408
409static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
410{
411 u64 ctrl;
412
413 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
414 ctrl &= ~CTRL_INV_TO_MASK;
415 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
416 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
417}
418
419/* Function to enable the hardware */
420static void iommu_enable(struct amd_iommu *iommu)
421{
422 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
423}
424
425static void iommu_disable(struct amd_iommu *iommu)
426{
427 /* Disable command buffer */
428 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
429
430 /* Disable event logging and event interrupts */
431 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
432 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
433
434 /* Disable IOMMU GA_LOG */
435 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
436 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
437
438 /* Disable IOMMU hardware itself */
439 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
440}
441
442/*
443 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
444 * the system has one.
445 */
446static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
447{
448 if (!request_mem_region(address, end, "amd_iommu")) {
449 pr_err("Can not reserve memory region %llx-%llx for mmio\n",
450 address, end);
451 pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
452 return NULL;
453 }
454
455 return (u8 __iomem *)ioremap_nocache(address, end);
456}
457
458static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
459{
460 if (iommu->mmio_base)
461 iounmap(iommu->mmio_base);
462 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
463}
464
465static inline u32 get_ivhd_header_size(struct ivhd_header *h)
466{
467 u32 size = 0;
468
469 switch (h->type) {
470 case 0x10:
471 size = 24;
472 break;
473 case 0x11:
474 case 0x40:
475 size = 40;
476 break;
477 }
478 return size;
479}
480
481/****************************************************************************
482 *
483 * The functions below belong to the first pass of AMD IOMMU ACPI table
484 * parsing. In this pass we try to find out the highest device id this
485 * code has to handle. Upon this information the size of the shared data
486 * structures is determined later.
487 *
488 ****************************************************************************/
489
490/*
491 * This function calculates the length of a given IVHD entry
492 */
493static inline int ivhd_entry_length(u8 *ivhd)
494{
495 u32 type = ((struct ivhd_entry *)ivhd)->type;
496
497 if (type < 0x80) {
498 return 0x04 << (*ivhd >> 6);
499 } else if (type == IVHD_DEV_ACPI_HID) {
500 /* For ACPI_HID, offset 21 is uid len */
501 return *((u8 *)ivhd + 21) + 22;
502 }
503 return 0;
504}
505
506/*
507 * After reading the highest device id from the IOMMU PCI capability header
508 * this function looks if there is a higher device id defined in the ACPI table
509 */
510static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
511{
512 u8 *p = (void *)h, *end = (void *)h;
513 struct ivhd_entry *dev;
514
515 u32 ivhd_size = get_ivhd_header_size(h);
516
517 if (!ivhd_size) {
518 pr_err("Unsupported IVHD type %#x\n", h->type);
519 return -EINVAL;
520 }
521
522 p += ivhd_size;
523 end += h->length;
524
525 while (p < end) {
526 dev = (struct ivhd_entry *)p;
527 switch (dev->type) {
528 case IVHD_DEV_ALL:
529 /* Use maximum BDF value for DEV_ALL */
530 update_last_devid(0xffff);
531 break;
532 case IVHD_DEV_SELECT:
533 case IVHD_DEV_RANGE_END:
534 case IVHD_DEV_ALIAS:
535 case IVHD_DEV_EXT_SELECT:
536 /* all the above subfield types refer to device ids */
537 update_last_devid(dev->devid);
538 break;
539 default:
540 break;
541 }
542 p += ivhd_entry_length(p);
543 }
544
545 WARN_ON(p != end);
546
547 return 0;
548}
549
550static int __init check_ivrs_checksum(struct acpi_table_header *table)
551{
552 int i;
553 u8 checksum = 0, *p = (u8 *)table;
554
555 for (i = 0; i < table->length; ++i)
556 checksum += p[i];
557 if (checksum != 0) {
558 /* ACPI table corrupt */
559 pr_err(FW_BUG "IVRS invalid checksum\n");
560 return -ENODEV;
561 }
562
563 return 0;
564}
565
566/*
567 * Iterate over all IVHD entries in the ACPI table and find the highest device
568 * id which we need to handle. This is the first of three functions which parse
569 * the ACPI table. So we check the checksum here.
570 */
571static int __init find_last_devid_acpi(struct acpi_table_header *table)
572{
573 u8 *p = (u8 *)table, *end = (u8 *)table;
574 struct ivhd_header *h;
575
576 p += IVRS_HEADER_LENGTH;
577
578 end += table->length;
579 while (p < end) {
580 h = (struct ivhd_header *)p;
581 if (h->type == amd_iommu_target_ivhd_type) {
582 int ret = find_last_devid_from_ivhd(h);
583
584 if (ret)
585 return ret;
586 }
587 p += h->length;
588 }
589 WARN_ON(p != end);
590
591 return 0;
592}
593
594/****************************************************************************
595 *
596 * The following functions belong to the code path which parses the ACPI table
597 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
598 * data structures, initialize the device/alias/rlookup table and also
599 * basically initialize the hardware.
600 *
601 ****************************************************************************/
602
603/*
604 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
605 * write commands to that buffer later and the IOMMU will execute them
606 * asynchronously
607 */
608static int __init alloc_command_buffer(struct amd_iommu *iommu)
609{
610 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
611 get_order(CMD_BUFFER_SIZE));
612
613 return iommu->cmd_buf ? 0 : -ENOMEM;
614}
615
616/*
617 * This function resets the command buffer if the IOMMU stopped fetching
618 * commands from it.
619 */
620void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
621{
622 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
623
624 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
625 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
626 iommu->cmd_buf_head = 0;
627 iommu->cmd_buf_tail = 0;
628
629 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
630}
631
632/*
633 * This function writes the command buffer address to the hardware and
634 * enables it.
635 */
636static void iommu_enable_command_buffer(struct amd_iommu *iommu)
637{
638 u64 entry;
639
640 BUG_ON(iommu->cmd_buf == NULL);
641
642 entry = iommu_virt_to_phys(iommu->cmd_buf);
643 entry |= MMIO_CMD_SIZE_512;
644
645 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
646 &entry, sizeof(entry));
647
648 amd_iommu_reset_cmd_buffer(iommu);
649}
650
651/*
652 * This function disables the command buffer
653 */
654static void iommu_disable_command_buffer(struct amd_iommu *iommu)
655{
656 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
657}
658
659static void __init free_command_buffer(struct amd_iommu *iommu)
660{
661 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
662}
663
664/* allocates the memory where the IOMMU will log its events to */
665static int __init alloc_event_buffer(struct amd_iommu *iommu)
666{
667 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
668 get_order(EVT_BUFFER_SIZE));
669
670 return iommu->evt_buf ? 0 : -ENOMEM;
671}
672
673static void iommu_enable_event_buffer(struct amd_iommu *iommu)
674{
675 u64 entry;
676
677 BUG_ON(iommu->evt_buf == NULL);
678
679 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
680
681 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
682 &entry, sizeof(entry));
683
684 /* set head and tail to zero manually */
685 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
686 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
687
688 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
689}
690
691/*
692 * This function disables the event log buffer
693 */
694static void iommu_disable_event_buffer(struct amd_iommu *iommu)
695{
696 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
697}
698
699static void __init free_event_buffer(struct amd_iommu *iommu)
700{
701 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
702}
703
704/* allocates the memory where the IOMMU will log its events to */
705static int __init alloc_ppr_log(struct amd_iommu *iommu)
706{
707 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
708 get_order(PPR_LOG_SIZE));
709
710 return iommu->ppr_log ? 0 : -ENOMEM;
711}
712
713static void iommu_enable_ppr_log(struct amd_iommu *iommu)
714{
715 u64 entry;
716
717 if (iommu->ppr_log == NULL)
718 return;
719
720 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
721
722 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
723 &entry, sizeof(entry));
724
725 /* set head and tail to zero manually */
726 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
727 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
728
729 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
730 iommu_feature_enable(iommu, CONTROL_PPR_EN);
731}
732
733static void __init free_ppr_log(struct amd_iommu *iommu)
734{
735 if (iommu->ppr_log == NULL)
736 return;
737
738 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
739}
740
741static void free_ga_log(struct amd_iommu *iommu)
742{
743#ifdef CONFIG_IRQ_REMAP
744 if (iommu->ga_log)
745 free_pages((unsigned long)iommu->ga_log,
746 get_order(GA_LOG_SIZE));
747 if (iommu->ga_log_tail)
748 free_pages((unsigned long)iommu->ga_log_tail,
749 get_order(8));
750#endif
751}
752
753static int iommu_ga_log_enable(struct amd_iommu *iommu)
754{
755#ifdef CONFIG_IRQ_REMAP
756 u32 status, i;
757
758 if (!iommu->ga_log)
759 return -EINVAL;
760
761 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
762
763 /* Check if already running */
764 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
765 return 0;
766
767 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
768 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
769
770 for (i = 0; i < LOOP_TIMEOUT; ++i) {
771 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
772 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
773 break;
774 }
775
776 if (i >= LOOP_TIMEOUT)
777 return -EINVAL;
778#endif /* CONFIG_IRQ_REMAP */
779 return 0;
780}
781
782#ifdef CONFIG_IRQ_REMAP
783static int iommu_init_ga_log(struct amd_iommu *iommu)
784{
785 u64 entry;
786
787 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
788 return 0;
789
790 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
791 get_order(GA_LOG_SIZE));
792 if (!iommu->ga_log)
793 goto err_out;
794
795 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
796 get_order(8));
797 if (!iommu->ga_log_tail)
798 goto err_out;
799
800 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
801 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
802 &entry, sizeof(entry));
803 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
804 (BIT_ULL(52)-1)) & ~7ULL;
805 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
806 &entry, sizeof(entry));
807 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
808 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
809
810 return 0;
811err_out:
812 free_ga_log(iommu);
813 return -EINVAL;
814}
815#endif /* CONFIG_IRQ_REMAP */
816
817static int iommu_init_ga(struct amd_iommu *iommu)
818{
819 int ret = 0;
820
821#ifdef CONFIG_IRQ_REMAP
822 /* Note: We have already checked GASup from IVRS table.
823 * Now, we need to make sure that GAMSup is set.
824 */
825 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
826 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
827 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
828
829 ret = iommu_init_ga_log(iommu);
830#endif /* CONFIG_IRQ_REMAP */
831
832 return ret;
833}
834
835static void iommu_enable_xt(struct amd_iommu *iommu)
836{
837#ifdef CONFIG_IRQ_REMAP
838 /*
839 * XT mode (32-bit APIC destination ID) requires
840 * GA mode (128-bit IRTE support) as a prerequisite.
841 */
842 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
843 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
844 iommu_feature_enable(iommu, CONTROL_XT_EN);
845#endif /* CONFIG_IRQ_REMAP */
846}
847
848static void iommu_enable_gt(struct amd_iommu *iommu)
849{
850 if (!iommu_feature(iommu, FEATURE_GT))
851 return;
852
853 iommu_feature_enable(iommu, CONTROL_GT_EN);
854}
855
856/* sets a specific bit in the device table entry. */
857static void set_dev_entry_bit(u16 devid, u8 bit)
858{
859 int i = (bit >> 6) & 0x03;
860 int _bit = bit & 0x3f;
861
862 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
863}
864
865static int get_dev_entry_bit(u16 devid, u8 bit)
866{
867 int i = (bit >> 6) & 0x03;
868 int _bit = bit & 0x3f;
869
870 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
871}
872
873
874static bool copy_device_table(void)
875{
876 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
877 struct dev_table_entry *old_devtb = NULL;
878 u32 lo, hi, devid, old_devtb_size;
879 phys_addr_t old_devtb_phys;
880 struct amd_iommu *iommu;
881 u16 dom_id, dte_v, irq_v;
882 gfp_t gfp_flag;
883 u64 tmp;
884
885 if (!amd_iommu_pre_enabled)
886 return false;
887
888 pr_warn("Translation is already enabled - trying to copy translation structures\n");
889 for_each_iommu(iommu) {
890 /* All IOMMUs should use the same device table with the same size */
891 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
892 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
893 entry = (((u64) hi) << 32) + lo;
894 if (last_entry && last_entry != entry) {
895 pr_err("IOMMU:%d should use the same dev table as others!\n",
896 iommu->index);
897 return false;
898 }
899 last_entry = entry;
900
901 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
902 if (old_devtb_size != dev_table_size) {
903 pr_err("The device table size of IOMMU:%d is not expected!\n",
904 iommu->index);
905 return false;
906 }
907 }
908
909 /*
910 * When SME is enabled in the first kernel, the entry includes the
911 * memory encryption mask(sme_me_mask), we must remove the memory
912 * encryption mask to obtain the true physical address in kdump kernel.
913 */
914 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
915
916 if (old_devtb_phys >= 0x100000000ULL) {
917 pr_err("The address of old device table is above 4G, not trustworthy!\n");
918 return false;
919 }
920 old_devtb = (sme_active() && is_kdump_kernel())
921 ? (__force void *)ioremap_encrypted(old_devtb_phys,
922 dev_table_size)
923 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
924
925 if (!old_devtb)
926 return false;
927
928 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
929 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
930 get_order(dev_table_size));
931 if (old_dev_tbl_cpy == NULL) {
932 pr_err("Failed to allocate memory for copying old device table!\n");
933 return false;
934 }
935
936 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
937 old_dev_tbl_cpy[devid] = old_devtb[devid];
938 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
939 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
940
941 if (dte_v && dom_id) {
942 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
943 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
944 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
945 /* If gcr3 table existed, mask it out */
946 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
947 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
948 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
949 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
950 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
951 tmp |= DTE_FLAG_GV;
952 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
953 }
954 }
955
956 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
957 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
958 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
959 if (irq_v && (int_ctl || int_tab_len)) {
960 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
961 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
962 pr_err("Wrong old irq remapping flag: %#x\n", devid);
963 return false;
964 }
965
966 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
967 }
968 }
969 memunmap(old_devtb);
970
971 return true;
972}
973
974void amd_iommu_apply_erratum_63(u16 devid)
975{
976 int sysmgt;
977
978 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
979 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
980
981 if (sysmgt == 0x01)
982 set_dev_entry_bit(devid, DEV_ENTRY_IW);
983}
984
985/* Writes the specific IOMMU for a device into the rlookup table */
986static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
987{
988 amd_iommu_rlookup_table[devid] = iommu;
989}
990
991/*
992 * This function takes the device specific flags read from the ACPI
993 * table and sets up the device table entry with that information
994 */
995static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
996 u16 devid, u32 flags, u32 ext_flags)
997{
998 if (flags & ACPI_DEVFLAG_INITPASS)
999 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
1000 if (flags & ACPI_DEVFLAG_EXTINT)
1001 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
1002 if (flags & ACPI_DEVFLAG_NMI)
1003 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
1004 if (flags & ACPI_DEVFLAG_SYSMGT1)
1005 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
1006 if (flags & ACPI_DEVFLAG_SYSMGT2)
1007 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
1008 if (flags & ACPI_DEVFLAG_LINT0)
1009 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
1010 if (flags & ACPI_DEVFLAG_LINT1)
1011 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
1012
1013 amd_iommu_apply_erratum_63(devid);
1014
1015 set_iommu_for_device(iommu, devid);
1016}
1017
1018static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1019{
1020 struct devid_map *entry;
1021 struct list_head *list;
1022
1023 if (type == IVHD_SPECIAL_IOAPIC)
1024 list = &ioapic_map;
1025 else if (type == IVHD_SPECIAL_HPET)
1026 list = &hpet_map;
1027 else
1028 return -EINVAL;
1029
1030 list_for_each_entry(entry, list, list) {
1031 if (!(entry->id == id && entry->cmd_line))
1032 continue;
1033
1034 pr_info("Command-line override present for %s id %d - ignoring\n",
1035 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1036
1037 *devid = entry->devid;
1038
1039 return 0;
1040 }
1041
1042 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1043 if (!entry)
1044 return -ENOMEM;
1045
1046 entry->id = id;
1047 entry->devid = *devid;
1048 entry->cmd_line = cmd_line;
1049
1050 list_add_tail(&entry->list, list);
1051
1052 return 0;
1053}
1054
1055static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1056 bool cmd_line)
1057{
1058 struct acpihid_map_entry *entry;
1059 struct list_head *list = &acpihid_map;
1060
1061 list_for_each_entry(entry, list, list) {
1062 if (strcmp(entry->hid, hid) ||
1063 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1064 !entry->cmd_line)
1065 continue;
1066
1067 pr_info("Command-line override for hid:%s uid:%s\n",
1068 hid, uid);
1069 *devid = entry->devid;
1070 return 0;
1071 }
1072
1073 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1074 if (!entry)
1075 return -ENOMEM;
1076
1077 memcpy(entry->uid, uid, strlen(uid));
1078 memcpy(entry->hid, hid, strlen(hid));
1079 entry->devid = *devid;
1080 entry->cmd_line = cmd_line;
1081 entry->root_devid = (entry->devid & (~0x7));
1082
1083 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
1084 entry->cmd_line ? "cmd" : "ivrs",
1085 entry->hid, entry->uid, entry->root_devid);
1086
1087 list_add_tail(&entry->list, list);
1088 return 0;
1089}
1090
1091static int __init add_early_maps(void)
1092{
1093 int i, ret;
1094
1095 for (i = 0; i < early_ioapic_map_size; ++i) {
1096 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1097 early_ioapic_map[i].id,
1098 &early_ioapic_map[i].devid,
1099 early_ioapic_map[i].cmd_line);
1100 if (ret)
1101 return ret;
1102 }
1103
1104 for (i = 0; i < early_hpet_map_size; ++i) {
1105 ret = add_special_device(IVHD_SPECIAL_HPET,
1106 early_hpet_map[i].id,
1107 &early_hpet_map[i].devid,
1108 early_hpet_map[i].cmd_line);
1109 if (ret)
1110 return ret;
1111 }
1112
1113 for (i = 0; i < early_acpihid_map_size; ++i) {
1114 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1115 early_acpihid_map[i].uid,
1116 &early_acpihid_map[i].devid,
1117 early_acpihid_map[i].cmd_line);
1118 if (ret)
1119 return ret;
1120 }
1121
1122 return 0;
1123}
1124
1125/*
1126 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1127 * it
1128 */
1129static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1130{
1131 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1132
1133 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1134 return;
1135
1136 if (iommu) {
1137 /*
1138 * We only can configure exclusion ranges per IOMMU, not
1139 * per device. But we can enable the exclusion range per
1140 * device. This is done here
1141 */
1142 set_dev_entry_bit(devid, DEV_ENTRY_EX);
1143 iommu->exclusion_start = m->range_start;
1144 iommu->exclusion_length = m->range_length;
1145 }
1146}
1147
1148/*
1149 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1150 * initializes the hardware and our data structures with it.
1151 */
1152static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1153 struct ivhd_header *h)
1154{
1155 u8 *p = (u8 *)h;
1156 u8 *end = p, flags = 0;
1157 u16 devid = 0, devid_start = 0, devid_to = 0;
1158 u32 dev_i, ext_flags = 0;
1159 bool alias = false;
1160 struct ivhd_entry *e;
1161 u32 ivhd_size;
1162 int ret;
1163
1164
1165 ret = add_early_maps();
1166 if (ret)
1167 return ret;
1168
1169 /*
1170 * First save the recommended feature enable bits from ACPI
1171 */
1172 iommu->acpi_flags = h->flags;
1173
1174 /*
1175 * Done. Now parse the device entries
1176 */
1177 ivhd_size = get_ivhd_header_size(h);
1178 if (!ivhd_size) {
1179 pr_err("Unsupported IVHD type %#x\n", h->type);
1180 return -EINVAL;
1181 }
1182
1183 p += ivhd_size;
1184
1185 end += h->length;
1186
1187
1188 while (p < end) {
1189 e = (struct ivhd_entry *)p;
1190 switch (e->type) {
1191 case IVHD_DEV_ALL:
1192
1193 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1194
1195 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1196 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1197 break;
1198 case IVHD_DEV_SELECT:
1199
1200 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1201 "flags: %02x\n",
1202 PCI_BUS_NUM(e->devid),
1203 PCI_SLOT(e->devid),
1204 PCI_FUNC(e->devid),
1205 e->flags);
1206
1207 devid = e->devid;
1208 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1209 break;
1210 case IVHD_DEV_SELECT_RANGE_START:
1211
1212 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1213 "devid: %02x:%02x.%x flags: %02x\n",
1214 PCI_BUS_NUM(e->devid),
1215 PCI_SLOT(e->devid),
1216 PCI_FUNC(e->devid),
1217 e->flags);
1218
1219 devid_start = e->devid;
1220 flags = e->flags;
1221 ext_flags = 0;
1222 alias = false;
1223 break;
1224 case IVHD_DEV_ALIAS:
1225
1226 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1227 "flags: %02x devid_to: %02x:%02x.%x\n",
1228 PCI_BUS_NUM(e->devid),
1229 PCI_SLOT(e->devid),
1230 PCI_FUNC(e->devid),
1231 e->flags,
1232 PCI_BUS_NUM(e->ext >> 8),
1233 PCI_SLOT(e->ext >> 8),
1234 PCI_FUNC(e->ext >> 8));
1235
1236 devid = e->devid;
1237 devid_to = e->ext >> 8;
1238 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1239 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1240 amd_iommu_alias_table[devid] = devid_to;
1241 break;
1242 case IVHD_DEV_ALIAS_RANGE:
1243
1244 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1245 "devid: %02x:%02x.%x flags: %02x "
1246 "devid_to: %02x:%02x.%x\n",
1247 PCI_BUS_NUM(e->devid),
1248 PCI_SLOT(e->devid),
1249 PCI_FUNC(e->devid),
1250 e->flags,
1251 PCI_BUS_NUM(e->ext >> 8),
1252 PCI_SLOT(e->ext >> 8),
1253 PCI_FUNC(e->ext >> 8));
1254
1255 devid_start = e->devid;
1256 flags = e->flags;
1257 devid_to = e->ext >> 8;
1258 ext_flags = 0;
1259 alias = true;
1260 break;
1261 case IVHD_DEV_EXT_SELECT:
1262
1263 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1264 "flags: %02x ext: %08x\n",
1265 PCI_BUS_NUM(e->devid),
1266 PCI_SLOT(e->devid),
1267 PCI_FUNC(e->devid),
1268 e->flags, e->ext);
1269
1270 devid = e->devid;
1271 set_dev_entry_from_acpi(iommu, devid, e->flags,
1272 e->ext);
1273 break;
1274 case IVHD_DEV_EXT_SELECT_RANGE:
1275
1276 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1277 "%02x:%02x.%x flags: %02x ext: %08x\n",
1278 PCI_BUS_NUM(e->devid),
1279 PCI_SLOT(e->devid),
1280 PCI_FUNC(e->devid),
1281 e->flags, e->ext);
1282
1283 devid_start = e->devid;
1284 flags = e->flags;
1285 ext_flags = e->ext;
1286 alias = false;
1287 break;
1288 case IVHD_DEV_RANGE_END:
1289
1290 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1291 PCI_BUS_NUM(e->devid),
1292 PCI_SLOT(e->devid),
1293 PCI_FUNC(e->devid));
1294
1295 devid = e->devid;
1296 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1297 if (alias) {
1298 amd_iommu_alias_table[dev_i] = devid_to;
1299 set_dev_entry_from_acpi(iommu,
1300 devid_to, flags, ext_flags);
1301 }
1302 set_dev_entry_from_acpi(iommu, dev_i,
1303 flags, ext_flags);
1304 }
1305 break;
1306 case IVHD_DEV_SPECIAL: {
1307 u8 handle, type;
1308 const char *var;
1309 u16 devid;
1310 int ret;
1311
1312 handle = e->ext & 0xff;
1313 devid = (e->ext >> 8) & 0xffff;
1314 type = (e->ext >> 24) & 0xff;
1315
1316 if (type == IVHD_SPECIAL_IOAPIC)
1317 var = "IOAPIC";
1318 else if (type == IVHD_SPECIAL_HPET)
1319 var = "HPET";
1320 else
1321 var = "UNKNOWN";
1322
1323 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1324 var, (int)handle,
1325 PCI_BUS_NUM(devid),
1326 PCI_SLOT(devid),
1327 PCI_FUNC(devid));
1328
1329 ret = add_special_device(type, handle, &devid, false);
1330 if (ret)
1331 return ret;
1332
1333 /*
1334 * add_special_device might update the devid in case a
1335 * command-line override is present. So call
1336 * set_dev_entry_from_acpi after add_special_device.
1337 */
1338 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1339
1340 break;
1341 }
1342 case IVHD_DEV_ACPI_HID: {
1343 u16 devid;
1344 u8 hid[ACPIHID_HID_LEN] = {0};
1345 u8 uid[ACPIHID_UID_LEN] = {0};
1346 int ret;
1347
1348 if (h->type != 0x40) {
1349 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1350 e->type);
1351 break;
1352 }
1353
1354 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1355 hid[ACPIHID_HID_LEN - 1] = '\0';
1356
1357 if (!(*hid)) {
1358 pr_err(FW_BUG "Invalid HID.\n");
1359 break;
1360 }
1361
1362 switch (e->uidf) {
1363 case UID_NOT_PRESENT:
1364
1365 if (e->uidl != 0)
1366 pr_warn(FW_BUG "Invalid UID length.\n");
1367
1368 break;
1369 case UID_IS_INTEGER:
1370
1371 sprintf(uid, "%d", e->uid);
1372
1373 break;
1374 case UID_IS_CHARACTER:
1375
1376 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1377 uid[ACPIHID_UID_LEN - 1] = '\0';
1378
1379 break;
1380 default:
1381 break;
1382 }
1383
1384 devid = e->devid;
1385 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1386 hid, uid,
1387 PCI_BUS_NUM(devid),
1388 PCI_SLOT(devid),
1389 PCI_FUNC(devid));
1390
1391 flags = e->flags;
1392
1393 ret = add_acpi_hid_device(hid, uid, &devid, false);
1394 if (ret)
1395 return ret;
1396
1397 /*
1398 * add_special_device might update the devid in case a
1399 * command-line override is present. So call
1400 * set_dev_entry_from_acpi after add_special_device.
1401 */
1402 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1403
1404 break;
1405 }
1406 default:
1407 break;
1408 }
1409
1410 p += ivhd_entry_length(p);
1411 }
1412
1413 return 0;
1414}
1415
1416static void __init free_iommu_one(struct amd_iommu *iommu)
1417{
1418 free_command_buffer(iommu);
1419 free_event_buffer(iommu);
1420 free_ppr_log(iommu);
1421 free_ga_log(iommu);
1422 iommu_unmap_mmio_space(iommu);
1423}
1424
1425static void __init free_iommu_all(void)
1426{
1427 struct amd_iommu *iommu, *next;
1428
1429 for_each_iommu_safe(iommu, next) {
1430 list_del(&iommu->list);
1431 free_iommu_one(iommu);
1432 kfree(iommu);
1433 }
1434}
1435
1436/*
1437 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1438 * Workaround:
1439 * BIOS should disable L2B micellaneous clock gating by setting
1440 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1441 */
1442static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1443{
1444 u32 value;
1445
1446 if ((boot_cpu_data.x86 != 0x15) ||
1447 (boot_cpu_data.x86_model < 0x10) ||
1448 (boot_cpu_data.x86_model > 0x1f))
1449 return;
1450
1451 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1452 pci_read_config_dword(iommu->dev, 0xf4, &value);
1453
1454 if (value & BIT(2))
1455 return;
1456
1457 /* Select NB indirect register 0x90 and enable writing */
1458 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1459
1460 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1461 pci_info(iommu->dev, "Applying erratum 746 workaround\n");
1462
1463 /* Clear the enable writing bit */
1464 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1465}
1466
1467/*
1468 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1469 * Workaround:
1470 * BIOS should enable ATS write permission check by setting
1471 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1472 */
1473static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1474{
1475 u32 value;
1476
1477 if ((boot_cpu_data.x86 != 0x15) ||
1478 (boot_cpu_data.x86_model < 0x30) ||
1479 (boot_cpu_data.x86_model > 0x3f))
1480 return;
1481
1482 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1483 value = iommu_read_l2(iommu, 0x47);
1484
1485 if (value & BIT(0))
1486 return;
1487
1488 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1489 iommu_write_l2(iommu, 0x47, value | BIT(0));
1490
1491 pci_info(iommu->dev, "Applying ATS write check workaround\n");
1492}
1493
1494/*
1495 * This function clues the initialization function for one IOMMU
1496 * together and also allocates the command buffer and programs the
1497 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1498 */
1499static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1500{
1501 int ret;
1502
1503 raw_spin_lock_init(&iommu->lock);
1504
1505 /* Add IOMMU to internal data structures */
1506 list_add_tail(&iommu->list, &amd_iommu_list);
1507 iommu->index = amd_iommus_present++;
1508
1509 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1510 WARN(1, "System has more IOMMUs than supported by this driver\n");
1511 return -ENOSYS;
1512 }
1513
1514 /* Index is fine - add IOMMU to the array */
1515 amd_iommus[iommu->index] = iommu;
1516
1517 /*
1518 * Copy data from ACPI table entry to the iommu struct
1519 */
1520 iommu->devid = h->devid;
1521 iommu->cap_ptr = h->cap_ptr;
1522 iommu->pci_seg = h->pci_seg;
1523 iommu->mmio_phys = h->mmio_phys;
1524
1525 switch (h->type) {
1526 case 0x10:
1527 /* Check if IVHD EFR contains proper max banks/counters */
1528 if ((h->efr_attr != 0) &&
1529 ((h->efr_attr & (0xF << 13)) != 0) &&
1530 ((h->efr_attr & (0x3F << 17)) != 0))
1531 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1532 else
1533 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1534 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1535 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1536 if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
1537 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1538 break;
1539 case 0x11:
1540 case 0x40:
1541 if (h->efr_reg & (1 << 9))
1542 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1543 else
1544 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1545 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1546 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1547 if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
1548 amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
1549 break;
1550 default:
1551 return -EINVAL;
1552 }
1553
1554 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1555 iommu->mmio_phys_end);
1556 if (!iommu->mmio_base)
1557 return -ENOMEM;
1558
1559 if (alloc_command_buffer(iommu))
1560 return -ENOMEM;
1561
1562 if (alloc_event_buffer(iommu))
1563 return -ENOMEM;
1564
1565 iommu->int_enabled = false;
1566
1567 init_translation_status(iommu);
1568 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1569 iommu_disable(iommu);
1570 clear_translation_pre_enabled(iommu);
1571 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1572 iommu->index);
1573 }
1574 if (amd_iommu_pre_enabled)
1575 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1576
1577 ret = init_iommu_from_acpi(iommu, h);
1578 if (ret)
1579 return ret;
1580
1581 ret = amd_iommu_create_irq_domain(iommu);
1582 if (ret)
1583 return ret;
1584
1585 /*
1586 * Make sure IOMMU is not considered to translate itself. The IVRS
1587 * table tells us so, but this is a lie!
1588 */
1589 amd_iommu_rlookup_table[iommu->devid] = NULL;
1590
1591 return 0;
1592}
1593
1594/**
1595 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1596 * @ivrs Pointer to the IVRS header
1597 *
1598 * This function search through all IVDB of the maximum supported IVHD
1599 */
1600static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1601{
1602 u8 *base = (u8 *)ivrs;
1603 struct ivhd_header *ivhd = (struct ivhd_header *)
1604 (base + IVRS_HEADER_LENGTH);
1605 u8 last_type = ivhd->type;
1606 u16 devid = ivhd->devid;
1607
1608 while (((u8 *)ivhd - base < ivrs->length) &&
1609 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1610 u8 *p = (u8 *) ivhd;
1611
1612 if (ivhd->devid == devid)
1613 last_type = ivhd->type;
1614 ivhd = (struct ivhd_header *)(p + ivhd->length);
1615 }
1616
1617 return last_type;
1618}
1619
1620/*
1621 * Iterates over all IOMMU entries in the ACPI table, allocates the
1622 * IOMMU structure and initializes it with init_iommu_one()
1623 */
1624static int __init init_iommu_all(struct acpi_table_header *table)
1625{
1626 u8 *p = (u8 *)table, *end = (u8 *)table;
1627 struct ivhd_header *h;
1628 struct amd_iommu *iommu;
1629 int ret;
1630
1631 end += table->length;
1632 p += IVRS_HEADER_LENGTH;
1633
1634 while (p < end) {
1635 h = (struct ivhd_header *)p;
1636 if (*p == amd_iommu_target_ivhd_type) {
1637
1638 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1639 "seg: %d flags: %01x info %04x\n",
1640 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1641 PCI_FUNC(h->devid), h->cap_ptr,
1642 h->pci_seg, h->flags, h->info);
1643 DUMP_printk(" mmio-addr: %016llx\n",
1644 h->mmio_phys);
1645
1646 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1647 if (iommu == NULL)
1648 return -ENOMEM;
1649
1650 ret = init_iommu_one(iommu, h);
1651 if (ret)
1652 return ret;
1653 }
1654 p += h->length;
1655
1656 }
1657 WARN_ON(p != end);
1658
1659 return 0;
1660}
1661
1662static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1663 u8 fxn, u64 *value, bool is_write);
1664
1665static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1666{
1667 struct pci_dev *pdev = iommu->dev;
1668 u64 val = 0xabcd, val2 = 0;
1669
1670 if (!iommu_feature(iommu, FEATURE_PC))
1671 return;
1672
1673 amd_iommu_pc_present = true;
1674
1675 /* Check if the performance counters can be written to */
1676 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1677 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1678 (val != val2)) {
1679 pci_err(pdev, "Unable to write to IOMMU perf counter.\n");
1680 amd_iommu_pc_present = false;
1681 return;
1682 }
1683
1684 pci_info(pdev, "IOMMU performance counters supported\n");
1685
1686 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1687 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1688 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1689}
1690
1691static ssize_t amd_iommu_show_cap(struct device *dev,
1692 struct device_attribute *attr,
1693 char *buf)
1694{
1695 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1696 return sprintf(buf, "%x\n", iommu->cap);
1697}
1698static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1699
1700static ssize_t amd_iommu_show_features(struct device *dev,
1701 struct device_attribute *attr,
1702 char *buf)
1703{
1704 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1705 return sprintf(buf, "%llx\n", iommu->features);
1706}
1707static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1708
1709static struct attribute *amd_iommu_attrs[] = {
1710 &dev_attr_cap.attr,
1711 &dev_attr_features.attr,
1712 NULL,
1713};
1714
1715static struct attribute_group amd_iommu_group = {
1716 .name = "amd-iommu",
1717 .attrs = amd_iommu_attrs,
1718};
1719
1720static const struct attribute_group *amd_iommu_groups[] = {
1721 &amd_iommu_group,
1722 NULL,
1723};
1724
1725static int __init iommu_init_pci(struct amd_iommu *iommu)
1726{
1727 int cap_ptr = iommu->cap_ptr;
1728 u32 range, misc, low, high;
1729 int ret;
1730
1731 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1732 iommu->devid & 0xff);
1733 if (!iommu->dev)
1734 return -ENODEV;
1735
1736 /* Prevent binding other PCI device drivers to IOMMU devices */
1737 iommu->dev->match_driver = false;
1738
1739 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1740 &iommu->cap);
1741 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1742 &range);
1743 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1744 &misc);
1745
1746 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1747 amd_iommu_iotlb_sup = false;
1748
1749 /* read extended feature bits */
1750 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1751 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1752
1753 iommu->features = ((u64)high << 32) | low;
1754
1755 if (iommu_feature(iommu, FEATURE_GT)) {
1756 int glxval;
1757 u32 max_pasid;
1758 u64 pasmax;
1759
1760 pasmax = iommu->features & FEATURE_PASID_MASK;
1761 pasmax >>= FEATURE_PASID_SHIFT;
1762 max_pasid = (1 << (pasmax + 1)) - 1;
1763
1764 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1765
1766 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1767
1768 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1769 glxval >>= FEATURE_GLXVAL_SHIFT;
1770
1771 if (amd_iommu_max_glx_val == -1)
1772 amd_iommu_max_glx_val = glxval;
1773 else
1774 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1775 }
1776
1777 if (iommu_feature(iommu, FEATURE_GT) &&
1778 iommu_feature(iommu, FEATURE_PPR)) {
1779 iommu->is_iommu_v2 = true;
1780 amd_iommu_v2_present = true;
1781 }
1782
1783 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1784 return -ENOMEM;
1785
1786 ret = iommu_init_ga(iommu);
1787 if (ret)
1788 return ret;
1789
1790 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1791 amd_iommu_np_cache = true;
1792
1793 init_iommu_perf_ctr(iommu);
1794
1795 if (is_rd890_iommu(iommu->dev)) {
1796 int i, j;
1797
1798 iommu->root_pdev =
1799 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1800 PCI_DEVFN(0, 0));
1801
1802 /*
1803 * Some rd890 systems may not be fully reconfigured by the
1804 * BIOS, so it's necessary for us to store this information so
1805 * it can be reprogrammed on resume
1806 */
1807 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1808 &iommu->stored_addr_lo);
1809 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1810 &iommu->stored_addr_hi);
1811
1812 /* Low bit locks writes to configuration space */
1813 iommu->stored_addr_lo &= ~1;
1814
1815 for (i = 0; i < 6; i++)
1816 for (j = 0; j < 0x12; j++)
1817 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1818
1819 for (i = 0; i < 0x83; i++)
1820 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1821 }
1822
1823 amd_iommu_erratum_746_workaround(iommu);
1824 amd_iommu_ats_write_check_workaround(iommu);
1825
1826 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1827 amd_iommu_groups, "ivhd%d", iommu->index);
1828 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1829 iommu_device_register(&iommu->iommu);
1830
1831 return pci_enable_device(iommu->dev);
1832}
1833
1834static void print_iommu_info(void)
1835{
1836 static const char * const feat_str[] = {
1837 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1838 "IA", "GA", "HE", "PC"
1839 };
1840 struct amd_iommu *iommu;
1841
1842 for_each_iommu(iommu) {
1843 struct pci_dev *pdev = iommu->dev;
1844 int i;
1845
1846 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr);
1847
1848 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1849 pci_info(pdev, "Extended features (%#llx):\n",
1850 iommu->features);
1851 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1852 if (iommu_feature(iommu, (1ULL << i)))
1853 pr_cont(" %s", feat_str[i]);
1854 }
1855
1856 if (iommu->features & FEATURE_GAM_VAPIC)
1857 pr_cont(" GA_vAPIC");
1858
1859 pr_cont("\n");
1860 }
1861 }
1862 if (irq_remapping_enabled) {
1863 pr_info("Interrupt remapping enabled\n");
1864 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1865 pr_info("Virtual APIC enabled\n");
1866 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1867 pr_info("X2APIC enabled\n");
1868 }
1869}
1870
1871static int __init amd_iommu_init_pci(void)
1872{
1873 struct amd_iommu *iommu;
1874 int ret = 0;
1875
1876 for_each_iommu(iommu) {
1877 ret = iommu_init_pci(iommu);
1878 if (ret)
1879 break;
1880 }
1881
1882 /*
1883 * Order is important here to make sure any unity map requirements are
1884 * fulfilled. The unity mappings are created and written to the device
1885 * table during the amd_iommu_init_api() call.
1886 *
1887 * After that we call init_device_table_dma() to make sure any
1888 * uninitialized DTE will block DMA, and in the end we flush the caches
1889 * of all IOMMUs to make sure the changes to the device table are
1890 * active.
1891 */
1892 ret = amd_iommu_init_api();
1893
1894 init_device_table_dma();
1895
1896 for_each_iommu(iommu)
1897 iommu_flush_all_caches(iommu);
1898
1899 if (!ret)
1900 print_iommu_info();
1901
1902 return ret;
1903}
1904
1905/****************************************************************************
1906 *
1907 * The following functions initialize the MSI interrupts for all IOMMUs
1908 * in the system. It's a bit challenging because there could be multiple
1909 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1910 * pci_dev.
1911 *
1912 ****************************************************************************/
1913
1914static int iommu_setup_msi(struct amd_iommu *iommu)
1915{
1916 int r;
1917
1918 r = pci_enable_msi(iommu->dev);
1919 if (r)
1920 return r;
1921
1922 r = request_threaded_irq(iommu->dev->irq,
1923 amd_iommu_int_handler,
1924 amd_iommu_int_thread,
1925 0, "AMD-Vi",
1926 iommu);
1927
1928 if (r) {
1929 pci_disable_msi(iommu->dev);
1930 return r;
1931 }
1932
1933 iommu->int_enabled = true;
1934
1935 return 0;
1936}
1937
1938static int iommu_init_msi(struct amd_iommu *iommu)
1939{
1940 int ret;
1941
1942 if (iommu->int_enabled)
1943 goto enable_faults;
1944
1945 if (iommu->dev->msi_cap)
1946 ret = iommu_setup_msi(iommu);
1947 else
1948 ret = -ENODEV;
1949
1950 if (ret)
1951 return ret;
1952
1953enable_faults:
1954 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1955
1956 if (iommu->ppr_log != NULL)
1957 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1958
1959 iommu_ga_log_enable(iommu);
1960
1961 return 0;
1962}
1963
1964/****************************************************************************
1965 *
1966 * The next functions belong to the third pass of parsing the ACPI
1967 * table. In this last pass the memory mapping requirements are
1968 * gathered (like exclusion and unity mapping ranges).
1969 *
1970 ****************************************************************************/
1971
1972static void __init free_unity_maps(void)
1973{
1974 struct unity_map_entry *entry, *next;
1975
1976 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1977 list_del(&entry->list);
1978 kfree(entry);
1979 }
1980}
1981
1982/* called when we find an exclusion range definition in ACPI */
1983static int __init init_exclusion_range(struct ivmd_header *m)
1984{
1985 int i;
1986
1987 switch (m->type) {
1988 case ACPI_IVMD_TYPE:
1989 set_device_exclusion_range(m->devid, m);
1990 break;
1991 case ACPI_IVMD_TYPE_ALL:
1992 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1993 set_device_exclusion_range(i, m);
1994 break;
1995 case ACPI_IVMD_TYPE_RANGE:
1996 for (i = m->devid; i <= m->aux; ++i)
1997 set_device_exclusion_range(i, m);
1998 break;
1999 default:
2000 break;
2001 }
2002
2003 return 0;
2004}
2005
2006/* called for unity map ACPI definition */
2007static int __init init_unity_map_range(struct ivmd_header *m)
2008{
2009 struct unity_map_entry *e = NULL;
2010 char *s;
2011
2012 e = kzalloc(sizeof(*e), GFP_KERNEL);
2013 if (e == NULL)
2014 return -ENOMEM;
2015
2016 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2017 init_exclusion_range(m);
2018
2019 switch (m->type) {
2020 default:
2021 kfree(e);
2022 return 0;
2023 case ACPI_IVMD_TYPE:
2024 s = "IVMD_TYPEi\t\t\t";
2025 e->devid_start = e->devid_end = m->devid;
2026 break;
2027 case ACPI_IVMD_TYPE_ALL:
2028 s = "IVMD_TYPE_ALL\t\t";
2029 e->devid_start = 0;
2030 e->devid_end = amd_iommu_last_bdf;
2031 break;
2032 case ACPI_IVMD_TYPE_RANGE:
2033 s = "IVMD_TYPE_RANGE\t\t";
2034 e->devid_start = m->devid;
2035 e->devid_end = m->aux;
2036 break;
2037 }
2038 e->address_start = PAGE_ALIGN(m->range_start);
2039 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2040 e->prot = m->flags >> 1;
2041
2042 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2043 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2044 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2045 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2046 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2047 e->address_start, e->address_end, m->flags);
2048
2049 list_add_tail(&e->list, &amd_iommu_unity_map);
2050
2051 return 0;
2052}
2053
2054/* iterates over all memory definitions we find in the ACPI table */
2055static int __init init_memory_definitions(struct acpi_table_header *table)
2056{
2057 u8 *p = (u8 *)table, *end = (u8 *)table;
2058 struct ivmd_header *m;
2059
2060 end += table->length;
2061 p += IVRS_HEADER_LENGTH;
2062
2063 while (p < end) {
2064 m = (struct ivmd_header *)p;
2065 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
2066 init_unity_map_range(m);
2067
2068 p += m->length;
2069 }
2070
2071 return 0;
2072}
2073
2074/*
2075 * Init the device table to not allow DMA access for devices
2076 */
2077static void init_device_table_dma(void)
2078{
2079 u32 devid;
2080
2081 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2082 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2083 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2084 }
2085}
2086
2087static void __init uninit_device_table_dma(void)
2088{
2089 u32 devid;
2090
2091 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2092 amd_iommu_dev_table[devid].data[0] = 0ULL;
2093 amd_iommu_dev_table[devid].data[1] = 0ULL;
2094 }
2095}
2096
2097static void init_device_table(void)
2098{
2099 u32 devid;
2100
2101 if (!amd_iommu_irq_remap)
2102 return;
2103
2104 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2105 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2106}
2107
2108static void iommu_init_flags(struct amd_iommu *iommu)
2109{
2110 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2111 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2112 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2113
2114 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2115 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2116 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2117
2118 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2119 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2120 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2121
2122 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2123 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2124 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2125
2126 /*
2127 * make IOMMU memory accesses cache coherent
2128 */
2129 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2130
2131 /* Set IOTLB invalidation timeout to 1s */
2132 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2133}
2134
2135static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2136{
2137 int i, j;
2138 u32 ioc_feature_control;
2139 struct pci_dev *pdev = iommu->root_pdev;
2140
2141 /* RD890 BIOSes may not have completely reconfigured the iommu */
2142 if (!is_rd890_iommu(iommu->dev) || !pdev)
2143 return;
2144
2145 /*
2146 * First, we need to ensure that the iommu is enabled. This is
2147 * controlled by a register in the northbridge
2148 */
2149
2150 /* Select Northbridge indirect register 0x75 and enable writing */
2151 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2152 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2153
2154 /* Enable the iommu */
2155 if (!(ioc_feature_control & 0x1))
2156 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2157
2158 /* Restore the iommu BAR */
2159 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2160 iommu->stored_addr_lo);
2161 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2162 iommu->stored_addr_hi);
2163
2164 /* Restore the l1 indirect regs for each of the 6 l1s */
2165 for (i = 0; i < 6; i++)
2166 for (j = 0; j < 0x12; j++)
2167 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2168
2169 /* Restore the l2 indirect regs */
2170 for (i = 0; i < 0x83; i++)
2171 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2172
2173 /* Lock PCI setup registers */
2174 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2175 iommu->stored_addr_lo | 1);
2176}
2177
2178static void iommu_enable_ga(struct amd_iommu *iommu)
2179{
2180#ifdef CONFIG_IRQ_REMAP
2181 switch (amd_iommu_guest_ir) {
2182 case AMD_IOMMU_GUEST_IR_VAPIC:
2183 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2184 /* Fall through */
2185 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2186 iommu_feature_enable(iommu, CONTROL_GA_EN);
2187 iommu->irte_ops = &irte_128_ops;
2188 break;
2189 default:
2190 iommu->irte_ops = &irte_32_ops;
2191 break;
2192 }
2193#endif
2194}
2195
2196static void early_enable_iommu(struct amd_iommu *iommu)
2197{
2198 iommu_disable(iommu);
2199 iommu_init_flags(iommu);
2200 iommu_set_device_table(iommu);
2201 iommu_enable_command_buffer(iommu);
2202 iommu_enable_event_buffer(iommu);
2203 iommu_set_exclusion_range(iommu);
2204 iommu_enable_ga(iommu);
2205 iommu_enable_xt(iommu);
2206 iommu_enable(iommu);
2207 iommu_flush_all_caches(iommu);
2208}
2209
2210/*
2211 * This function finally enables all IOMMUs found in the system after
2212 * they have been initialized.
2213 *
2214 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2215 * the old content of device table entries. Not this case or copy failed,
2216 * just continue as normal kernel does.
2217 */
2218static void early_enable_iommus(void)
2219{
2220 struct amd_iommu *iommu;
2221
2222
2223 if (!copy_device_table()) {
2224 /*
2225 * If come here because of failure in copying device table from old
2226 * kernel with all IOMMUs enabled, print error message and try to
2227 * free allocated old_dev_tbl_cpy.
2228 */
2229 if (amd_iommu_pre_enabled)
2230 pr_err("Failed to copy DEV table from previous kernel.\n");
2231 if (old_dev_tbl_cpy != NULL)
2232 free_pages((unsigned long)old_dev_tbl_cpy,
2233 get_order(dev_table_size));
2234
2235 for_each_iommu(iommu) {
2236 clear_translation_pre_enabled(iommu);
2237 early_enable_iommu(iommu);
2238 }
2239 } else {
2240 pr_info("Copied DEV table from previous kernel.\n");
2241 free_pages((unsigned long)amd_iommu_dev_table,
2242 get_order(dev_table_size));
2243 amd_iommu_dev_table = old_dev_tbl_cpy;
2244 for_each_iommu(iommu) {
2245 iommu_disable_command_buffer(iommu);
2246 iommu_disable_event_buffer(iommu);
2247 iommu_enable_command_buffer(iommu);
2248 iommu_enable_event_buffer(iommu);
2249 iommu_enable_ga(iommu);
2250 iommu_enable_xt(iommu);
2251 iommu_set_device_table(iommu);
2252 iommu_flush_all_caches(iommu);
2253 }
2254 }
2255
2256#ifdef CONFIG_IRQ_REMAP
2257 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2258 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2259#endif
2260}
2261
2262static void enable_iommus_v2(void)
2263{
2264 struct amd_iommu *iommu;
2265
2266 for_each_iommu(iommu) {
2267 iommu_enable_ppr_log(iommu);
2268 iommu_enable_gt(iommu);
2269 }
2270}
2271
2272static void enable_iommus(void)
2273{
2274 early_enable_iommus();
2275
2276 enable_iommus_v2();
2277}
2278
2279static void disable_iommus(void)
2280{
2281 struct amd_iommu *iommu;
2282
2283 for_each_iommu(iommu)
2284 iommu_disable(iommu);
2285
2286#ifdef CONFIG_IRQ_REMAP
2287 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2288 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2289#endif
2290}
2291
2292/*
2293 * Suspend/Resume support
2294 * disable suspend until real resume implemented
2295 */
2296
2297static void amd_iommu_resume(void)
2298{
2299 struct amd_iommu *iommu;
2300
2301 for_each_iommu(iommu)
2302 iommu_apply_resume_quirks(iommu);
2303
2304 /* re-load the hardware */
2305 enable_iommus();
2306
2307 amd_iommu_enable_interrupts();
2308}
2309
2310static int amd_iommu_suspend(void)
2311{
2312 /* disable IOMMUs to go out of the way for BIOS */
2313 disable_iommus();
2314
2315 return 0;
2316}
2317
2318static struct syscore_ops amd_iommu_syscore_ops = {
2319 .suspend = amd_iommu_suspend,
2320 .resume = amd_iommu_resume,
2321};
2322
2323static void __init free_iommu_resources(void)
2324{
2325 kmemleak_free(irq_lookup_table);
2326 free_pages((unsigned long)irq_lookup_table,
2327 get_order(rlookup_table_size));
2328 irq_lookup_table = NULL;
2329
2330 kmem_cache_destroy(amd_iommu_irq_cache);
2331 amd_iommu_irq_cache = NULL;
2332
2333 free_pages((unsigned long)amd_iommu_rlookup_table,
2334 get_order(rlookup_table_size));
2335 amd_iommu_rlookup_table = NULL;
2336
2337 free_pages((unsigned long)amd_iommu_alias_table,
2338 get_order(alias_table_size));
2339 amd_iommu_alias_table = NULL;
2340
2341 free_pages((unsigned long)amd_iommu_dev_table,
2342 get_order(dev_table_size));
2343 amd_iommu_dev_table = NULL;
2344
2345 free_iommu_all();
2346
2347#ifdef CONFIG_GART_IOMMU
2348 /*
2349 * We failed to initialize the AMD IOMMU - try fallback to GART
2350 * if possible.
2351 */
2352 gart_iommu_init();
2353
2354#endif
2355}
2356
2357/* SB IOAPIC is always on this device in AMD systems */
2358#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2359
2360static bool __init check_ioapic_information(void)
2361{
2362 const char *fw_bug = FW_BUG;
2363 bool ret, has_sb_ioapic;
2364 int idx;
2365
2366 has_sb_ioapic = false;
2367 ret = false;
2368
2369 /*
2370 * If we have map overrides on the kernel command line the
2371 * messages in this function might not describe firmware bugs
2372 * anymore - so be careful
2373 */
2374 if (cmdline_maps)
2375 fw_bug = "";
2376
2377 for (idx = 0; idx < nr_ioapics; idx++) {
2378 int devid, id = mpc_ioapic_id(idx);
2379
2380 devid = get_ioapic_devid(id);
2381 if (devid < 0) {
2382 pr_err("%s: IOAPIC[%d] not in IVRS table\n",
2383 fw_bug, id);
2384 ret = false;
2385 } else if (devid == IOAPIC_SB_DEVID) {
2386 has_sb_ioapic = true;
2387 ret = true;
2388 }
2389 }
2390
2391 if (!has_sb_ioapic) {
2392 /*
2393 * We expect the SB IOAPIC to be listed in the IVRS
2394 * table. The system timer is connected to the SB IOAPIC
2395 * and if we don't have it in the list the system will
2396 * panic at boot time. This situation usually happens
2397 * when the BIOS is buggy and provides us the wrong
2398 * device id for the IOAPIC in the system.
2399 */
2400 pr_err("%s: No southbridge IOAPIC found\n", fw_bug);
2401 }
2402
2403 if (!ret)
2404 pr_err("Disabling interrupt remapping\n");
2405
2406 return ret;
2407}
2408
2409static void __init free_dma_resources(void)
2410{
2411 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2412 get_order(MAX_DOMAIN_ID/8));
2413 amd_iommu_pd_alloc_bitmap = NULL;
2414
2415 free_unity_maps();
2416}
2417
2418/*
2419 * This is the hardware init function for AMD IOMMU in the system.
2420 * This function is called either from amd_iommu_init or from the interrupt
2421 * remapping setup code.
2422 *
2423 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2424 * four times:
2425 *
2426 * 1 pass) Discover the most comprehensive IVHD type to use.
2427 *
2428 * 2 pass) Find the highest PCI device id the driver has to handle.
2429 * Upon this information the size of the data structures is
2430 * determined that needs to be allocated.
2431 *
2432 * 3 pass) Initialize the data structures just allocated with the
2433 * information in the ACPI table about available AMD IOMMUs
2434 * in the system. It also maps the PCI devices in the
2435 * system to specific IOMMUs
2436 *
2437 * 4 pass) After the basic data structures are allocated and
2438 * initialized we update them with information about memory
2439 * remapping requirements parsed out of the ACPI table in
2440 * this last pass.
2441 *
2442 * After everything is set up the IOMMUs are enabled and the necessary
2443 * hotplug and suspend notifiers are registered.
2444 */
2445static int __init early_amd_iommu_init(void)
2446{
2447 struct acpi_table_header *ivrs_base;
2448 acpi_status status;
2449 int i, remap_cache_sz, ret = 0;
2450
2451 if (!amd_iommu_detected)
2452 return -ENODEV;
2453
2454 status = acpi_get_table("IVRS", 0, &ivrs_base);
2455 if (status == AE_NOT_FOUND)
2456 return -ENODEV;
2457 else if (ACPI_FAILURE(status)) {
2458 const char *err = acpi_format_exception(status);
2459 pr_err("IVRS table error: %s\n", err);
2460 return -EINVAL;
2461 }
2462
2463 /*
2464 * Validate checksum here so we don't need to do it when
2465 * we actually parse the table
2466 */
2467 ret = check_ivrs_checksum(ivrs_base);
2468 if (ret)
2469 goto out;
2470
2471 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2472 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2473
2474 /*
2475 * First parse ACPI tables to find the largest Bus/Dev/Func
2476 * we need to handle. Upon this information the shared data
2477 * structures for the IOMMUs in the system will be allocated
2478 */
2479 ret = find_last_devid_acpi(ivrs_base);
2480 if (ret)
2481 goto out;
2482
2483 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2484 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2485 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2486
2487 /* Device table - directly used by all IOMMUs */
2488 ret = -ENOMEM;
2489 amd_iommu_dev_table = (void *)__get_free_pages(
2490 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2491 get_order(dev_table_size));
2492 if (amd_iommu_dev_table == NULL)
2493 goto out;
2494
2495 /*
2496 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2497 * IOMMU see for that device
2498 */
2499 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2500 get_order(alias_table_size));
2501 if (amd_iommu_alias_table == NULL)
2502 goto out;
2503
2504 /* IOMMU rlookup table - find the IOMMU for a specific device */
2505 amd_iommu_rlookup_table = (void *)__get_free_pages(
2506 GFP_KERNEL | __GFP_ZERO,
2507 get_order(rlookup_table_size));
2508 if (amd_iommu_rlookup_table == NULL)
2509 goto out;
2510
2511 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2512 GFP_KERNEL | __GFP_ZERO,
2513 get_order(MAX_DOMAIN_ID/8));
2514 if (amd_iommu_pd_alloc_bitmap == NULL)
2515 goto out;
2516
2517 /*
2518 * let all alias entries point to itself
2519 */
2520 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2521 amd_iommu_alias_table[i] = i;
2522
2523 /*
2524 * never allocate domain 0 because its used as the non-allocated and
2525 * error value placeholder
2526 */
2527 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2528
2529 spin_lock_init(&amd_iommu_pd_lock);
2530
2531 /*
2532 * now the data structures are allocated and basically initialized
2533 * start the real acpi table scan
2534 */
2535 ret = init_iommu_all(ivrs_base);
2536 if (ret)
2537 goto out;
2538
2539 /* Disable any previously enabled IOMMUs */
2540 if (!is_kdump_kernel() || amd_iommu_disabled)
2541 disable_iommus();
2542
2543 if (amd_iommu_irq_remap)
2544 amd_iommu_irq_remap = check_ioapic_information();
2545
2546 if (amd_iommu_irq_remap) {
2547 /*
2548 * Interrupt remapping enabled, create kmem_cache for the
2549 * remapping tables.
2550 */
2551 ret = -ENOMEM;
2552 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2553 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2554 else
2555 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2556 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2557 remap_cache_sz,
2558 IRQ_TABLE_ALIGNMENT,
2559 0, NULL);
2560 if (!amd_iommu_irq_cache)
2561 goto out;
2562
2563 irq_lookup_table = (void *)__get_free_pages(
2564 GFP_KERNEL | __GFP_ZERO,
2565 get_order(rlookup_table_size));
2566 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2567 1, GFP_KERNEL);
2568 if (!irq_lookup_table)
2569 goto out;
2570 }
2571
2572 ret = init_memory_definitions(ivrs_base);
2573 if (ret)
2574 goto out;
2575
2576 /* init the device table */
2577 init_device_table();
2578
2579out:
2580 /* Don't leak any ACPI memory */
2581 acpi_put_table(ivrs_base);
2582 ivrs_base = NULL;
2583
2584 return ret;
2585}
2586
2587static int amd_iommu_enable_interrupts(void)
2588{
2589 struct amd_iommu *iommu;
2590 int ret = 0;
2591
2592 for_each_iommu(iommu) {
2593 ret = iommu_init_msi(iommu);
2594 if (ret)
2595 goto out;
2596 }
2597
2598out:
2599 return ret;
2600}
2601
2602static bool detect_ivrs(void)
2603{
2604 struct acpi_table_header *ivrs_base;
2605 acpi_status status;
2606
2607 status = acpi_get_table("IVRS", 0, &ivrs_base);
2608 if (status == AE_NOT_FOUND)
2609 return false;
2610 else if (ACPI_FAILURE(status)) {
2611 const char *err = acpi_format_exception(status);
2612 pr_err("IVRS table error: %s\n", err);
2613 return false;
2614 }
2615
2616 acpi_put_table(ivrs_base);
2617
2618 /* Make sure ACS will be enabled during PCI probe */
2619 pci_request_acs();
2620
2621 return true;
2622}
2623
2624/****************************************************************************
2625 *
2626 * AMD IOMMU Initialization State Machine
2627 *
2628 ****************************************************************************/
2629
2630static int __init state_next(void)
2631{
2632 int ret = 0;
2633
2634 switch (init_state) {
2635 case IOMMU_START_STATE:
2636 if (!detect_ivrs()) {
2637 init_state = IOMMU_NOT_FOUND;
2638 ret = -ENODEV;
2639 } else {
2640 init_state = IOMMU_IVRS_DETECTED;
2641 }
2642 break;
2643 case IOMMU_IVRS_DETECTED:
2644 ret = early_amd_iommu_init();
2645 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2646 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2647 pr_info("AMD IOMMU disabled on kernel command-line\n");
2648 free_dma_resources();
2649 free_iommu_resources();
2650 init_state = IOMMU_CMDLINE_DISABLED;
2651 ret = -EINVAL;
2652 }
2653 break;
2654 case IOMMU_ACPI_FINISHED:
2655 early_enable_iommus();
2656 x86_platform.iommu_shutdown = disable_iommus;
2657 init_state = IOMMU_ENABLED;
2658 break;
2659 case IOMMU_ENABLED:
2660 register_syscore_ops(&amd_iommu_syscore_ops);
2661 ret = amd_iommu_init_pci();
2662 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2663 enable_iommus_v2();
2664 break;
2665 case IOMMU_PCI_INIT:
2666 ret = amd_iommu_enable_interrupts();
2667 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2668 break;
2669 case IOMMU_INTERRUPTS_EN:
2670 ret = amd_iommu_init_dma_ops();
2671 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2672 break;
2673 case IOMMU_DMA_OPS:
2674 init_state = IOMMU_INITIALIZED;
2675 break;
2676 case IOMMU_INITIALIZED:
2677 /* Nothing to do */
2678 break;
2679 case IOMMU_NOT_FOUND:
2680 case IOMMU_INIT_ERROR:
2681 case IOMMU_CMDLINE_DISABLED:
2682 /* Error states => do nothing */
2683 ret = -EINVAL;
2684 break;
2685 default:
2686 /* Unknown state */
2687 BUG();
2688 }
2689
2690 return ret;
2691}
2692
2693static int __init iommu_go_to_state(enum iommu_init_state state)
2694{
2695 int ret = -EINVAL;
2696
2697 while (init_state != state) {
2698 if (init_state == IOMMU_NOT_FOUND ||
2699 init_state == IOMMU_INIT_ERROR ||
2700 init_state == IOMMU_CMDLINE_DISABLED)
2701 break;
2702 ret = state_next();
2703 }
2704
2705 return ret;
2706}
2707
2708#ifdef CONFIG_IRQ_REMAP
2709int __init amd_iommu_prepare(void)
2710{
2711 int ret;
2712
2713 amd_iommu_irq_remap = true;
2714
2715 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2716 if (ret)
2717 return ret;
2718 return amd_iommu_irq_remap ? 0 : -ENODEV;
2719}
2720
2721int __init amd_iommu_enable(void)
2722{
2723 int ret;
2724
2725 ret = iommu_go_to_state(IOMMU_ENABLED);
2726 if (ret)
2727 return ret;
2728
2729 irq_remapping_enabled = 1;
2730 return amd_iommu_xt_mode;
2731}
2732
2733void amd_iommu_disable(void)
2734{
2735 amd_iommu_suspend();
2736}
2737
2738int amd_iommu_reenable(int mode)
2739{
2740 amd_iommu_resume();
2741
2742 return 0;
2743}
2744
2745int __init amd_iommu_enable_faulting(void)
2746{
2747 /* We enable MSI later when PCI is initialized */
2748 return 0;
2749}
2750#endif
2751
2752/*
2753 * This is the core init function for AMD IOMMU hardware in the system.
2754 * This function is called from the generic x86 DMA layer initialization
2755 * code.
2756 */
2757static int __init amd_iommu_init(void)
2758{
2759 struct amd_iommu *iommu;
2760 int ret;
2761
2762 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2763 if (ret) {
2764 free_dma_resources();
2765 if (!irq_remapping_enabled) {
2766 disable_iommus();
2767 free_iommu_resources();
2768 } else {
2769 uninit_device_table_dma();
2770 for_each_iommu(iommu)
2771 iommu_flush_all_caches(iommu);
2772 }
2773 }
2774
2775 for_each_iommu(iommu)
2776 amd_iommu_debugfs_setup(iommu);
2777
2778 return ret;
2779}
2780
2781static bool amd_iommu_sme_check(void)
2782{
2783 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2784 return true;
2785
2786 /* For Fam17h, a specific level of support is required */
2787 if (boot_cpu_data.microcode >= 0x08001205)
2788 return true;
2789
2790 if ((boot_cpu_data.microcode >= 0x08001126) &&
2791 (boot_cpu_data.microcode <= 0x080011ff))
2792 return true;
2793
2794 pr_notice("IOMMU not currently supported when SME is active\n");
2795
2796 return false;
2797}
2798
2799/****************************************************************************
2800 *
2801 * Early detect code. This code runs at IOMMU detection time in the DMA
2802 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2803 * IOMMUs
2804 *
2805 ****************************************************************************/
2806int __init amd_iommu_detect(void)
2807{
2808 int ret;
2809
2810 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2811 return -ENODEV;
2812
2813 if (!amd_iommu_sme_check())
2814 return -ENODEV;
2815
2816 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2817 if (ret)
2818 return ret;
2819
2820 amd_iommu_detected = true;
2821 iommu_detected = 1;
2822 x86_init.iommu.iommu_init = amd_iommu_init;
2823
2824 return 1;
2825}
2826
2827/****************************************************************************
2828 *
2829 * Parsing functions for the AMD IOMMU specific kernel command line
2830 * options.
2831 *
2832 ****************************************************************************/
2833
2834static int __init parse_amd_iommu_dump(char *str)
2835{
2836 amd_iommu_dump = true;
2837
2838 return 1;
2839}
2840
2841static int __init parse_amd_iommu_intr(char *str)
2842{
2843 for (; *str; ++str) {
2844 if (strncmp(str, "legacy", 6) == 0) {
2845 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2846 break;
2847 }
2848 if (strncmp(str, "vapic", 5) == 0) {
2849 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2850 break;
2851 }
2852 }
2853 return 1;
2854}
2855
2856static int __init parse_amd_iommu_options(char *str)
2857{
2858 for (; *str; ++str) {
2859 if (strncmp(str, "fullflush", 9) == 0)
2860 amd_iommu_unmap_flush = true;
2861 if (strncmp(str, "off", 3) == 0)
2862 amd_iommu_disabled = true;
2863 if (strncmp(str, "force_isolation", 15) == 0)
2864 amd_iommu_force_isolation = true;
2865 }
2866
2867 return 1;
2868}
2869
2870static int __init parse_ivrs_ioapic(char *str)
2871{
2872 unsigned int bus, dev, fn;
2873 int ret, id, i;
2874 u16 devid;
2875
2876 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2877
2878 if (ret != 4) {
2879 pr_err("Invalid command line: ivrs_ioapic%s\n", str);
2880 return 1;
2881 }
2882
2883 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2884 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2885 str);
2886 return 1;
2887 }
2888
2889 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2890
2891 cmdline_maps = true;
2892 i = early_ioapic_map_size++;
2893 early_ioapic_map[i].id = id;
2894 early_ioapic_map[i].devid = devid;
2895 early_ioapic_map[i].cmd_line = true;
2896
2897 return 1;
2898}
2899
2900static int __init parse_ivrs_hpet(char *str)
2901{
2902 unsigned int bus, dev, fn;
2903 int ret, id, i;
2904 u16 devid;
2905
2906 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2907
2908 if (ret != 4) {
2909 pr_err("Invalid command line: ivrs_hpet%s\n", str);
2910 return 1;
2911 }
2912
2913 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2914 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n",
2915 str);
2916 return 1;
2917 }
2918
2919 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2920
2921 cmdline_maps = true;
2922 i = early_hpet_map_size++;
2923 early_hpet_map[i].id = id;
2924 early_hpet_map[i].devid = devid;
2925 early_hpet_map[i].cmd_line = true;
2926
2927 return 1;
2928}
2929
2930static int __init parse_ivrs_acpihid(char *str)
2931{
2932 u32 bus, dev, fn;
2933 char *hid, *uid, *p;
2934 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2935 int ret, i;
2936
2937 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2938 if (ret != 4) {
2939 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str);
2940 return 1;
2941 }
2942
2943 p = acpiid;
2944 hid = strsep(&p, ":");
2945 uid = p;
2946
2947 if (!hid || !(*hid) || !uid) {
2948 pr_err("Invalid command line: hid or uid\n");
2949 return 1;
2950 }
2951
2952 i = early_acpihid_map_size++;
2953 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2954 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2955 early_acpihid_map[i].devid =
2956 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2957 early_acpihid_map[i].cmd_line = true;
2958
2959 return 1;
2960}
2961
2962__setup("amd_iommu_dump", parse_amd_iommu_dump);
2963__setup("amd_iommu=", parse_amd_iommu_options);
2964__setup("amd_iommu_intr=", parse_amd_iommu_intr);
2965__setup("ivrs_ioapic", parse_ivrs_ioapic);
2966__setup("ivrs_hpet", parse_ivrs_hpet);
2967__setup("ivrs_acpihid", parse_ivrs_acpihid);
2968
2969IOMMU_INIT_FINISH(amd_iommu_detect,
2970 gart_iommu_hole_init,
2971 NULL,
2972 NULL);
2973
2974bool amd_iommu_v2_supported(void)
2975{
2976 return amd_iommu_v2_present;
2977}
2978EXPORT_SYMBOL(amd_iommu_v2_supported);
2979
2980struct amd_iommu *get_amd_iommu(unsigned int idx)
2981{
2982 unsigned int i = 0;
2983 struct amd_iommu *iommu;
2984
2985 for_each_iommu(iommu)
2986 if (i++ == idx)
2987 return iommu;
2988 return NULL;
2989}
2990EXPORT_SYMBOL(get_amd_iommu);
2991
2992/****************************************************************************
2993 *
2994 * IOMMU EFR Performance Counter support functionality. This code allows
2995 * access to the IOMMU PC functionality.
2996 *
2997 ****************************************************************************/
2998
2999u8 amd_iommu_pc_get_max_banks(unsigned int idx)
3000{
3001 struct amd_iommu *iommu = get_amd_iommu(idx);
3002
3003 if (iommu)
3004 return iommu->max_banks;
3005
3006 return 0;
3007}
3008EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
3009
3010bool amd_iommu_pc_supported(void)
3011{
3012 return amd_iommu_pc_present;
3013}
3014EXPORT_SYMBOL(amd_iommu_pc_supported);
3015
3016u8 amd_iommu_pc_get_max_counters(unsigned int idx)
3017{
3018 struct amd_iommu *iommu = get_amd_iommu(idx);
3019
3020 if (iommu)
3021 return iommu->max_counters;
3022
3023 return 0;
3024}
3025EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3026
3027static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3028 u8 fxn, u64 *value, bool is_write)
3029{
3030 u32 offset;
3031 u32 max_offset_lim;
3032
3033 /* Make sure the IOMMU PC resource is available */
3034 if (!amd_iommu_pc_present)
3035 return -ENODEV;
3036
3037 /* Check for valid iommu and pc register indexing */
3038 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3039 return -ENODEV;
3040
3041 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3042
3043 /* Limit the offset to the hw defined mmio region aperture */
3044 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3045 (iommu->max_counters << 8) | 0x28);
3046 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3047 (offset > max_offset_lim))
3048 return -EINVAL;
3049
3050 if (is_write) {
3051 u64 val = *value & GENMASK_ULL(47, 0);
3052
3053 writel((u32)val, iommu->mmio_base + offset);
3054 writel((val >> 32), iommu->mmio_base + offset + 4);
3055 } else {
3056 *value = readl(iommu->mmio_base + offset + 4);
3057 *value <<= 32;
3058 *value |= readl(iommu->mmio_base + offset);
3059 *value &= GENMASK_ULL(47, 0);
3060 }
3061
3062 return 0;
3063}
3064
3065int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3066{
3067 if (!iommu)
3068 return -EINVAL;
3069
3070 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3071}
3072EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3073
3074int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3075{
3076 if (!iommu)
3077 return -EINVAL;
3078
3079 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3080}
3081EXPORT_SYMBOL(amd_iommu_pc_set_reg);
A mirror of Linus' kernel repository