]> git.ipfire.org Git - people/ms/u-boot.git/blame_incremental - drivers/mmc/omap_hsmmc.c
projects / people / ms / u-boot.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
mmc: omap_hsmmc: Enable Auto command (CMD12) enable
[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c
... / ...
CommitLineData
1/*
2 * (C) Copyright 2008
3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
12 * the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <common.h>
27#include <malloc.h>
28#include <memalign.h>
29#include <mmc.h>
30#include <part.h>
31#include <i2c.h>
32#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
33#include <palmas.h>
34#endif
35#include <asm/io.h>
36#include <asm/arch/mmc_host_def.h>
37#if !defined(CONFIG_SOC_KEYSTONE)
38#include <asm/gpio.h>
39#include <asm/arch/sys_proto.h>
40#endif
41#ifdef CONFIG_MMC_OMAP36XX_PINS
42#include <asm/arch/mux.h>
43#endif
44#include <dm.h>
45
46DECLARE_GLOBAL_DATA_PTR;
47
48/* simplify defines to OMAP_HSMMC_USE_GPIO */
49#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
50 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
51#define OMAP_HSMMC_USE_GPIO
52#else
53#undef OMAP_HSMMC_USE_GPIO
54#endif
55
56/* common definitions for all OMAPs */
57#define SYSCTL_SRC (1 << 25)
58#define SYSCTL_SRD (1 << 26)
59
60struct omap_hsmmc_data {
61 struct hsmmc *base_addr;
62#if !CONFIG_IS_ENABLED(DM_MMC)
63 struct mmc_config cfg;
64#endif
65#ifdef OMAP_HSMMC_USE_GPIO
66#if CONFIG_IS_ENABLED(DM_MMC)
67 struct gpio_desc cd_gpio; /* Change Detect GPIO */
68 struct gpio_desc wp_gpio; /* Write Protect GPIO */
69 bool cd_inverted;
70#else
71 int cd_gpio;
72 int wp_gpio;
73#endif
74#endif
75 u8 controller_flags;
76#ifndef CONFIG_OMAP34XX
77 struct omap_hsmmc_adma_desc *adma_desc_table;
78 uint desc_slot;
79#endif
80};
81
82#ifndef CONFIG_OMAP34XX
83struct omap_hsmmc_adma_desc {
84 u8 attr;
85 u8 reserved;
86 u16 len;
87 u32 addr;
88};
89
90#define ADMA_MAX_LEN 63488
91
92/* Decriptor table defines */
93#define ADMA_DESC_ATTR_VALID BIT(0)
94#define ADMA_DESC_ATTR_END BIT(1)
95#define ADMA_DESC_ATTR_INT BIT(2)
96#define ADMA_DESC_ATTR_ACT1 BIT(4)
97#define ADMA_DESC_ATTR_ACT2 BIT(5)
98
99#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
100#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
101#endif
102
103/* If we fail after 1 second wait, something is really bad */
104#define MAX_RETRY_MS 1000
105
106/* DMA transfers can take a long time if a lot a data is transferred.
107 * The timeout must take in account the amount of data. Let's assume
108 * that the time will never exceed 333 ms per MB (in other word we assume
109 * that the bandwidth is always above 3MB/s).
110 */
111#define DMA_TIMEOUT_PER_MB 333
112#define OMAP_HSMMC_USE_ADMA BIT(2)
113
114static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
115static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
116 unsigned int siz);
117
118static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
119{
120#if CONFIG_IS_ENABLED(DM_MMC)
121 return dev_get_priv(mmc->dev);
122#else
123 return (struct omap_hsmmc_data *)mmc->priv;
124#endif
125}
126static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
127{
128#if CONFIG_IS_ENABLED(DM_MMC)
129 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
130 return &plat->cfg;
131#else
132 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
133#endif
134}
135
136#if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
137static int omap_mmc_setup_gpio_in(int gpio, const char *label)
138{
139 int ret;
140
141#ifndef CONFIG_DM_GPIO
142 if (!gpio_is_valid(gpio))
143 return -1;
144#endif
145 ret = gpio_request(gpio, label);
146 if (ret)
147 return ret;
148
149 ret = gpio_direction_input(gpio);
150 if (ret)
151 return ret;
152
153 return gpio;
154}
155#endif
156
157static unsigned char mmc_board_init(struct mmc *mmc)
158{
159#if defined(CONFIG_OMAP34XX)
160 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
161 t2_t *t2_base = (t2_t *)T2_BASE;
162 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
163 u32 pbias_lite;
164#ifdef CONFIG_MMC_OMAP36XX_PINS
165 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
166#endif
167
168 pbias_lite = readl(&t2_base->pbias_lite);
169 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
170#ifdef CONFIG_TARGET_OMAP3_CAIRO
171 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
172 pbias_lite &= ~PBIASLITEVMODE0;
173#endif
174#ifdef CONFIG_MMC_OMAP36XX_PINS
175 if (get_cpu_family() == CPU_OMAP36XX) {
176 /* Disable extended drain IO before changing PBIAS */
177 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
178 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
179 }
180#endif
181 writel(pbias_lite, &t2_base->pbias_lite);
182
183 writel(pbias_lite | PBIASLITEPWRDNZ1 |
184 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
185 &t2_base->pbias_lite);
186
187#ifdef CONFIG_MMC_OMAP36XX_PINS
188 if (get_cpu_family() == CPU_OMAP36XX)
189 /* Enable extended drain IO after changing PBIAS */
190 writel(wkup_ctrl |
191 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
192 OMAP34XX_CTRL_WKUP_CTRL);
193#endif
194 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
195 &t2_base->devconf0);
196
197 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
198 &t2_base->devconf1);
199
200 /* Change from default of 52MHz to 26MHz if necessary */
201 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
202 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
203 &t2_base->ctl_prog_io1);
204
205 writel(readl(&prcm_base->fclken1_core) |
206 EN_MMC1 | EN_MMC2 | EN_MMC3,
207 &prcm_base->fclken1_core);
208
209 writel(readl(&prcm_base->iclken1_core) |
210 EN_MMC1 | EN_MMC2 | EN_MMC3,
211 &prcm_base->iclken1_core);
212#endif
213
214#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
215 /* PBIAS config needed for MMC1 only */
216 if (mmc_get_blk_desc(mmc)->devnum == 0)
217 vmmc_pbias_config(LDO_VOLT_3V0);
218#endif
219
220 return 0;
221}
222
223void mmc_init_stream(struct hsmmc *mmc_base)
224{
225 ulong start;
226
227 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
228
229 writel(MMC_CMD0, &mmc_base->cmd);
230 start = get_timer(0);
231 while (!(readl(&mmc_base->stat) & CC_MASK)) {
232 if (get_timer(0) - start > MAX_RETRY_MS) {
233 printf("%s: timedout waiting for cc!\n", __func__);
234 return;
235 }
236 }
237 writel(CC_MASK, &mmc_base->stat)
238 ;
239 writel(MMC_CMD0, &mmc_base->cmd)
240 ;
241 start = get_timer(0);
242 while (!(readl(&mmc_base->stat) & CC_MASK)) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for cc2!\n", __func__);
245 return;
246 }
247 }
248 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
249}
250
251static int omap_hsmmc_init_setup(struct mmc *mmc)
252{
253 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
254 struct hsmmc *mmc_base;
255 unsigned int reg_val;
256 unsigned int dsor;
257 ulong start;
258
259 mmc_base = priv->base_addr;
260 mmc_board_init(mmc);
261
262 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
263 &mmc_base->sysconfig);
264 start = get_timer(0);
265 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
266 if (get_timer(0) - start > MAX_RETRY_MS) {
267 printf("%s: timedout waiting for cc2!\n", __func__);
268 return -ETIMEDOUT;
269 }
270 }
271 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
272 start = get_timer(0);
273 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s: timedout waiting for softresetall!\n",
276 __func__);
277 return -ETIMEDOUT;
278 }
279 }
280#ifndef CONFIG_OMAP34XX
281 reg_val = readl(&mmc_base->hl_hwinfo);
282 if (reg_val & MADMA_EN)
283 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
284#endif
285 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
286 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
287 &mmc_base->capa);
288
289 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
290
291 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
292 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
293 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
294
295 dsor = 240;
296 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
297 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
298 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
299 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
300 start = get_timer(0);
301 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
302 if (get_timer(0) - start > MAX_RETRY_MS) {
303 printf("%s: timedout waiting for ics!\n", __func__);
304 return -ETIMEDOUT;
305 }
306 }
307 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
308
309 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
310
311 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
312 IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC |
313 IE_CC, &mmc_base->ie);
314
315 mmc_init_stream(mmc_base);
316
317 return 0;
318}
319
320/*
321 * MMC controller internal finite state machine reset
322 *
323 * Used to reset command or data internal state machines, using respectively
324 * SRC or SRD bit of SYSCTL register
325 */
326static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
327{
328 ulong start;
329
330 mmc_reg_out(&mmc_base->sysctl, bit, bit);
331
332 /*
333 * CMD(DAT) lines reset procedures are slightly different
334 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
335 * According to OMAP3 TRM:
336 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
337 * returns to 0x0.
338 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
339 * procedure steps must be as follows:
340 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
341 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
342 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
343 * 3. Wait until the SRC (SRD) bit returns to 0x0
344 * (reset procedure is completed).
345 */
346#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
347 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
348 if (!(readl(&mmc_base->sysctl) & bit)) {
349 start = get_timer(0);
350 while (!(readl(&mmc_base->sysctl) & bit)) {
351 if (get_timer(0) - start > MAX_RETRY_MS)
352 return;
353 }
354 }
355#endif
356 start = get_timer(0);
357 while ((readl(&mmc_base->sysctl) & bit) != 0) {
358 if (get_timer(0) - start > MAX_RETRY_MS) {
359 printf("%s: timedout waiting for sysctl %x to clear\n",
360 __func__, bit);
361 return;
362 }
363 }
364}
365
366#ifndef CONFIG_OMAP34XX
367static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
368{
369 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
370 struct omap_hsmmc_adma_desc *desc;
371 u8 attr;
372
373 desc = &priv->adma_desc_table[priv->desc_slot];
374
375 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
376 if (!end)
377 priv->desc_slot++;
378 else
379 attr |= ADMA_DESC_ATTR_END;
380
381 desc->len = len;
382 desc->addr = (u32)buf;
383 desc->reserved = 0;
384 desc->attr = attr;
385}
386
387static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
388 struct mmc_data *data)
389{
390 uint total_len = data->blocksize * data->blocks;
391 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
392 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
393 int i = desc_count;
394 char *buf;
395
396 priv->desc_slot = 0;
397 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
398 memalign(ARCH_DMA_MINALIGN, desc_count *
399 sizeof(struct omap_hsmmc_adma_desc));
400
401 if (data->flags & MMC_DATA_READ)
402 buf = data->dest;
403 else
404 buf = (char *)data->src;
405
406 while (--i) {
407 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
408 buf += ADMA_MAX_LEN;
409 total_len -= ADMA_MAX_LEN;
410 }
411
412 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
413
414 flush_dcache_range((long)priv->adma_desc_table,
415 (long)priv->adma_desc_table +
416 ROUND(desc_count *
417 sizeof(struct omap_hsmmc_adma_desc),
418 ARCH_DMA_MINALIGN));
419}
420
421static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
422{
423 struct hsmmc *mmc_base;
424 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
425 u32 val;
426 char *buf;
427
428 mmc_base = priv->base_addr;
429 omap_hsmmc_prepare_adma_table(mmc, data);
430
431 if (data->flags & MMC_DATA_READ)
432 buf = data->dest;
433 else
434 buf = (char *)data->src;
435
436 val = readl(&mmc_base->hctl);
437 val |= DMA_SELECT;
438 writel(val, &mmc_base->hctl);
439
440 val = readl(&mmc_base->con);
441 val |= DMA_MASTER;
442 writel(val, &mmc_base->con);
443
444 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
445
446 flush_dcache_range((u32)buf,
447 (u32)buf +
448 ROUND(data->blocksize * data->blocks,
449 ARCH_DMA_MINALIGN));
450}
451
452static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
453{
454 struct hsmmc *mmc_base;
455 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
456 u32 val;
457
458 mmc_base = priv->base_addr;
459
460 val = readl(&mmc_base->con);
461 val &= ~DMA_MASTER;
462 writel(val, &mmc_base->con);
463
464 val = readl(&mmc_base->hctl);
465 val &= ~DMA_SELECT;
466 writel(val, &mmc_base->hctl);
467
468 kfree(priv->adma_desc_table);
469}
470#else
471#define omap_hsmmc_adma_desc
472#define omap_hsmmc_prepare_adma_table
473#define omap_hsmmc_prepare_data
474#define omap_hsmmc_dma_cleanup
475#endif
476
477#if !CONFIG_IS_ENABLED(DM_MMC)
478static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
479 struct mmc_data *data)
480{
481 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
482#else
483static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
484 struct mmc_data *data)
485{
486 struct omap_hsmmc_data *priv = dev_get_priv(dev);
487#ifndef CONFIG_OMAP34XX
488 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
489 struct mmc *mmc = upriv->mmc;
490#endif
491#endif
492 struct hsmmc *mmc_base;
493 unsigned int flags, mmc_stat;
494 ulong start;
495
496 mmc_base = priv->base_addr;
497
498 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
499 return 0;
500
501 start = get_timer(0);
502 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
503 if (get_timer(0) - start > MAX_RETRY_MS) {
504 printf("%s: timedout waiting on cmd inhibit to clear\n",
505 __func__);
506 return -ETIMEDOUT;
507 }
508 }
509 writel(0xFFFFFFFF, &mmc_base->stat);
510 start = get_timer(0);
511 while (readl(&mmc_base->stat)) {
512 if (get_timer(0) - start > MAX_RETRY_MS) {
513 printf("%s: timedout waiting for STAT (%x) to clear\n",
514 __func__, readl(&mmc_base->stat));
515 return -ETIMEDOUT;
516 }
517 }
518 /*
519 * CMDREG
520 * CMDIDX[13:8] : Command index
521 * DATAPRNT[5] : Data Present Select
522 * ENCMDIDX[4] : Command Index Check Enable
523 * ENCMDCRC[3] : Command CRC Check Enable
524 * RSPTYP[1:0]
525 * 00 = No Response
526 * 01 = Length 136
527 * 10 = Length 48
528 * 11 = Length 48 Check busy after response
529 */
530 /* Delay added before checking the status of frq change
531 * retry not supported by mmc.c(core file)
532 */
533 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
534 udelay(50000); /* wait 50 ms */
535
536 if (!(cmd->resp_type & MMC_RSP_PRESENT))
537 flags = 0;
538 else if (cmd->resp_type & MMC_RSP_136)
539 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
540 else if (cmd->resp_type & MMC_RSP_BUSY)
541 flags = RSP_TYPE_LGHT48B;
542 else
543 flags = RSP_TYPE_LGHT48;
544
545 /* enable default flags */
546 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
547 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
548
549 if (cmd->resp_type & MMC_RSP_CRC)
550 flags |= CCCE_CHECK;
551 if (cmd->resp_type & MMC_RSP_OPCODE)
552 flags |= CICE_CHECK;
553
554 if (data) {
555 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
556 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
557 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
558 data->blocksize = 512;
559 writel(data->blocksize | (data->blocks << 16),
560 &mmc_base->blk);
561 } else
562 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
563
564 if (data->flags & MMC_DATA_READ)
565 flags |= (DP_DATA | DDIR_READ);
566 else
567 flags |= (DP_DATA | DDIR_WRITE);
568
569#ifndef CONFIG_OMAP34XX
570 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
571 !mmc_is_tuning_cmd(cmd->cmdidx)) {
572 omap_hsmmc_prepare_data(mmc, data);
573 flags |= DE_ENABLE;
574 }
575#endif
576 }
577
578 writel(cmd->cmdarg, &mmc_base->arg);
579 udelay(20); /* To fix "No status update" error on eMMC */
580 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
581
582 start = get_timer(0);
583 do {
584 mmc_stat = readl(&mmc_base->stat);
585 if (get_timer(start) > MAX_RETRY_MS) {
586 printf("%s : timeout: No status update\n", __func__);
587 return -ETIMEDOUT;
588 }
589 } while (!mmc_stat);
590
591 if ((mmc_stat & IE_CTO) != 0) {
592 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
593 return -ETIMEDOUT;
594 } else if ((mmc_stat & ERRI_MASK) != 0)
595 return -1;
596
597 if (mmc_stat & CC_MASK) {
598 writel(CC_MASK, &mmc_base->stat);
599 if (cmd->resp_type & MMC_RSP_PRESENT) {
600 if (cmd->resp_type & MMC_RSP_136) {
601 /* response type 2 */
602 cmd->response[3] = readl(&mmc_base->rsp10);
603 cmd->response[2] = readl(&mmc_base->rsp32);
604 cmd->response[1] = readl(&mmc_base->rsp54);
605 cmd->response[0] = readl(&mmc_base->rsp76);
606 } else
607 /* response types 1, 1b, 3, 4, 5, 6 */
608 cmd->response[0] = readl(&mmc_base->rsp10);
609 }
610 }
611
612#ifndef CONFIG_OMAP34XX
613 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
614 !mmc_is_tuning_cmd(cmd->cmdidx)) {
615 u32 sz_mb, timeout;
616
617 if (mmc_stat & IE_ADMAE) {
618 omap_hsmmc_dma_cleanup(mmc);
619 return -EIO;
620 }
621
622 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
623 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
624 if (timeout < MAX_RETRY_MS)
625 timeout = MAX_RETRY_MS;
626
627 start = get_timer(0);
628 do {
629 mmc_stat = readl(&mmc_base->stat);
630 if (mmc_stat & TC_MASK) {
631 writel(readl(&mmc_base->stat) | TC_MASK,
632 &mmc_base->stat);
633 break;
634 }
635 if (get_timer(start) > timeout) {
636 printf("%s : DMA timeout: No status update\n",
637 __func__);
638 return -ETIMEDOUT;
639 }
640 } while (1);
641
642 omap_hsmmc_dma_cleanup(mmc);
643 return 0;
644 }
645#endif
646
647 if (data && (data->flags & MMC_DATA_READ)) {
648 mmc_read_data(mmc_base, data->dest,
649 data->blocksize * data->blocks);
650 } else if (data && (data->flags & MMC_DATA_WRITE)) {
651 mmc_write_data(mmc_base, data->src,
652 data->blocksize * data->blocks);
653 }
654 return 0;
655}
656
657static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
658{
659 unsigned int *output_buf = (unsigned int *)buf;
660 unsigned int mmc_stat;
661 unsigned int count;
662
663 /*
664 * Start Polled Read
665 */
666 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
667 count /= 4;
668
669 while (size) {
670 ulong start = get_timer(0);
671 do {
672 mmc_stat = readl(&mmc_base->stat);
673 if (get_timer(0) - start > MAX_RETRY_MS) {
674 printf("%s: timedout waiting for status!\n",
675 __func__);
676 return -ETIMEDOUT;
677 }
678 } while (mmc_stat == 0);
679
680 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
681 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
682
683 if ((mmc_stat & ERRI_MASK) != 0)
684 return 1;
685
686 if (mmc_stat & BRR_MASK) {
687 unsigned int k;
688
689 writel(readl(&mmc_base->stat) | BRR_MASK,
690 &mmc_base->stat);
691 for (k = 0; k < count; k++) {
692 *output_buf = readl(&mmc_base->data);
693 output_buf++;
694 }
695 size -= (count*4);
696 }
697
698 if (mmc_stat & BWR_MASK)
699 writel(readl(&mmc_base->stat) | BWR_MASK,
700 &mmc_base->stat);
701
702 if (mmc_stat & TC_MASK) {
703 writel(readl(&mmc_base->stat) | TC_MASK,
704 &mmc_base->stat);
705 break;
706 }
707 }
708 return 0;
709}
710
711static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
712 unsigned int size)
713{
714 unsigned int *input_buf = (unsigned int *)buf;
715 unsigned int mmc_stat;
716 unsigned int count;
717
718 /*
719 * Start Polled Write
720 */
721 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
722 count /= 4;
723
724 while (size) {
725 ulong start = get_timer(0);
726 do {
727 mmc_stat = readl(&mmc_base->stat);
728 if (get_timer(0) - start > MAX_RETRY_MS) {
729 printf("%s: timedout waiting for status!\n",
730 __func__);
731 return -ETIMEDOUT;
732 }
733 } while (mmc_stat == 0);
734
735 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
736 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
737
738 if ((mmc_stat & ERRI_MASK) != 0)
739 return 1;
740
741 if (mmc_stat & BWR_MASK) {
742 unsigned int k;
743
744 writel(readl(&mmc_base->stat) | BWR_MASK,
745 &mmc_base->stat);
746 for (k = 0; k < count; k++) {
747 writel(*input_buf, &mmc_base->data);
748 input_buf++;
749 }
750 size -= (count*4);
751 }
752
753 if (mmc_stat & BRR_MASK)
754 writel(readl(&mmc_base->stat) | BRR_MASK,
755 &mmc_base->stat);
756
757 if (mmc_stat & TC_MASK) {
758 writel(readl(&mmc_base->stat) | TC_MASK,
759 &mmc_base->stat);
760 break;
761 }
762 }
763 return 0;
764}
765
766#if !CONFIG_IS_ENABLED(DM_MMC)
767static int omap_hsmmc_set_ios(struct mmc *mmc)
768{
769 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
770#else
771static int omap_hsmmc_set_ios(struct udevice *dev)
772{
773 struct omap_hsmmc_data *priv = dev_get_priv(dev);
774 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
775 struct mmc *mmc = upriv->mmc;
776#endif
777 struct hsmmc *mmc_base;
778 unsigned int dsor = 0;
779 ulong start;
780
781 mmc_base = priv->base_addr;
782 /* configue bus width */
783 switch (mmc->bus_width) {
784 case 8:
785 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
786 &mmc_base->con);
787 break;
788
789 case 4:
790 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
791 &mmc_base->con);
792 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
793 &mmc_base->hctl);
794 break;
795
796 case 1:
797 default:
798 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
799 &mmc_base->con);
800 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
801 &mmc_base->hctl);
802 break;
803 }
804
805 /* configure clock with 96Mhz system clock.
806 */
807 if (mmc->clock != 0) {
808 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
809 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
810 dsor++;
811 }
812
813 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
814 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
815
816 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
817 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
818
819 start = get_timer(0);
820 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
821 if (get_timer(0) - start > MAX_RETRY_MS) {
822 printf("%s: timedout waiting for ics!\n", __func__);
823 return -ETIMEDOUT;
824 }
825 }
826 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
827
828 return 0;
829}
830
831#ifdef OMAP_HSMMC_USE_GPIO
832#if CONFIG_IS_ENABLED(DM_MMC)
833static int omap_hsmmc_getcd(struct udevice *dev)
834{
835 struct omap_hsmmc_data *priv = dev_get_priv(dev);
836 int value;
837
838 value = dm_gpio_get_value(&priv->cd_gpio);
839 /* if no CD return as 1 */
840 if (value < 0)
841 return 1;
842
843 if (priv->cd_inverted)
844 return !value;
845 return value;
846}
847
848static int omap_hsmmc_getwp(struct udevice *dev)
849{
850 struct omap_hsmmc_data *priv = dev_get_priv(dev);
851 int value;
852
853 value = dm_gpio_get_value(&priv->wp_gpio);
854 /* if no WP return as 0 */
855 if (value < 0)
856 return 0;
857 return value;
858}
859#else
860static int omap_hsmmc_getcd(struct mmc *mmc)
861{
862 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
863 int cd_gpio;
864
865 /* if no CD return as 1 */
866 cd_gpio = priv->cd_gpio;
867 if (cd_gpio < 0)
868 return 1;
869
870 /* NOTE: assumes card detect signal is active-low */
871 return !gpio_get_value(cd_gpio);
872}
873
874static int omap_hsmmc_getwp(struct mmc *mmc)
875{
876 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
877 int wp_gpio;
878
879 /* if no WP return as 0 */
880 wp_gpio = priv->wp_gpio;
881 if (wp_gpio < 0)
882 return 0;
883
884 /* NOTE: assumes write protect signal is active-high */
885 return gpio_get_value(wp_gpio);
886}
887#endif
888#endif
889
890#if CONFIG_IS_ENABLED(DM_MMC)
891static const struct dm_mmc_ops omap_hsmmc_ops = {
892 .send_cmd = omap_hsmmc_send_cmd,
893 .set_ios = omap_hsmmc_set_ios,
894#ifdef OMAP_HSMMC_USE_GPIO
895 .get_cd = omap_hsmmc_getcd,
896 .get_wp = omap_hsmmc_getwp,
897#endif
898};
899#else
900static const struct mmc_ops omap_hsmmc_ops = {
901 .send_cmd = omap_hsmmc_send_cmd,
902 .set_ios = omap_hsmmc_set_ios,
903 .init = omap_hsmmc_init_setup,
904#ifdef OMAP_HSMMC_USE_GPIO
905 .getcd = omap_hsmmc_getcd,
906 .getwp = omap_hsmmc_getwp,
907#endif
908};
909#endif
910
911#if !CONFIG_IS_ENABLED(DM_MMC)
912int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
913 int wp_gpio)
914{
915 struct mmc *mmc;
916 struct omap_hsmmc_data *priv;
917 struct mmc_config *cfg;
918 uint host_caps_val;
919
920 priv = malloc(sizeof(*priv));
921 if (priv == NULL)
922 return -1;
923
924 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
925
926 switch (dev_index) {
927 case 0:
928 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
929 break;
930#ifdef OMAP_HSMMC2_BASE
931 case 1:
932 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
933#if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
934 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
935 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
936 defined(CONFIG_HSMMC2_8BIT)
937 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
938 host_caps_val |= MMC_MODE_8BIT;
939#endif
940 break;
941#endif
942#ifdef OMAP_HSMMC3_BASE
943 case 2:
944 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
945#if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
946 /* Enable 8-bit interface for eMMC on DRA7XX */
947 host_caps_val |= MMC_MODE_8BIT;
948#endif
949 break;
950#endif
951 default:
952 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
953 return 1;
954 }
955#ifdef OMAP_HSMMC_USE_GPIO
956 /* on error gpio values are set to -1, which is what we want */
957 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
958 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
959#endif
960
961 cfg = &priv->cfg;
962
963 cfg->name = "OMAP SD/MMC";
964 cfg->ops = &omap_hsmmc_ops;
965
966 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
967 cfg->host_caps = host_caps_val & ~host_caps_mask;
968
969 cfg->f_min = 400000;
970
971 if (f_max != 0)
972 cfg->f_max = f_max;
973 else {
974 if (cfg->host_caps & MMC_MODE_HS) {
975 if (cfg->host_caps & MMC_MODE_HS_52MHz)
976 cfg->f_max = 52000000;
977 else
978 cfg->f_max = 26000000;
979 } else
980 cfg->f_max = 20000000;
981 }
982
983 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
984
985#if defined(CONFIG_OMAP34XX)
986 /*
987 * Silicon revs 2.1 and older do not support multiblock transfers.
988 */
989 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
990 cfg->b_max = 1;
991#endif
992 mmc = mmc_create(cfg, priv);
993 if (mmc == NULL)
994 return -1;
995
996 return 0;
997}
998#else
999#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1000static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1001{
1002 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1003 struct mmc_config *cfg = &plat->cfg;
1004 const void *fdt = gd->fdt_blob;
1005 int node = dev_of_offset(dev);
1006 int val;
1007
1008 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1009 sizeof(struct hsmmc *),
1010 MAP_NOCACHE);
1011
1012 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
1013 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1014 if (val < 0) {
1015 printf("error: bus-width property missing\n");
1016 return -ENOENT;
1017 }
1018
1019 switch (val) {
1020 case 0x8:
1021 cfg->host_caps |= MMC_MODE_8BIT;
1022 case 0x4:
1023 cfg->host_caps |= MMC_MODE_4BIT;
1024 break;
1025 default:
1026 printf("error: invalid bus-width property\n");
1027 return -ENOENT;
1028 }
1029
1030 cfg->f_min = 400000;
1031 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
1032 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1033 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1034
1035#ifdef OMAP_HSMMC_USE_GPIO
1036 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1037#endif
1038
1039 return 0;
1040}
1041#endif
1042
1043#ifdef CONFIG_BLK
1044
1045static int omap_hsmmc_bind(struct udevice *dev)
1046{
1047 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1048
1049 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1050}
1051#endif
1052static int omap_hsmmc_probe(struct udevice *dev)
1053{
1054 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1055 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1056 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1057 struct mmc_config *cfg = &plat->cfg;
1058 struct mmc *mmc;
1059
1060 cfg->name = "OMAP SD/MMC";
1061 priv->base_addr = plat->base_addr;
1062#ifdef OMAP_HSMMC_USE_GPIO
1063 priv->cd_inverted = plat->cd_inverted;
1064#endif
1065
1066#ifdef CONFIG_BLK
1067 mmc = &plat->mmc;
1068#else
1069 mmc = mmc_create(cfg, priv);
1070 if (mmc == NULL)
1071 return -1;
1072#endif
1073
1074#if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1075 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1076 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1077#endif
1078
1079 mmc->dev = dev;
1080 upriv->mmc = mmc;
1081
1082 return omap_hsmmc_init_setup(mmc);
1083}
1084
1085#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1086static const struct udevice_id omap_hsmmc_ids[] = {
1087 { .compatible = "ti,omap3-hsmmc" },
1088 { .compatible = "ti,omap4-hsmmc" },
1089 { .compatible = "ti,am33xx-hsmmc" },
1090 { }
1091};
1092#endif
1093
1094U_BOOT_DRIVER(omap_hsmmc) = {
1095 .name = "omap_hsmmc",
1096 .id = UCLASS_MMC,
1097#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1098 .of_match = omap_hsmmc_ids,
1099 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1100 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1101#endif
1102#ifdef CONFIG_BLK
1103 .bind = omap_hsmmc_bind,
1104#endif
1105 .ops = &omap_hsmmc_ops,
1106 .probe = omap_hsmmc_probe,
1107 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1108 .flags = DM_FLAG_PRE_RELOC,
1109};
1110#endif
"Das U-Boot" Source Tree