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1 | /* | |
2 | * Xilinx xps_ll_temac ethernet driver for u-boot | |
3 | * | |
4 | * LL_TEMAC interface | |
5 | * | |
6 | * Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net> | |
7 | * Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu> | |
8 | * Copyright (C) 2008 - 2011 PetaLogix | |
9 | * | |
10 | * Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver | |
11 | * Copyright (C) 2008 Nissin Systems Co.,Ltd. | |
12 | * March 2008 created | |
13 | * | |
14 | * SPDX-License-Identifier: GPL-2.0+ | |
15 | * | |
16 | * [0]: http://www.xilinx.com/support/documentation | |
17 | * | |
18 | * [S]: [0]/ip_documentation/xps_ll_temac.pdf | |
19 | * [A]: [0]/application_notes/xapp1041.pdf | |
20 | */ | |
21 | #ifndef _XILINX_LL_TEMAC_ | |
22 | #define _XILINX_LL_TEMAC_ | |
23 | ||
24 | #include <config.h> | |
25 | #include <net.h> | |
26 | #include <phy.h> | |
27 | #include <miiphy.h> | |
28 | ||
29 | #include <asm/types.h> | |
30 | #include <asm/byteorder.h> | |
31 | ||
32 | #include "xilinx_ll_temac_sdma.h" | |
33 | ||
34 | #if !defined(__BIG_ENDIAN) | |
35 | # error LL_TEMAC requires big endianess | |
36 | #endif | |
37 | ||
38 | /* | |
39 | * TEMAC Memory and Register Definition | |
40 | * | |
41 | * [1]: [0]/ip_documentation/xps_ll_temac.pdf | |
42 | * page 19, Memory and Register Descriptions | |
43 | */ | |
44 | struct temac_reg { | |
45 | /* direct soft registers (low part) */ | |
46 | u32 raf; /* Reset and Address Filter */ | |
47 | u32 tpf; /* Transmit Pause Frame */ | |
48 | u32 ifgp; /* Transmit Inter Frame Gap Adjustment */ | |
49 | u32 is; /* Interrupt Status */ | |
50 | u32 ip; /* Interrupt Pending */ | |
51 | u32 ie; /* Interrupt Enable */ | |
52 | u32 ttag; /* Transmit VLAN Tag */ | |
53 | u32 rtag; /* Receive VLAN Tag */ | |
54 | /* hard TEMAC registers */ | |
55 | u32 msw; /* Most Significant Word Data */ | |
56 | u32 lsw; /* Least Significant Word Data */ | |
57 | u32 ctl; /* Control */ | |
58 | u32 rdy; /* Ready Status */ | |
59 | /* direct soft registers (high part) */ | |
60 | u32 uawl; /* Unicast Address Word Lower */ | |
61 | u32 uawu; /* Unicast Address Word Upper */ | |
62 | u32 tpid0; /* VLAN TPID Word 0 */ | |
63 | u32 tpid1; /* VLAN TPID Word 1 */ | |
64 | }; | |
65 | ||
66 | /* Reset and Address Filter Registers (raf), [1] p25 */ | |
67 | #define RAF_SR (1 << 13) | |
68 | #define RAF_EMFE (1 << 12) | |
69 | #define RAF_NFE (1 << 11) | |
70 | #define RAF_RVSTM_POS 9 | |
71 | #define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS) | |
72 | #define RAF_TVSTM_POS 7 | |
73 | #define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS) | |
74 | #define RAF_RVTM_POS 5 | |
75 | #define RAF_RVTM_MASK (3 << RAF_RVTM_POS) | |
76 | #define RAF_TVTM_POS 3 | |
77 | #define RAF_TVTM_MASK (3 << RAF_TVTM_POS) | |
78 | #define RAF_BCREJ (1 << 2) | |
79 | #define RAF_MCREJ (1 << 1) | |
80 | #define RAF_HTRST (1 << 0) | |
81 | ||
82 | /* Transmit Pause Frame Registers (tpf), [1] p28 */ | |
83 | #define TPF_TPFV_POS 0 | |
84 | #define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS) | |
85 | ||
86 | /* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */ | |
87 | #define IFGP_POS 0 | |
88 | #define IFGP_MASK (0xFF << IFGP_POS) | |
89 | ||
90 | /* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */ | |
91 | #define ISPE_MR (1 << 7) | |
92 | #define ISPE_RDL (1 << 6) | |
93 | #define ISPE_TC (1 << 5) | |
94 | #define ISPE_RFO (1 << 4) | |
95 | #define ISPE_RR (1 << 3) | |
96 | #define ISPE_RC (1 << 2) | |
97 | #define ISPE_AN (1 << 1) | |
98 | #define ISPE_HAC (1 << 0) | |
99 | ||
100 | /* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */ | |
101 | #define TRTAG_TPID_POS 16 | |
102 | #define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS) | |
103 | #define TRTAG_PRIO_POS 13 | |
104 | #define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS) | |
105 | #define TRTAG_CFI (1 << 12) | |
106 | #define TRTAG_VID_POS 0 | |
107 | #define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS) | |
108 | ||
109 | /* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */ | |
110 | #define MLSW_POS 0 | |
111 | #define MLSW_MASK (~0UL << MLSW_POS) | |
112 | ||
113 | /* LSW Data Register for PHY addresses (lsw), [1] p66 */ | |
114 | #define LSW_REGAD_POS 0 | |
115 | #define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS) | |
116 | #define LSW_PHYAD_POS 5 | |
117 | #define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS) | |
118 | ||
119 | /* LSW Data Register for PHY data (lsw), [1] p66 */ | |
120 | #define LSW_REGDAT_POS 0 | |
121 | #define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS) | |
122 | ||
123 | /* Control Register (ctl), [1] p47 */ | |
124 | #define CTL_WEN (1 << 15) | |
125 | #define CTL_ADDR_POS 0 | |
126 | #define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS) | |
127 | ||
128 | /* Ready Status Register Ethernet (rdy), [1] p48 */ | |
129 | #define RSE_HACS_RDY (1 << 14) | |
130 | #define RSE_CFG_WR (1 << 6) | |
131 | #define RSE_CFG_RR (1 << 5) | |
132 | #define RSE_AF_WR (1 << 4) | |
133 | #define RSE_AF_RR (1 << 3) | |
134 | #define RSE_MIIM_WR (1 << 2) | |
135 | #define RSE_MIIM_RR (1 << 1) | |
136 | #define RSE_FABR_RR (1 << 0) | |
137 | ||
138 | /* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */ | |
139 | #define UAWL_UADDR_POS 0 | |
140 | #define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS) | |
141 | #define UAWU_UADDR_POS 0 | |
142 | #define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS) | |
143 | ||
144 | /* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */ | |
145 | #define TPID0_V0_POS 0 | |
146 | #define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS) | |
147 | #define TPID0_V1_POS 16 | |
148 | #define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS) | |
149 | #define TPID1_V2_POS 0 | |
150 | #define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS) | |
151 | #define TPID1_V3_POS 16 | |
152 | #define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS) | |
153 | ||
154 | /* | |
155 | * TEMAC Indirectly Addressable Register Index Enumeration | |
156 | * | |
157 | * [0]: http://www.xilinx.com/support/documentation | |
158 | * | |
159 | * [1]: [0]/ip_documentation/xps_ll_temac.pdf | |
160 | * page 23, PLB Indirectly Addressable TEMAC Registers | |
161 | */ | |
162 | enum temac_ctrl { | |
163 | TEMAC_RCW0 = 0x200, | |
164 | TEMAC_RCW1 = 0x240, | |
165 | TEMAC_TC = 0x280, | |
166 | TEMAC_FCC = 0x2C0, | |
167 | TEMAC_EMMC = 0x300, | |
168 | TEMAC_PHYC = 0x320, | |
169 | TEMAC_MC = 0x340, | |
170 | TEMAC_UAW0 = 0x380, | |
171 | TEMAC_UAW1 = 0x384, | |
172 | TEMAC_MAW0 = 0x388, | |
173 | TEMAC_MAW1 = 0x38C, | |
174 | TEMAC_AFM = 0x390, | |
175 | TEMAC_TIS = 0x3A0, | |
176 | TEMAC_TIE = 0x3A4, | |
177 | TEMAC_MIIMWD = 0x3B0, | |
178 | TEMAC_MIIMAI = 0x3B4 | |
179 | }; | |
180 | ||
181 | /* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */ | |
182 | #define RCW0_PADDR_POS 0 | |
183 | #define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS) | |
184 | #define RCW1_RST (1 << 31) | |
185 | #define RCW1_JUM (1 << 30) | |
186 | #define RCW1_FCS (1 << 29) | |
187 | #define RCW1_RX (1 << 28) | |
188 | #define RCW1_VLAN (1 << 27) | |
189 | #define RCW1_HD (1 << 26) | |
190 | #define RCW1_LT_DIS (1 << 25) | |
191 | #define RCW1_PADDR_POS 0 | |
192 | #define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS) | |
193 | ||
194 | /* Transmit Configuration Registers (TC), [1] p52 */ | |
195 | #define TC_RST (1 << 31) | |
196 | #define TC_JUM (1 << 30) | |
197 | #define TC_FCS (1 << 29) | |
198 | #define TC_TX (1 << 28) | |
199 | #define TC_VLAN (1 << 27) | |
200 | #define TC_HD (1 << 26) | |
201 | #define TC_IFG (1 << 25) | |
202 | ||
203 | /* Flow Control Configuration Registers (FCC), [1] p54 */ | |
204 | #define FCC_FCTX (1 << 30) | |
205 | #define FCC_FCRX (1 << 29) | |
206 | ||
207 | /* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */ | |
208 | #define EMMC_LSPD_POS 30 | |
209 | #define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS) | |
210 | #define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS) | |
211 | #define EMMC_LSPD_100 (1 << EMMC_LSPD_POS) | |
212 | #define EMMC_LSPD_10 0 | |
213 | #define EMMC_RGMII (1 << 29) | |
214 | #define EMMC_SGMII (1 << 28) | |
215 | #define EMMC_GPCS (1 << 27) | |
216 | #define EMMC_HOST (1 << 26) | |
217 | #define EMMC_TX16 (1 << 25) | |
218 | #define EMMC_RX16 (1 << 24) | |
219 | ||
220 | /* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */ | |
221 | #define PHYC_SLSPD_POS 30 | |
222 | #define PHYC_SLSPD_MASK (3 << EMMC_SLSPD_POS) | |
223 | #define PHYC_SLSPD_1000 (2 << EMMC_SLSPD_POS) | |
224 | #define PHYC_SLSPD_100 (1 << EMMC_SLSPD_POS) | |
225 | #define PHYC_SLSPD_10 0 | |
226 | #define PHYC_RLSPD_POS 2 | |
227 | #define PHYC_RLSPD_MASK (3 << EMMC_RLSPD_POS) | |
228 | #define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS) | |
229 | #define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS) | |
230 | #define PHYC_RLSPD_10 0 | |
231 | #define PHYC_RGMII_HD (1 << 1) | |
232 | #define PHYC_RGMII_LINK (1 << 0) | |
233 | ||
234 | /* Management Configuration Registers (MC), [1] p57 */ | |
235 | #define MC_MDIOEN (1 << 6) | |
236 | #define MC_CLKDIV_POS 0 | |
237 | #define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS) | |
238 | ||
239 | /* | |
240 | * fHOSTCLK fMDC = fHOSTCLK | |
241 | * fMDC = ------------------- ---------> MC_CLKDIV = -------- - 1 | |
242 | * (1 + MC_CLKDIV) * 2 2.5 MHz 5MHz | |
243 | */ | |
244 | #define MC_CLKDIV(f, m) ((f / (2 * m)) - 1) | |
245 | #define MC_CLKDIV_25(f) MC_CLKDIV(f, 2500000) | |
246 | #define MC_CLKDIV_20(f) MC_CLKDIV(f, 2000000) | |
247 | #define MC_CLKDIV_15(f) MC_CLKDIV(f, 1500000) | |
248 | #define MC_CLKDIV_10(f) MC_CLKDIV(f, 1000000) | |
249 | ||
250 | /* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */ | |
251 | #define UAW0_UADDR_POS 0 | |
252 | #define UAW0_UADDR_MASK (~0UL << UAW0_UADDR_POS) | |
253 | #define UAW1_UADDR_POS 0 | |
254 | #define UAW1_UADDR_MASK (0xFFFF << UAW1_UADDR_POS) | |
255 | ||
256 | /* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */ | |
257 | #define MAW0_MADDR_POS 0 | |
258 | #define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS) | |
259 | #define MAW1_RNW (1 << 23) | |
260 | #define MAW1_MAIDX_POS 16 | |
261 | #define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS) | |
262 | #define MAW1_MADDR_POS 0 | |
263 | #define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS) | |
264 | ||
265 | /* Address Filter Mode Registers (AFM), [1] p63 */ | |
266 | #define AFM_PM (1 << 31) | |
267 | ||
268 | /* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */ | |
269 | #define TISE_CFG_W (1 << 6) | |
270 | #define TISE_CFG_R (1 << 5) | |
271 | #define TISE_AF_W (1 << 4) | |
272 | #define TISE_AF_R (1 << 3) | |
273 | #define TISE_MIIM_W (1 << 2) | |
274 | #define TISE_MIIM_R (1 << 1) | |
275 | #define TISE_FABR_R (1 << 0) | |
276 | ||
277 | /* MII Management Write Data Registers (MIIMWD), [1] p66 */ | |
278 | #define MIIMWD_DATA_POS 0 | |
279 | #define MIIMWD_DATA_MASK (0xFFFF << MIIMWD_DATA_POS) | |
280 | ||
281 | /* Ethernet interface ready status */ | |
282 | int ll_temac_check_status(struct temac_reg *regs, u32 mask); | |
283 | ||
284 | /* Indirect write to ll_temac. */ | |
285 | int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data); | |
286 | ||
287 | /* Indirect read from ll_temac. */ | |
288 | int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data); | |
289 | ||
290 | struct ll_temac { | |
291 | phys_addr_t ctrladdr; | |
292 | phys_addr_t sdma_reg_addr[SDMA_CTRL_REGNUMS]; | |
293 | ||
294 | unsigned (*in32)(phys_addr_t); | |
295 | void (*out32)(phys_addr_t, unsigned); | |
296 | ||
297 | int (*ctrlinit) (struct eth_device *); | |
298 | int (*ctrlhalt) (struct eth_device *); | |
299 | int (*ctrlreset) (struct eth_device *); | |
300 | ||
301 | int phyaddr; | |
302 | struct phy_device *phydev; | |
303 | struct mii_dev *bus; | |
304 | char mdio_busname[MDIO_NAME_LEN]; | |
305 | }; | |
306 | ||
307 | #endif /* _XILINX_LL_TEMAC_ */ |