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1 | /* | |
2 | * Virtual page mapping | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include "qemu/osdep.h" | |
20 | #include "qapi/error.h" | |
21 | #ifndef _WIN32 | |
22 | #endif | |
23 | ||
24 | #include "qemu/cutils.h" | |
25 | #include "cpu.h" | |
26 | #include "exec/exec-all.h" | |
27 | #include "exec/target_page.h" | |
28 | #include "tcg.h" | |
29 | #include "hw/qdev-core.h" | |
30 | #include "hw/qdev-properties.h" | |
31 | #if !defined(CONFIG_USER_ONLY) | |
32 | #include "hw/boards.h" | |
33 | #include "hw/xen/xen.h" | |
34 | #endif | |
35 | #include "sysemu/kvm.h" | |
36 | #include "sysemu/sysemu.h" | |
37 | #include "qemu/timer.h" | |
38 | #include "qemu/config-file.h" | |
39 | #include "qemu/error-report.h" | |
40 | #if defined(CONFIG_USER_ONLY) | |
41 | #include "qemu.h" | |
42 | #else /* !CONFIG_USER_ONLY */ | |
43 | #include "hw/hw.h" | |
44 | #include "exec/memory.h" | |
45 | #include "exec/ioport.h" | |
46 | #include "sysemu/dma.h" | |
47 | #include "sysemu/numa.h" | |
48 | #include "sysemu/hw_accel.h" | |
49 | #include "exec/address-spaces.h" | |
50 | #include "sysemu/xen-mapcache.h" | |
51 | #include "trace-root.h" | |
52 | ||
53 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
54 | #include <fcntl.h> | |
55 | #include <linux/falloc.h> | |
56 | #endif | |
57 | ||
58 | #endif | |
59 | #include "qemu/rcu_queue.h" | |
60 | #include "qemu/main-loop.h" | |
61 | #include "translate-all.h" | |
62 | #include "sysemu/replay.h" | |
63 | ||
64 | #include "exec/memory-internal.h" | |
65 | #include "exec/ram_addr.h" | |
66 | #include "exec/log.h" | |
67 | ||
68 | #include "migration/vmstate.h" | |
69 | ||
70 | #include "qemu/range.h" | |
71 | #ifndef _WIN32 | |
72 | #include "qemu/mmap-alloc.h" | |
73 | #endif | |
74 | ||
75 | #include "monitor/monitor.h" | |
76 | ||
77 | //#define DEBUG_SUBPAGE | |
78 | ||
79 | #if !defined(CONFIG_USER_ONLY) | |
80 | /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes | |
81 | * are protected by the ramlist lock. | |
82 | */ | |
83 | RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) }; | |
84 | ||
85 | static MemoryRegion *system_memory; | |
86 | static MemoryRegion *system_io; | |
87 | ||
88 | AddressSpace address_space_io; | |
89 | AddressSpace address_space_memory; | |
90 | ||
91 | MemoryRegion io_mem_rom, io_mem_notdirty; | |
92 | static MemoryRegion io_mem_unassigned; | |
93 | ||
94 | /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ | |
95 | #define RAM_PREALLOC (1 << 0) | |
96 | ||
97 | /* RAM is mmap-ed with MAP_SHARED */ | |
98 | #define RAM_SHARED (1 << 1) | |
99 | ||
100 | /* Only a portion of RAM (used_length) is actually used, and migrated. | |
101 | * This used_length size can change across reboots. | |
102 | */ | |
103 | #define RAM_RESIZEABLE (1 << 2) | |
104 | ||
105 | #endif | |
106 | ||
107 | #ifdef TARGET_PAGE_BITS_VARY | |
108 | int target_page_bits; | |
109 | bool target_page_bits_decided; | |
110 | #endif | |
111 | ||
112 | struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); | |
113 | /* current CPU in the current thread. It is only valid inside | |
114 | cpu_exec() */ | |
115 | __thread CPUState *current_cpu; | |
116 | /* 0 = Do not count executed instructions. | |
117 | 1 = Precise instruction counting. | |
118 | 2 = Adaptive rate instruction counting. */ | |
119 | int use_icount; | |
120 | ||
121 | uintptr_t qemu_host_page_size; | |
122 | intptr_t qemu_host_page_mask; | |
123 | ||
124 | bool set_preferred_target_page_bits(int bits) | |
125 | { | |
126 | /* The target page size is the lowest common denominator for all | |
127 | * the CPUs in the system, so we can only make it smaller, never | |
128 | * larger. And we can't make it smaller once we've committed to | |
129 | * a particular size. | |
130 | */ | |
131 | #ifdef TARGET_PAGE_BITS_VARY | |
132 | assert(bits >= TARGET_PAGE_BITS_MIN); | |
133 | if (target_page_bits == 0 || target_page_bits > bits) { | |
134 | if (target_page_bits_decided) { | |
135 | return false; | |
136 | } | |
137 | target_page_bits = bits; | |
138 | } | |
139 | #endif | |
140 | return true; | |
141 | } | |
142 | ||
143 | #if !defined(CONFIG_USER_ONLY) | |
144 | ||
145 | static void finalize_target_page_bits(void) | |
146 | { | |
147 | #ifdef TARGET_PAGE_BITS_VARY | |
148 | if (target_page_bits == 0) { | |
149 | target_page_bits = TARGET_PAGE_BITS_MIN; | |
150 | } | |
151 | target_page_bits_decided = true; | |
152 | #endif | |
153 | } | |
154 | ||
155 | typedef struct PhysPageEntry PhysPageEntry; | |
156 | ||
157 | struct PhysPageEntry { | |
158 | /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */ | |
159 | uint32_t skip : 6; | |
160 | /* index into phys_sections (!skip) or phys_map_nodes (skip) */ | |
161 | uint32_t ptr : 26; | |
162 | }; | |
163 | ||
164 | #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6) | |
165 | ||
166 | /* Size of the L2 (and L3, etc) page tables. */ | |
167 | #define ADDR_SPACE_BITS 64 | |
168 | ||
169 | #define P_L2_BITS 9 | |
170 | #define P_L2_SIZE (1 << P_L2_BITS) | |
171 | ||
172 | #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1) | |
173 | ||
174 | typedef PhysPageEntry Node[P_L2_SIZE]; | |
175 | ||
176 | typedef struct PhysPageMap { | |
177 | struct rcu_head rcu; | |
178 | ||
179 | unsigned sections_nb; | |
180 | unsigned sections_nb_alloc; | |
181 | unsigned nodes_nb; | |
182 | unsigned nodes_nb_alloc; | |
183 | Node *nodes; | |
184 | MemoryRegionSection *sections; | |
185 | } PhysPageMap; | |
186 | ||
187 | struct AddressSpaceDispatch { | |
188 | MemoryRegionSection *mru_section; | |
189 | /* This is a multi-level map on the physical address space. | |
190 | * The bottom level has pointers to MemoryRegionSections. | |
191 | */ | |
192 | PhysPageEntry phys_map; | |
193 | PhysPageMap map; | |
194 | }; | |
195 | ||
196 | #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK) | |
197 | typedef struct subpage_t { | |
198 | MemoryRegion iomem; | |
199 | FlatView *fv; | |
200 | hwaddr base; | |
201 | uint16_t sub_section[]; | |
202 | } subpage_t; | |
203 | ||
204 | #define PHYS_SECTION_UNASSIGNED 0 | |
205 | #define PHYS_SECTION_NOTDIRTY 1 | |
206 | #define PHYS_SECTION_ROM 2 | |
207 | #define PHYS_SECTION_WATCH 3 | |
208 | ||
209 | static void io_mem_init(void); | |
210 | static void memory_map_init(void); | |
211 | static void tcg_commit(MemoryListener *listener); | |
212 | ||
213 | static MemoryRegion io_mem_watch; | |
214 | ||
215 | /** | |
216 | * CPUAddressSpace: all the information a CPU needs about an AddressSpace | |
217 | * @cpu: the CPU whose AddressSpace this is | |
218 | * @as: the AddressSpace itself | |
219 | * @memory_dispatch: its dispatch pointer (cached, RCU protected) | |
220 | * @tcg_as_listener: listener for tracking changes to the AddressSpace | |
221 | */ | |
222 | struct CPUAddressSpace { | |
223 | CPUState *cpu; | |
224 | AddressSpace *as; | |
225 | struct AddressSpaceDispatch *memory_dispatch; | |
226 | MemoryListener tcg_as_listener; | |
227 | }; | |
228 | ||
229 | struct DirtyBitmapSnapshot { | |
230 | ram_addr_t start; | |
231 | ram_addr_t end; | |
232 | unsigned long dirty[]; | |
233 | }; | |
234 | ||
235 | #endif | |
236 | ||
237 | #if !defined(CONFIG_USER_ONLY) | |
238 | ||
239 | static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) | |
240 | { | |
241 | static unsigned alloc_hint = 16; | |
242 | if (map->nodes_nb + nodes > map->nodes_nb_alloc) { | |
243 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); | |
244 | map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); | |
245 | map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); | |
246 | alloc_hint = map->nodes_nb_alloc; | |
247 | } | |
248 | } | |
249 | ||
250 | static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) | |
251 | { | |
252 | unsigned i; | |
253 | uint32_t ret; | |
254 | PhysPageEntry e; | |
255 | PhysPageEntry *p; | |
256 | ||
257 | ret = map->nodes_nb++; | |
258 | p = map->nodes[ret]; | |
259 | assert(ret != PHYS_MAP_NODE_NIL); | |
260 | assert(ret != map->nodes_nb_alloc); | |
261 | ||
262 | e.skip = leaf ? 0 : 1; | |
263 | e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL; | |
264 | for (i = 0; i < P_L2_SIZE; ++i) { | |
265 | memcpy(&p[i], &e, sizeof(e)); | |
266 | } | |
267 | return ret; | |
268 | } | |
269 | ||
270 | static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, | |
271 | hwaddr *index, hwaddr *nb, uint16_t leaf, | |
272 | int level) | |
273 | { | |
274 | PhysPageEntry *p; | |
275 | hwaddr step = (hwaddr)1 << (level * P_L2_BITS); | |
276 | ||
277 | if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) { | |
278 | lp->ptr = phys_map_node_alloc(map, level == 0); | |
279 | } | |
280 | p = map->nodes[lp->ptr]; | |
281 | lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)]; | |
282 | ||
283 | while (*nb && lp < &p[P_L2_SIZE]) { | |
284 | if ((*index & (step - 1)) == 0 && *nb >= step) { | |
285 | lp->skip = 0; | |
286 | lp->ptr = leaf; | |
287 | *index += step; | |
288 | *nb -= step; | |
289 | } else { | |
290 | phys_page_set_level(map, lp, index, nb, leaf, level - 1); | |
291 | } | |
292 | ++lp; | |
293 | } | |
294 | } | |
295 | ||
296 | static void phys_page_set(AddressSpaceDispatch *d, | |
297 | hwaddr index, hwaddr nb, | |
298 | uint16_t leaf) | |
299 | { | |
300 | /* Wildly overreserve - it doesn't matter much. */ | |
301 | phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS); | |
302 | ||
303 | phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1); | |
304 | } | |
305 | ||
306 | /* Compact a non leaf page entry. Simply detect that the entry has a single child, | |
307 | * and update our entry so we can skip it and go directly to the destination. | |
308 | */ | |
309 | static void phys_page_compact(PhysPageEntry *lp, Node *nodes) | |
310 | { | |
311 | unsigned valid_ptr = P_L2_SIZE; | |
312 | int valid = 0; | |
313 | PhysPageEntry *p; | |
314 | int i; | |
315 | ||
316 | if (lp->ptr == PHYS_MAP_NODE_NIL) { | |
317 | return; | |
318 | } | |
319 | ||
320 | p = nodes[lp->ptr]; | |
321 | for (i = 0; i < P_L2_SIZE; i++) { | |
322 | if (p[i].ptr == PHYS_MAP_NODE_NIL) { | |
323 | continue; | |
324 | } | |
325 | ||
326 | valid_ptr = i; | |
327 | valid++; | |
328 | if (p[i].skip) { | |
329 | phys_page_compact(&p[i], nodes); | |
330 | } | |
331 | } | |
332 | ||
333 | /* We can only compress if there's only one child. */ | |
334 | if (valid != 1) { | |
335 | return; | |
336 | } | |
337 | ||
338 | assert(valid_ptr < P_L2_SIZE); | |
339 | ||
340 | /* Don't compress if it won't fit in the # of bits we have. */ | |
341 | if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { | |
342 | return; | |
343 | } | |
344 | ||
345 | lp->ptr = p[valid_ptr].ptr; | |
346 | if (!p[valid_ptr].skip) { | |
347 | /* If our only child is a leaf, make this a leaf. */ | |
348 | /* By design, we should have made this node a leaf to begin with so we | |
349 | * should never reach here. | |
350 | * But since it's so simple to handle this, let's do it just in case we | |
351 | * change this rule. | |
352 | */ | |
353 | lp->skip = 0; | |
354 | } else { | |
355 | lp->skip += p[valid_ptr].skip; | |
356 | } | |
357 | } | |
358 | ||
359 | void address_space_dispatch_compact(AddressSpaceDispatch *d) | |
360 | { | |
361 | if (d->phys_map.skip) { | |
362 | phys_page_compact(&d->phys_map, d->map.nodes); | |
363 | } | |
364 | } | |
365 | ||
366 | static inline bool section_covers_addr(const MemoryRegionSection *section, | |
367 | hwaddr addr) | |
368 | { | |
369 | /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means | |
370 | * the section must cover the entire address space. | |
371 | */ | |
372 | return int128_gethi(section->size) || | |
373 | range_covers_byte(section->offset_within_address_space, | |
374 | int128_getlo(section->size), addr); | |
375 | } | |
376 | ||
377 | static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr) | |
378 | { | |
379 | PhysPageEntry lp = d->phys_map, *p; | |
380 | Node *nodes = d->map.nodes; | |
381 | MemoryRegionSection *sections = d->map.sections; | |
382 | hwaddr index = addr >> TARGET_PAGE_BITS; | |
383 | int i; | |
384 | ||
385 | for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) { | |
386 | if (lp.ptr == PHYS_MAP_NODE_NIL) { | |
387 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
388 | } | |
389 | p = nodes[lp.ptr]; | |
390 | lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)]; | |
391 | } | |
392 | ||
393 | if (section_covers_addr(§ions[lp.ptr], addr)) { | |
394 | return §ions[lp.ptr]; | |
395 | } else { | |
396 | return §ions[PHYS_SECTION_UNASSIGNED]; | |
397 | } | |
398 | } | |
399 | ||
400 | bool memory_region_is_unassigned(MemoryRegion *mr) | |
401 | { | |
402 | return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device | |
403 | && mr != &io_mem_watch; | |
404 | } | |
405 | ||
406 | /* Called from RCU critical section */ | |
407 | static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d, | |
408 | hwaddr addr, | |
409 | bool resolve_subpage) | |
410 | { | |
411 | MemoryRegionSection *section = atomic_read(&d->mru_section); | |
412 | subpage_t *subpage; | |
413 | bool update; | |
414 | ||
415 | if (section && section != &d->map.sections[PHYS_SECTION_UNASSIGNED] && | |
416 | section_covers_addr(section, addr)) { | |
417 | update = false; | |
418 | } else { | |
419 | section = phys_page_find(d, addr); | |
420 | update = true; | |
421 | } | |
422 | if (resolve_subpage && section->mr->subpage) { | |
423 | subpage = container_of(section->mr, subpage_t, iomem); | |
424 | section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]]; | |
425 | } | |
426 | if (update) { | |
427 | atomic_set(&d->mru_section, section); | |
428 | } | |
429 | return section; | |
430 | } | |
431 | ||
432 | /* Called from RCU critical section */ | |
433 | static MemoryRegionSection * | |
434 | address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat, | |
435 | hwaddr *plen, bool resolve_subpage) | |
436 | { | |
437 | MemoryRegionSection *section; | |
438 | MemoryRegion *mr; | |
439 | Int128 diff; | |
440 | ||
441 | section = address_space_lookup_region(d, addr, resolve_subpage); | |
442 | /* Compute offset within MemoryRegionSection */ | |
443 | addr -= section->offset_within_address_space; | |
444 | ||
445 | /* Compute offset within MemoryRegion */ | |
446 | *xlat = addr + section->offset_within_region; | |
447 | ||
448 | mr = section->mr; | |
449 | ||
450 | /* MMIO registers can be expected to perform full-width accesses based only | |
451 | * on their address, without considering adjacent registers that could | |
452 | * decode to completely different MemoryRegions. When such registers | |
453 | * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO | |
454 | * regions overlap wildly. For this reason we cannot clamp the accesses | |
455 | * here. | |
456 | * | |
457 | * If the length is small (as is the case for address_space_ldl/stl), | |
458 | * everything works fine. If the incoming length is large, however, | |
459 | * the caller really has to do the clamping through memory_access_size. | |
460 | */ | |
461 | if (memory_region_is_ram(mr)) { | |
462 | diff = int128_sub(section->size, int128_make64(addr)); | |
463 | *plen = int128_get64(int128_min(diff, int128_make64(*plen))); | |
464 | } | |
465 | return section; | |
466 | } | |
467 | ||
468 | /** | |
469 | * flatview_do_translate - translate an address in FlatView | |
470 | * | |
471 | * @fv: the flat view that we want to translate on | |
472 | * @addr: the address to be translated in above address space | |
473 | * @xlat: the translated address offset within memory region. It | |
474 | * cannot be @NULL. | |
475 | * @plen_out: valid read/write length of the translated address. It | |
476 | * can be @NULL when we don't care about it. | |
477 | * @page_mask_out: page mask for the translated address. This | |
478 | * should only be meaningful for IOMMU translated | |
479 | * addresses, since there may be huge pages that this bit | |
480 | * would tell. It can be @NULL if we don't care about it. | |
481 | * @is_write: whether the translation operation is for write | |
482 | * @is_mmio: whether this can be MMIO, set true if it can | |
483 | * | |
484 | * This function is called from RCU critical section | |
485 | */ | |
486 | static MemoryRegionSection flatview_do_translate(FlatView *fv, | |
487 | hwaddr addr, | |
488 | hwaddr *xlat, | |
489 | hwaddr *plen_out, | |
490 | hwaddr *page_mask_out, | |
491 | bool is_write, | |
492 | bool is_mmio, | |
493 | AddressSpace **target_as) | |
494 | { | |
495 | IOMMUTLBEntry iotlb; | |
496 | MemoryRegionSection *section; | |
497 | IOMMUMemoryRegion *iommu_mr; | |
498 | IOMMUMemoryRegionClass *imrc; | |
499 | hwaddr page_mask = (hwaddr)(-1); | |
500 | hwaddr plen = (hwaddr)(-1); | |
501 | ||
502 | if (plen_out) { | |
503 | plen = *plen_out; | |
504 | } | |
505 | ||
506 | for (;;) { | |
507 | section = address_space_translate_internal( | |
508 | flatview_to_dispatch(fv), addr, &addr, | |
509 | &plen, is_mmio); | |
510 | ||
511 | iommu_mr = memory_region_get_iommu(section->mr); | |
512 | if (!iommu_mr) { | |
513 | break; | |
514 | } | |
515 | imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | |
516 | ||
517 | iotlb = imrc->translate(iommu_mr, addr, is_write ? | |
518 | IOMMU_WO : IOMMU_RO); | |
519 | addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | |
520 | | (addr & iotlb.addr_mask)); | |
521 | page_mask &= iotlb.addr_mask; | |
522 | plen = MIN(plen, (addr | iotlb.addr_mask) - addr + 1); | |
523 | if (!(iotlb.perm & (1 << is_write))) { | |
524 | goto translate_fail; | |
525 | } | |
526 | ||
527 | fv = address_space_to_flatview(iotlb.target_as); | |
528 | *target_as = iotlb.target_as; | |
529 | } | |
530 | ||
531 | *xlat = addr; | |
532 | ||
533 | if (page_mask == (hwaddr)(-1)) { | |
534 | /* Not behind an IOMMU, use default page size. */ | |
535 | page_mask = ~TARGET_PAGE_MASK; | |
536 | } | |
537 | ||
538 | if (page_mask_out) { | |
539 | *page_mask_out = page_mask; | |
540 | } | |
541 | ||
542 | if (plen_out) { | |
543 | *plen_out = plen; | |
544 | } | |
545 | ||
546 | return *section; | |
547 | ||
548 | translate_fail: | |
549 | return (MemoryRegionSection) { .mr = &io_mem_unassigned }; | |
550 | } | |
551 | ||
552 | /* Called from RCU critical section */ | |
553 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | |
554 | bool is_write) | |
555 | { | |
556 | MemoryRegionSection section; | |
557 | hwaddr xlat, page_mask; | |
558 | ||
559 | /* | |
560 | * This can never be MMIO, and we don't really care about plen, | |
561 | * but page mask. | |
562 | */ | |
563 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | |
564 | NULL, &page_mask, is_write, false, &as); | |
565 | ||
566 | /* Illegal translation */ | |
567 | if (section.mr == &io_mem_unassigned) { | |
568 | goto iotlb_fail; | |
569 | } | |
570 | ||
571 | /* Convert memory region offset into address space offset */ | |
572 | xlat += section.offset_within_address_space - | |
573 | section.offset_within_region; | |
574 | ||
575 | return (IOMMUTLBEntry) { | |
576 | .target_as = as, | |
577 | .iova = addr & ~page_mask, | |
578 | .translated_addr = xlat & ~page_mask, | |
579 | .addr_mask = page_mask, | |
580 | /* IOTLBs are for DMAs, and DMA only allows on RAMs. */ | |
581 | .perm = IOMMU_RW, | |
582 | }; | |
583 | ||
584 | iotlb_fail: | |
585 | return (IOMMUTLBEntry) {0}; | |
586 | } | |
587 | ||
588 | /* Called from RCU critical section */ | |
589 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, | |
590 | hwaddr *plen, bool is_write) | |
591 | { | |
592 | MemoryRegion *mr; | |
593 | MemoryRegionSection section; | |
594 | AddressSpace *as = NULL; | |
595 | ||
596 | /* This can be MMIO, so setup MMIO bit. */ | |
597 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, | |
598 | is_write, true, &as); | |
599 | mr = section.mr; | |
600 | ||
601 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { | |
602 | hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr; | |
603 | *plen = MIN(page, *plen); | |
604 | } | |
605 | ||
606 | return mr; | |
607 | } | |
608 | ||
609 | /* Called from RCU critical section */ | |
610 | MemoryRegionSection * | |
611 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, | |
612 | hwaddr *xlat, hwaddr *plen) | |
613 | { | |
614 | MemoryRegionSection *section; | |
615 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); | |
616 | ||
617 | section = address_space_translate_internal(d, addr, xlat, plen, false); | |
618 | ||
619 | assert(!memory_region_is_iommu(section->mr)); | |
620 | return section; | |
621 | } | |
622 | #endif | |
623 | ||
624 | #if !defined(CONFIG_USER_ONLY) | |
625 | ||
626 | static int cpu_common_post_load(void *opaque, int version_id) | |
627 | { | |
628 | CPUState *cpu = opaque; | |
629 | ||
630 | /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the | |
631 | version_id is increased. */ | |
632 | cpu->interrupt_request &= ~0x01; | |
633 | tlb_flush(cpu); | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | static int cpu_common_pre_load(void *opaque) | |
639 | { | |
640 | CPUState *cpu = opaque; | |
641 | ||
642 | cpu->exception_index = -1; | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
647 | static bool cpu_common_exception_index_needed(void *opaque) | |
648 | { | |
649 | CPUState *cpu = opaque; | |
650 | ||
651 | return tcg_enabled() && cpu->exception_index != -1; | |
652 | } | |
653 | ||
654 | static const VMStateDescription vmstate_cpu_common_exception_index = { | |
655 | .name = "cpu_common/exception_index", | |
656 | .version_id = 1, | |
657 | .minimum_version_id = 1, | |
658 | .needed = cpu_common_exception_index_needed, | |
659 | .fields = (VMStateField[]) { | |
660 | VMSTATE_INT32(exception_index, CPUState), | |
661 | VMSTATE_END_OF_LIST() | |
662 | } | |
663 | }; | |
664 | ||
665 | static bool cpu_common_crash_occurred_needed(void *opaque) | |
666 | { | |
667 | CPUState *cpu = opaque; | |
668 | ||
669 | return cpu->crash_occurred; | |
670 | } | |
671 | ||
672 | static const VMStateDescription vmstate_cpu_common_crash_occurred = { | |
673 | .name = "cpu_common/crash_occurred", | |
674 | .version_id = 1, | |
675 | .minimum_version_id = 1, | |
676 | .needed = cpu_common_crash_occurred_needed, | |
677 | .fields = (VMStateField[]) { | |
678 | VMSTATE_BOOL(crash_occurred, CPUState), | |
679 | VMSTATE_END_OF_LIST() | |
680 | } | |
681 | }; | |
682 | ||
683 | const VMStateDescription vmstate_cpu_common = { | |
684 | .name = "cpu_common", | |
685 | .version_id = 1, | |
686 | .minimum_version_id = 1, | |
687 | .pre_load = cpu_common_pre_load, | |
688 | .post_load = cpu_common_post_load, | |
689 | .fields = (VMStateField[]) { | |
690 | VMSTATE_UINT32(halted, CPUState), | |
691 | VMSTATE_UINT32(interrupt_request, CPUState), | |
692 | VMSTATE_END_OF_LIST() | |
693 | }, | |
694 | .subsections = (const VMStateDescription*[]) { | |
695 | &vmstate_cpu_common_exception_index, | |
696 | &vmstate_cpu_common_crash_occurred, | |
697 | NULL | |
698 | } | |
699 | }; | |
700 | ||
701 | #endif | |
702 | ||
703 | CPUState *qemu_get_cpu(int index) | |
704 | { | |
705 | CPUState *cpu; | |
706 | ||
707 | CPU_FOREACH(cpu) { | |
708 | if (cpu->cpu_index == index) { | |
709 | return cpu; | |
710 | } | |
711 | } | |
712 | ||
713 | return NULL; | |
714 | } | |
715 | ||
716 | #if !defined(CONFIG_USER_ONLY) | |
717 | void cpu_address_space_init(CPUState *cpu, AddressSpace *as, int asidx) | |
718 | { | |
719 | CPUAddressSpace *newas; | |
720 | ||
721 | /* Target code should have set num_ases before calling us */ | |
722 | assert(asidx < cpu->num_ases); | |
723 | ||
724 | if (asidx == 0) { | |
725 | /* address space 0 gets the convenience alias */ | |
726 | cpu->as = as; | |
727 | } | |
728 | ||
729 | /* KVM cannot currently support multiple address spaces. */ | |
730 | assert(asidx == 0 || !kvm_enabled()); | |
731 | ||
732 | if (!cpu->cpu_ases) { | |
733 | cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases); | |
734 | } | |
735 | ||
736 | newas = &cpu->cpu_ases[asidx]; | |
737 | newas->cpu = cpu; | |
738 | newas->as = as; | |
739 | if (tcg_enabled()) { | |
740 | newas->tcg_as_listener.commit = tcg_commit; | |
741 | memory_listener_register(&newas->tcg_as_listener, as); | |
742 | } | |
743 | } | |
744 | ||
745 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx) | |
746 | { | |
747 | /* Return the AddressSpace corresponding to the specified index */ | |
748 | return cpu->cpu_ases[asidx].as; | |
749 | } | |
750 | #endif | |
751 | ||
752 | void cpu_exec_unrealizefn(CPUState *cpu) | |
753 | { | |
754 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
755 | ||
756 | cpu_list_remove(cpu); | |
757 | ||
758 | if (cc->vmsd != NULL) { | |
759 | vmstate_unregister(NULL, cc->vmsd, cpu); | |
760 | } | |
761 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
762 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | |
763 | } | |
764 | } | |
765 | ||
766 | Property cpu_common_props[] = { | |
767 | #ifndef CONFIG_USER_ONLY | |
768 | /* Create a memory property for softmmu CPU object, | |
769 | * so users can wire up its memory. (This can't go in qom/cpu.c | |
770 | * because that file is compiled only once for both user-mode | |
771 | * and system builds.) The default if no link is set up is to use | |
772 | * the system address space. | |
773 | */ | |
774 | DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | |
775 | MemoryRegion *), | |
776 | #endif | |
777 | DEFINE_PROP_END_OF_LIST(), | |
778 | }; | |
779 | ||
780 | void cpu_exec_initfn(CPUState *cpu) | |
781 | { | |
782 | cpu->as = NULL; | |
783 | cpu->num_ases = 0; | |
784 | ||
785 | #ifndef CONFIG_USER_ONLY | |
786 | cpu->thread_id = qemu_get_thread_id(); | |
787 | cpu->memory = system_memory; | |
788 | object_ref(OBJECT(cpu->memory)); | |
789 | #endif | |
790 | } | |
791 | ||
792 | void cpu_exec_realizefn(CPUState *cpu, Error **errp) | |
793 | { | |
794 | CPUClass *cc ATTRIBUTE_UNUSED = CPU_GET_CLASS(cpu); | |
795 | ||
796 | cpu_list_add(cpu); | |
797 | ||
798 | #ifndef CONFIG_USER_ONLY | |
799 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | |
800 | vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); | |
801 | } | |
802 | if (cc->vmsd != NULL) { | |
803 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); | |
804 | } | |
805 | #endif | |
806 | } | |
807 | ||
808 | #if defined(CONFIG_USER_ONLY) | |
809 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
810 | { | |
811 | mmap_lock(); | |
812 | tb_lock(); | |
813 | tb_invalidate_phys_page_range(pc, pc + 1, 0); | |
814 | tb_unlock(); | |
815 | mmap_unlock(); | |
816 | } | |
817 | #else | |
818 | static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | |
819 | { | |
820 | MemTxAttrs attrs; | |
821 | hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs); | |
822 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
823 | if (phys != -1) { | |
824 | /* Locks grabbed by tb_invalidate_phys_addr */ | |
825 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | |
826 | phys | (pc & ~TARGET_PAGE_MASK)); | |
827 | } | |
828 | } | |
829 | #endif | |
830 | ||
831 | #if defined(CONFIG_USER_ONLY) | |
832 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
833 | ||
834 | { | |
835 | } | |
836 | ||
837 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, | |
838 | int flags) | |
839 | { | |
840 | return -ENOSYS; | |
841 | } | |
842 | ||
843 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
844 | { | |
845 | } | |
846 | ||
847 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
848 | int flags, CPUWatchpoint **watchpoint) | |
849 | { | |
850 | return -ENOSYS; | |
851 | } | |
852 | #else | |
853 | /* Add a watchpoint. */ | |
854 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, | |
855 | int flags, CPUWatchpoint **watchpoint) | |
856 | { | |
857 | CPUWatchpoint *wp; | |
858 | ||
859 | /* forbid ranges which are empty or run off the end of the address space */ | |
860 | if (len == 0 || (addr + len - 1) < addr) { | |
861 | error_report("tried to set invalid watchpoint at %" | |
862 | VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); | |
863 | return -EINVAL; | |
864 | } | |
865 | wp = g_malloc(sizeof(*wp)); | |
866 | ||
867 | wp->vaddr = addr; | |
868 | wp->len = len; | |
869 | wp->flags = flags; | |
870 | ||
871 | /* keep all GDB-injected watchpoints in front */ | |
872 | if (flags & BP_GDB) { | |
873 | QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); | |
874 | } else { | |
875 | QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); | |
876 | } | |
877 | ||
878 | tlb_flush_page(cpu, addr); | |
879 | ||
880 | if (watchpoint) | |
881 | *watchpoint = wp; | |
882 | return 0; | |
883 | } | |
884 | ||
885 | /* Remove a specific watchpoint. */ | |
886 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, | |
887 | int flags) | |
888 | { | |
889 | CPUWatchpoint *wp; | |
890 | ||
891 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
892 | if (addr == wp->vaddr && len == wp->len | |
893 | && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { | |
894 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
895 | return 0; | |
896 | } | |
897 | } | |
898 | return -ENOENT; | |
899 | } | |
900 | ||
901 | /* Remove a specific watchpoint by reference. */ | |
902 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) | |
903 | { | |
904 | QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); | |
905 | ||
906 | tlb_flush_page(cpu, watchpoint->vaddr); | |
907 | ||
908 | g_free(watchpoint); | |
909 | } | |
910 | ||
911 | /* Remove all matching watchpoints. */ | |
912 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask) | |
913 | { | |
914 | CPUWatchpoint *wp, *next; | |
915 | ||
916 | QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { | |
917 | if (wp->flags & mask) { | |
918 | cpu_watchpoint_remove_by_ref(cpu, wp); | |
919 | } | |
920 | } | |
921 | } | |
922 | ||
923 | /* Return true if this watchpoint address matches the specified | |
924 | * access (ie the address range covered by the watchpoint overlaps | |
925 | * partially or completely with the address range covered by the | |
926 | * access). | |
927 | */ | |
928 | static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, | |
929 | vaddr addr, | |
930 | vaddr len) | |
931 | { | |
932 | /* We know the lengths are non-zero, but a little caution is | |
933 | * required to avoid errors in the case where the range ends | |
934 | * exactly at the top of the address space and so addr + len | |
935 | * wraps round to zero. | |
936 | */ | |
937 | vaddr wpend = wp->vaddr + wp->len - 1; | |
938 | vaddr addrend = addr + len - 1; | |
939 | ||
940 | return !(addr > wpend || wp->vaddr > addrend); | |
941 | } | |
942 | ||
943 | #endif | |
944 | ||
945 | /* Add a breakpoint. */ | |
946 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
947 | CPUBreakpoint **breakpoint) | |
948 | { | |
949 | CPUBreakpoint *bp; | |
950 | ||
951 | bp = g_malloc(sizeof(*bp)); | |
952 | ||
953 | bp->pc = pc; | |
954 | bp->flags = flags; | |
955 | ||
956 | /* keep all GDB-injected breakpoints in front */ | |
957 | if (flags & BP_GDB) { | |
958 | QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); | |
959 | } else { | |
960 | QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); | |
961 | } | |
962 | ||
963 | breakpoint_invalidate(cpu, pc); | |
964 | ||
965 | if (breakpoint) { | |
966 | *breakpoint = bp; | |
967 | } | |
968 | return 0; | |
969 | } | |
970 | ||
971 | /* Remove a specific breakpoint. */ | |
972 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) | |
973 | { | |
974 | CPUBreakpoint *bp; | |
975 | ||
976 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
977 | if (bp->pc == pc && bp->flags == flags) { | |
978 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
979 | return 0; | |
980 | } | |
981 | } | |
982 | return -ENOENT; | |
983 | } | |
984 | ||
985 | /* Remove a specific breakpoint by reference. */ | |
986 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) | |
987 | { | |
988 | QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); | |
989 | ||
990 | breakpoint_invalidate(cpu, breakpoint->pc); | |
991 | ||
992 | g_free(breakpoint); | |
993 | } | |
994 | ||
995 | /* Remove all matching breakpoints. */ | |
996 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask) | |
997 | { | |
998 | CPUBreakpoint *bp, *next; | |
999 | ||
1000 | QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { | |
1001 | if (bp->flags & mask) { | |
1002 | cpu_breakpoint_remove_by_ref(cpu, bp); | |
1003 | } | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | /* enable or disable single step mode. EXCP_DEBUG is returned by the | |
1008 | CPU loop after each instruction */ | |
1009 | void cpu_single_step(CPUState *cpu, int enabled) | |
1010 | { | |
1011 | if (cpu->singlestep_enabled != enabled) { | |
1012 | cpu->singlestep_enabled = enabled; | |
1013 | if (kvm_enabled()) { | |
1014 | kvm_update_guest_debug(cpu, 0); | |
1015 | } else { | |
1016 | /* must flush all the translated code to avoid inconsistencies */ | |
1017 | /* XXX: only flush what is necessary */ | |
1018 | tb_flush(cpu); | |
1019 | } | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | void cpu_abort(CPUState *cpu, const char *fmt, ...) | |
1024 | { | |
1025 | va_list ap; | |
1026 | va_list ap2; | |
1027 | ||
1028 | va_start(ap, fmt); | |
1029 | va_copy(ap2, ap); | |
1030 | fprintf(stderr, "qemu: fatal: "); | |
1031 | vfprintf(stderr, fmt, ap); | |
1032 | fprintf(stderr, "\n"); | |
1033 | cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP); | |
1034 | if (qemu_log_separate()) { | |
1035 | qemu_log_lock(); | |
1036 | qemu_log("qemu: fatal: "); | |
1037 | qemu_log_vprintf(fmt, ap2); | |
1038 | qemu_log("\n"); | |
1039 | log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); | |
1040 | qemu_log_flush(); | |
1041 | qemu_log_unlock(); | |
1042 | qemu_log_close(); | |
1043 | } | |
1044 | va_end(ap2); | |
1045 | va_end(ap); | |
1046 | replay_finish(); | |
1047 | #if defined(CONFIG_USER_ONLY) | |
1048 | { | |
1049 | struct sigaction act; | |
1050 | sigfillset(&act.sa_mask); | |
1051 | act.sa_handler = SIG_DFL; | |
1052 | sigaction(SIGABRT, &act, NULL); | |
1053 | } | |
1054 | #endif | |
1055 | abort(); | |
1056 | } | |
1057 | ||
1058 | #if !defined(CONFIG_USER_ONLY) | |
1059 | /* Called from RCU critical section */ | |
1060 | static RAMBlock *qemu_get_ram_block(ram_addr_t addr) | |
1061 | { | |
1062 | RAMBlock *block; | |
1063 | ||
1064 | block = atomic_rcu_read(&ram_list.mru_block); | |
1065 | if (block && addr - block->offset < block->max_length) { | |
1066 | return block; | |
1067 | } | |
1068 | RAMBLOCK_FOREACH(block) { | |
1069 | if (addr - block->offset < block->max_length) { | |
1070 | goto found; | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr); | |
1075 | abort(); | |
1076 | ||
1077 | found: | |
1078 | /* It is safe to write mru_block outside the iothread lock. This | |
1079 | * is what happens: | |
1080 | * | |
1081 | * mru_block = xxx | |
1082 | * rcu_read_unlock() | |
1083 | * xxx removed from list | |
1084 | * rcu_read_lock() | |
1085 | * read mru_block | |
1086 | * mru_block = NULL; | |
1087 | * call_rcu(reclaim_ramblock, xxx); | |
1088 | * rcu_read_unlock() | |
1089 | * | |
1090 | * atomic_rcu_set is not needed here. The block was already published | |
1091 | * when it was placed into the list. Here we're just making an extra | |
1092 | * copy of the pointer. | |
1093 | */ | |
1094 | ram_list.mru_block = block; | |
1095 | return block; | |
1096 | } | |
1097 | ||
1098 | static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length) | |
1099 | { | |
1100 | CPUState *cpu; | |
1101 | ram_addr_t start1; | |
1102 | RAMBlock *block; | |
1103 | ram_addr_t end; | |
1104 | ||
1105 | end = TARGET_PAGE_ALIGN(start + length); | |
1106 | start &= TARGET_PAGE_MASK; | |
1107 | ||
1108 | rcu_read_lock(); | |
1109 | block = qemu_get_ram_block(start); | |
1110 | assert(block == qemu_get_ram_block(end - 1)); | |
1111 | start1 = (uintptr_t)ramblock_ptr(block, start - block->offset); | |
1112 | CPU_FOREACH(cpu) { | |
1113 | tlb_reset_dirty(cpu, start1, length); | |
1114 | } | |
1115 | rcu_read_unlock(); | |
1116 | } | |
1117 | ||
1118 | /* Note: start and end must be within the same ram block. */ | |
1119 | bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, | |
1120 | ram_addr_t length, | |
1121 | unsigned client) | |
1122 | { | |
1123 | DirtyMemoryBlocks *blocks; | |
1124 | unsigned long end, page; | |
1125 | bool dirty = false; | |
1126 | ||
1127 | if (length == 0) { | |
1128 | return false; | |
1129 | } | |
1130 | ||
1131 | end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; | |
1132 | page = start >> TARGET_PAGE_BITS; | |
1133 | ||
1134 | rcu_read_lock(); | |
1135 | ||
1136 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1137 | ||
1138 | while (page < end) { | |
1139 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1140 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1141 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1142 | ||
1143 | dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx], | |
1144 | offset, num); | |
1145 | page += num; | |
1146 | } | |
1147 | ||
1148 | rcu_read_unlock(); | |
1149 | ||
1150 | if (dirty && tcg_enabled()) { | |
1151 | tlb_reset_dirty_range_all(start, length); | |
1152 | } | |
1153 | ||
1154 | return dirty; | |
1155 | } | |
1156 | ||
1157 | DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty | |
1158 | (ram_addr_t start, ram_addr_t length, unsigned client) | |
1159 | { | |
1160 | DirtyMemoryBlocks *blocks; | |
1161 | unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL); | |
1162 | ram_addr_t first = QEMU_ALIGN_DOWN(start, align); | |
1163 | ram_addr_t last = QEMU_ALIGN_UP(start + length, align); | |
1164 | DirtyBitmapSnapshot *snap; | |
1165 | unsigned long page, end, dest; | |
1166 | ||
1167 | snap = g_malloc0(sizeof(*snap) + | |
1168 | ((last - first) >> (TARGET_PAGE_BITS + 3))); | |
1169 | snap->start = first; | |
1170 | snap->end = last; | |
1171 | ||
1172 | page = first >> TARGET_PAGE_BITS; | |
1173 | end = last >> TARGET_PAGE_BITS; | |
1174 | dest = 0; | |
1175 | ||
1176 | rcu_read_lock(); | |
1177 | ||
1178 | blocks = atomic_rcu_read(&ram_list.dirty_memory[client]); | |
1179 | ||
1180 | while (page < end) { | |
1181 | unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE; | |
1182 | unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE; | |
1183 | unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset); | |
1184 | ||
1185 | assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL))); | |
1186 | assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL))); | |
1187 | offset >>= BITS_PER_LEVEL; | |
1188 | ||
1189 | bitmap_copy_and_clear_atomic(snap->dirty + dest, | |
1190 | blocks->blocks[idx] + offset, | |
1191 | num); | |
1192 | page += num; | |
1193 | dest += num >> BITS_PER_LEVEL; | |
1194 | } | |
1195 | ||
1196 | rcu_read_unlock(); | |
1197 | ||
1198 | if (tcg_enabled()) { | |
1199 | tlb_reset_dirty_range_all(start, length); | |
1200 | } | |
1201 | ||
1202 | return snap; | |
1203 | } | |
1204 | ||
1205 | bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, | |
1206 | ram_addr_t start, | |
1207 | ram_addr_t length) | |
1208 | { | |
1209 | unsigned long page, end; | |
1210 | ||
1211 | assert(start >= snap->start); | |
1212 | assert(start + length <= snap->end); | |
1213 | ||
1214 | end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS; | |
1215 | page = (start - snap->start) >> TARGET_PAGE_BITS; | |
1216 | ||
1217 | while (page < end) { | |
1218 | if (test_bit(page, snap->dirty)) { | |
1219 | return true; | |
1220 | } | |
1221 | page++; | |
1222 | } | |
1223 | return false; | |
1224 | } | |
1225 | ||
1226 | /* Called from RCU critical section */ | |
1227 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, | |
1228 | MemoryRegionSection *section, | |
1229 | target_ulong vaddr, | |
1230 | hwaddr paddr, hwaddr xlat, | |
1231 | int prot, | |
1232 | target_ulong *address) | |
1233 | { | |
1234 | hwaddr iotlb; | |
1235 | CPUWatchpoint *wp; | |
1236 | ||
1237 | if (memory_region_is_ram(section->mr)) { | |
1238 | /* Normal RAM. */ | |
1239 | iotlb = memory_region_get_ram_addr(section->mr) + xlat; | |
1240 | if (!section->readonly) { | |
1241 | iotlb |= PHYS_SECTION_NOTDIRTY; | |
1242 | } else { | |
1243 | iotlb |= PHYS_SECTION_ROM; | |
1244 | } | |
1245 | } else { | |
1246 | AddressSpaceDispatch *d; | |
1247 | ||
1248 | d = flatview_to_dispatch(section->fv); | |
1249 | iotlb = section - d->map.sections; | |
1250 | iotlb += xlat; | |
1251 | } | |
1252 | ||
1253 | /* Make accesses to pages with watchpoints go via the | |
1254 | watchpoint trap routines. */ | |
1255 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
1256 | if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) { | |
1257 | /* Avoid trapping reads of pages with a write breakpoint. */ | |
1258 | if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { | |
1259 | iotlb = PHYS_SECTION_WATCH + paddr; | |
1260 | *address |= TLB_MMIO; | |
1261 | break; | |
1262 | } | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | return iotlb; | |
1267 | } | |
1268 | #endif /* defined(CONFIG_USER_ONLY) */ | |
1269 | ||
1270 | #if !defined(CONFIG_USER_ONLY) | |
1271 | ||
1272 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
1273 | uint16_t section); | |
1274 | static subpage_t *subpage_init(FlatView *fv, hwaddr base); | |
1275 | ||
1276 | static void *(*phys_mem_alloc)(size_t size, uint64_t *align) = | |
1277 | qemu_anon_ram_alloc; | |
1278 | ||
1279 | /* | |
1280 | * Set a custom physical guest memory alloator. | |
1281 | * Accelerators with unusual needs may need this. Hopefully, we can | |
1282 | * get rid of it eventually. | |
1283 | */ | |
1284 | void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)) | |
1285 | { | |
1286 | phys_mem_alloc = alloc; | |
1287 | } | |
1288 | ||
1289 | static uint16_t phys_section_add(PhysPageMap *map, | |
1290 | MemoryRegionSection *section) | |
1291 | { | |
1292 | /* The physical section number is ORed with a page-aligned | |
1293 | * pointer to produce the iotlb entries. Thus it should | |
1294 | * never overflow into the page-aligned value. | |
1295 | */ | |
1296 | assert(map->sections_nb < TARGET_PAGE_SIZE); | |
1297 | ||
1298 | if (map->sections_nb == map->sections_nb_alloc) { | |
1299 | map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16); | |
1300 | map->sections = g_renew(MemoryRegionSection, map->sections, | |
1301 | map->sections_nb_alloc); | |
1302 | } | |
1303 | map->sections[map->sections_nb] = *section; | |
1304 | memory_region_ref(section->mr); | |
1305 | return map->sections_nb++; | |
1306 | } | |
1307 | ||
1308 | static void phys_section_destroy(MemoryRegion *mr) | |
1309 | { | |
1310 | bool have_sub_page = mr->subpage; | |
1311 | ||
1312 | memory_region_unref(mr); | |
1313 | ||
1314 | if (have_sub_page) { | |
1315 | subpage_t *subpage = container_of(mr, subpage_t, iomem); | |
1316 | object_unref(OBJECT(&subpage->iomem)); | |
1317 | g_free(subpage); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | static void phys_sections_free(PhysPageMap *map) | |
1322 | { | |
1323 | while (map->sections_nb > 0) { | |
1324 | MemoryRegionSection *section = &map->sections[--map->sections_nb]; | |
1325 | phys_section_destroy(section->mr); | |
1326 | } | |
1327 | g_free(map->sections); | |
1328 | g_free(map->nodes); | |
1329 | } | |
1330 | ||
1331 | static void register_subpage(FlatView *fv, MemoryRegionSection *section) | |
1332 | { | |
1333 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); | |
1334 | subpage_t *subpage; | |
1335 | hwaddr base = section->offset_within_address_space | |
1336 | & TARGET_PAGE_MASK; | |
1337 | MemoryRegionSection *existing = phys_page_find(d, base); | |
1338 | MemoryRegionSection subsection = { | |
1339 | .offset_within_address_space = base, | |
1340 | .size = int128_make64(TARGET_PAGE_SIZE), | |
1341 | }; | |
1342 | hwaddr start, end; | |
1343 | ||
1344 | assert(existing->mr->subpage || existing->mr == &io_mem_unassigned); | |
1345 | ||
1346 | if (!(existing->mr->subpage)) { | |
1347 | subpage = subpage_init(fv, base); | |
1348 | subsection.fv = fv; | |
1349 | subsection.mr = &subpage->iomem; | |
1350 | phys_page_set(d, base >> TARGET_PAGE_BITS, 1, | |
1351 | phys_section_add(&d->map, &subsection)); | |
1352 | } else { | |
1353 | subpage = container_of(existing->mr, subpage_t, iomem); | |
1354 | } | |
1355 | start = section->offset_within_address_space & ~TARGET_PAGE_MASK; | |
1356 | end = start + int128_get64(section->size) - 1; | |
1357 | subpage_register(subpage, start, end, | |
1358 | phys_section_add(&d->map, section)); | |
1359 | } | |
1360 | ||
1361 | ||
1362 | static void register_multipage(FlatView *fv, | |
1363 | MemoryRegionSection *section) | |
1364 | { | |
1365 | AddressSpaceDispatch *d = flatview_to_dispatch(fv); | |
1366 | hwaddr start_addr = section->offset_within_address_space; | |
1367 | uint16_t section_index = phys_section_add(&d->map, section); | |
1368 | uint64_t num_pages = int128_get64(int128_rshift(section->size, | |
1369 | TARGET_PAGE_BITS)); | |
1370 | ||
1371 | assert(num_pages); | |
1372 | phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index); | |
1373 | } | |
1374 | ||
1375 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section) | |
1376 | { | |
1377 | MemoryRegionSection now = *section, remain = *section; | |
1378 | Int128 page_size = int128_make64(TARGET_PAGE_SIZE); | |
1379 | ||
1380 | if (now.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1381 | uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space) | |
1382 | - now.offset_within_address_space; | |
1383 | ||
1384 | now.size = int128_min(int128_make64(left), now.size); | |
1385 | register_subpage(fv, &now); | |
1386 | } else { | |
1387 | now.size = int128_zero(); | |
1388 | } | |
1389 | while (int128_ne(remain.size, now.size)) { | |
1390 | remain.size = int128_sub(remain.size, now.size); | |
1391 | remain.offset_within_address_space += int128_get64(now.size); | |
1392 | remain.offset_within_region += int128_get64(now.size); | |
1393 | now = remain; | |
1394 | if (int128_lt(remain.size, page_size)) { | |
1395 | register_subpage(fv, &now); | |
1396 | } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) { | |
1397 | now.size = page_size; | |
1398 | register_subpage(fv, &now); | |
1399 | } else { | |
1400 | now.size = int128_and(now.size, int128_neg(page_size)); | |
1401 | register_multipage(fv, &now); | |
1402 | } | |
1403 | } | |
1404 | } | |
1405 | ||
1406 | void qemu_flush_coalesced_mmio_buffer(void) | |
1407 | { | |
1408 | if (kvm_enabled()) | |
1409 | kvm_flush_coalesced_mmio_buffer(); | |
1410 | } | |
1411 | ||
1412 | void qemu_mutex_lock_ramlist(void) | |
1413 | { | |
1414 | qemu_mutex_lock(&ram_list.mutex); | |
1415 | } | |
1416 | ||
1417 | void qemu_mutex_unlock_ramlist(void) | |
1418 | { | |
1419 | qemu_mutex_unlock(&ram_list.mutex); | |
1420 | } | |
1421 | ||
1422 | void ram_block_dump(Monitor *mon) | |
1423 | { | |
1424 | RAMBlock *block; | |
1425 | char *psize; | |
1426 | ||
1427 | rcu_read_lock(); | |
1428 | monitor_printf(mon, "%24s %8s %18s %18s %18s\n", | |
1429 | "Block Name", "PSize", "Offset", "Used", "Total"); | |
1430 | RAMBLOCK_FOREACH(block) { | |
1431 | psize = size_to_str(block->page_size); | |
1432 | monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64 | |
1433 | " 0x%016" PRIx64 "\n", block->idstr, psize, | |
1434 | (uint64_t)block->offset, | |
1435 | (uint64_t)block->used_length, | |
1436 | (uint64_t)block->max_length); | |
1437 | g_free(psize); | |
1438 | } | |
1439 | rcu_read_unlock(); | |
1440 | } | |
1441 | ||
1442 | #ifdef __linux__ | |
1443 | /* | |
1444 | * FIXME TOCTTOU: this iterates over memory backends' mem-path, which | |
1445 | * may or may not name the same files / on the same filesystem now as | |
1446 | * when we actually open and map them. Iterate over the file | |
1447 | * descriptors instead, and use qemu_fd_getpagesize(). | |
1448 | */ | |
1449 | static int find_max_supported_pagesize(Object *obj, void *opaque) | |
1450 | { | |
1451 | char *mem_path; | |
1452 | long *hpsize_min = opaque; | |
1453 | ||
1454 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
1455 | mem_path = object_property_get_str(obj, "mem-path", NULL); | |
1456 | if (mem_path) { | |
1457 | long hpsize = qemu_mempath_getpagesize(mem_path); | |
1458 | if (hpsize < *hpsize_min) { | |
1459 | *hpsize_min = hpsize; | |
1460 | } | |
1461 | } else { | |
1462 | *hpsize_min = getpagesize(); | |
1463 | } | |
1464 | } | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | long qemu_getrampagesize(void) | |
1470 | { | |
1471 | long hpsize = LONG_MAX; | |
1472 | long mainrampagesize; | |
1473 | Object *memdev_root; | |
1474 | ||
1475 | if (mem_path) { | |
1476 | mainrampagesize = qemu_mempath_getpagesize(mem_path); | |
1477 | } else { | |
1478 | mainrampagesize = getpagesize(); | |
1479 | } | |
1480 | ||
1481 | /* it's possible we have memory-backend objects with | |
1482 | * hugepage-backed RAM. these may get mapped into system | |
1483 | * address space via -numa parameters or memory hotplug | |
1484 | * hooks. we want to take these into account, but we | |
1485 | * also want to make sure these supported hugepage | |
1486 | * sizes are applicable across the entire range of memory | |
1487 | * we may boot from, so we take the min across all | |
1488 | * backends, and assume normal pages in cases where a | |
1489 | * backend isn't backed by hugepages. | |
1490 | */ | |
1491 | memdev_root = object_resolve_path("/objects", NULL); | |
1492 | if (memdev_root) { | |
1493 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
1494 | } | |
1495 | if (hpsize == LONG_MAX) { | |
1496 | /* No additional memory regions found ==> Report main RAM page size */ | |
1497 | return mainrampagesize; | |
1498 | } | |
1499 | ||
1500 | /* If NUMA is disabled or the NUMA nodes are not backed with a | |
1501 | * memory-backend, then there is at least one node using "normal" RAM, | |
1502 | * so if its page size is smaller we have got to report that size instead. | |
1503 | */ | |
1504 | if (hpsize > mainrampagesize && | |
1505 | (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) { | |
1506 | static bool warned; | |
1507 | if (!warned) { | |
1508 | error_report("Huge page support disabled (n/a for main memory)."); | |
1509 | warned = true; | |
1510 | } | |
1511 | return mainrampagesize; | |
1512 | } | |
1513 | ||
1514 | return hpsize; | |
1515 | } | |
1516 | #else | |
1517 | long qemu_getrampagesize(void) | |
1518 | { | |
1519 | return getpagesize(); | |
1520 | } | |
1521 | #endif | |
1522 | ||
1523 | #ifdef __linux__ | |
1524 | static int64_t get_file_size(int fd) | |
1525 | { | |
1526 | int64_t size = lseek(fd, 0, SEEK_END); | |
1527 | if (size < 0) { | |
1528 | return -errno; | |
1529 | } | |
1530 | return size; | |
1531 | } | |
1532 | ||
1533 | static int file_ram_open(const char *path, | |
1534 | const char *region_name, | |
1535 | bool *created, | |
1536 | Error **errp) | |
1537 | { | |
1538 | char *filename; | |
1539 | char *sanitized_name; | |
1540 | char *c; | |
1541 | int fd = -1; | |
1542 | ||
1543 | *created = false; | |
1544 | for (;;) { | |
1545 | fd = open(path, O_RDWR); | |
1546 | if (fd >= 0) { | |
1547 | /* @path names an existing file, use it */ | |
1548 | break; | |
1549 | } | |
1550 | if (errno == ENOENT) { | |
1551 | /* @path names a file that doesn't exist, create it */ | |
1552 | fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644); | |
1553 | if (fd >= 0) { | |
1554 | *created = true; | |
1555 | break; | |
1556 | } | |
1557 | } else if (errno == EISDIR) { | |
1558 | /* @path names a directory, create a file there */ | |
1559 | /* Make name safe to use with mkstemp by replacing '/' with '_'. */ | |
1560 | sanitized_name = g_strdup(region_name); | |
1561 | for (c = sanitized_name; *c != '\0'; c++) { | |
1562 | if (*c == '/') { | |
1563 | *c = '_'; | |
1564 | } | |
1565 | } | |
1566 | ||
1567 | filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path, | |
1568 | sanitized_name); | |
1569 | g_free(sanitized_name); | |
1570 | ||
1571 | fd = mkstemp(filename); | |
1572 | if (fd >= 0) { | |
1573 | unlink(filename); | |
1574 | g_free(filename); | |
1575 | break; | |
1576 | } | |
1577 | g_free(filename); | |
1578 | } | |
1579 | if (errno != EEXIST && errno != EINTR) { | |
1580 | error_setg_errno(errp, errno, | |
1581 | "can't open backing store %s for guest RAM", | |
1582 | path); | |
1583 | return -1; | |
1584 | } | |
1585 | /* | |
1586 | * Try again on EINTR and EEXIST. The latter happens when | |
1587 | * something else creates the file between our two open(). | |
1588 | */ | |
1589 | } | |
1590 | ||
1591 | return fd; | |
1592 | } | |
1593 | ||
1594 | static void *file_ram_alloc(RAMBlock *block, | |
1595 | ram_addr_t memory, | |
1596 | int fd, | |
1597 | bool truncate, | |
1598 | Error **errp) | |
1599 | { | |
1600 | void *area; | |
1601 | ||
1602 | block->page_size = qemu_fd_getpagesize(fd); | |
1603 | block->mr->align = block->page_size; | |
1604 | #if defined(__s390x__) | |
1605 | if (kvm_enabled()) { | |
1606 | block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN); | |
1607 | } | |
1608 | #endif | |
1609 | ||
1610 | if (memory < block->page_size) { | |
1611 | error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to " | |
1612 | "or larger than page size 0x%zx", | |
1613 | memory, block->page_size); | |
1614 | return NULL; | |
1615 | } | |
1616 | ||
1617 | memory = ROUND_UP(memory, block->page_size); | |
1618 | ||
1619 | /* | |
1620 | * ftruncate is not supported by hugetlbfs in older | |
1621 | * hosts, so don't bother bailing out on errors. | |
1622 | * If anything goes wrong with it under other filesystems, | |
1623 | * mmap will fail. | |
1624 | * | |
1625 | * Do not truncate the non-empty backend file to avoid corrupting | |
1626 | * the existing data in the file. Disabling shrinking is not | |
1627 | * enough. For example, the current vNVDIMM implementation stores | |
1628 | * the guest NVDIMM labels at the end of the backend file. If the | |
1629 | * backend file is later extended, QEMU will not be able to find | |
1630 | * those labels. Therefore, extending the non-empty backend file | |
1631 | * is disabled as well. | |
1632 | */ | |
1633 | if (truncate && ftruncate(fd, memory)) { | |
1634 | perror("ftruncate"); | |
1635 | } | |
1636 | ||
1637 | area = qemu_ram_mmap(fd, memory, block->mr->align, | |
1638 | block->flags & RAM_SHARED); | |
1639 | if (area == MAP_FAILED) { | |
1640 | error_setg_errno(errp, errno, | |
1641 | "unable to map backing store for guest RAM"); | |
1642 | return NULL; | |
1643 | } | |
1644 | ||
1645 | if (mem_prealloc) { | |
1646 | os_mem_prealloc(fd, area, memory, smp_cpus, errp); | |
1647 | if (errp && *errp) { | |
1648 | qemu_ram_munmap(area, memory); | |
1649 | return NULL; | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | block->fd = fd; | |
1654 | return area; | |
1655 | } | |
1656 | #endif | |
1657 | ||
1658 | /* Called with the ramlist lock held. */ | |
1659 | static ram_addr_t find_ram_offset(ram_addr_t size) | |
1660 | { | |
1661 | RAMBlock *block, *next_block; | |
1662 | ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX; | |
1663 | ||
1664 | assert(size != 0); /* it would hand out same offset multiple times */ | |
1665 | ||
1666 | if (QLIST_EMPTY_RCU(&ram_list.blocks)) { | |
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | RAMBLOCK_FOREACH(block) { | |
1671 | ram_addr_t end, next = RAM_ADDR_MAX; | |
1672 | ||
1673 | end = block->offset + block->max_length; | |
1674 | ||
1675 | RAMBLOCK_FOREACH(next_block) { | |
1676 | if (next_block->offset >= end) { | |
1677 | next = MIN(next, next_block->offset); | |
1678 | } | |
1679 | } | |
1680 | if (next - end >= size && next - end < mingap) { | |
1681 | offset = end; | |
1682 | mingap = next - end; | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | if (offset == RAM_ADDR_MAX) { | |
1687 | fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n", | |
1688 | (uint64_t)size); | |
1689 | abort(); | |
1690 | } | |
1691 | ||
1692 | return offset; | |
1693 | } | |
1694 | ||
1695 | unsigned long last_ram_page(void) | |
1696 | { | |
1697 | RAMBlock *block; | |
1698 | ram_addr_t last = 0; | |
1699 | ||
1700 | rcu_read_lock(); | |
1701 | RAMBLOCK_FOREACH(block) { | |
1702 | last = MAX(last, block->offset + block->max_length); | |
1703 | } | |
1704 | rcu_read_unlock(); | |
1705 | return last >> TARGET_PAGE_BITS; | |
1706 | } | |
1707 | ||
1708 | static void qemu_ram_setup_dump(void *addr, ram_addr_t size) | |
1709 | { | |
1710 | int ret; | |
1711 | ||
1712 | /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */ | |
1713 | if (!machine_dump_guest_core(current_machine)) { | |
1714 | ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP); | |
1715 | if (ret) { | |
1716 | perror("qemu_madvise"); | |
1717 | fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, " | |
1718 | "but dump_guest_core=off specified\n"); | |
1719 | } | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | const char *qemu_ram_get_idstr(RAMBlock *rb) | |
1724 | { | |
1725 | return rb->idstr; | |
1726 | } | |
1727 | ||
1728 | bool qemu_ram_is_shared(RAMBlock *rb) | |
1729 | { | |
1730 | return rb->flags & RAM_SHARED; | |
1731 | } | |
1732 | ||
1733 | /* Called with iothread lock held. */ | |
1734 | void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev) | |
1735 | { | |
1736 | RAMBlock *block; | |
1737 | ||
1738 | assert(new_block); | |
1739 | assert(!new_block->idstr[0]); | |
1740 | ||
1741 | if (dev) { | |
1742 | char *id = qdev_get_dev_path(dev); | |
1743 | if (id) { | |
1744 | snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id); | |
1745 | g_free(id); | |
1746 | } | |
1747 | } | |
1748 | pstrcat(new_block->idstr, sizeof(new_block->idstr), name); | |
1749 | ||
1750 | rcu_read_lock(); | |
1751 | RAMBLOCK_FOREACH(block) { | |
1752 | if (block != new_block && | |
1753 | !strcmp(block->idstr, new_block->idstr)) { | |
1754 | fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n", | |
1755 | new_block->idstr); | |
1756 | abort(); | |
1757 | } | |
1758 | } | |
1759 | rcu_read_unlock(); | |
1760 | } | |
1761 | ||
1762 | /* Called with iothread lock held. */ | |
1763 | void qemu_ram_unset_idstr(RAMBlock *block) | |
1764 | { | |
1765 | /* FIXME: arch_init.c assumes that this is not called throughout | |
1766 | * migration. Ignore the problem since hot-unplug during migration | |
1767 | * does not work anyway. | |
1768 | */ | |
1769 | if (block) { | |
1770 | memset(block->idstr, 0, sizeof(block->idstr)); | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | size_t qemu_ram_pagesize(RAMBlock *rb) | |
1775 | { | |
1776 | return rb->page_size; | |
1777 | } | |
1778 | ||
1779 | /* Returns the largest size of page in use */ | |
1780 | size_t qemu_ram_pagesize_largest(void) | |
1781 | { | |
1782 | RAMBlock *block; | |
1783 | size_t largest = 0; | |
1784 | ||
1785 | RAMBLOCK_FOREACH(block) { | |
1786 | largest = MAX(largest, qemu_ram_pagesize(block)); | |
1787 | } | |
1788 | ||
1789 | return largest; | |
1790 | } | |
1791 | ||
1792 | static int memory_try_enable_merging(void *addr, size_t len) | |
1793 | { | |
1794 | if (!machine_mem_merge(current_machine)) { | |
1795 | /* disabled by the user */ | |
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE); | |
1800 | } | |
1801 | ||
1802 | /* Only legal before guest might have detected the memory size: e.g. on | |
1803 | * incoming migration, or right after reset. | |
1804 | * | |
1805 | * As memory core doesn't know how is memory accessed, it is up to | |
1806 | * resize callback to update device state and/or add assertions to detect | |
1807 | * misuse, if necessary. | |
1808 | */ | |
1809 | int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp) | |
1810 | { | |
1811 | assert(block); | |
1812 | ||
1813 | newsize = HOST_PAGE_ALIGN(newsize); | |
1814 | ||
1815 | if (block->used_length == newsize) { | |
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | if (!(block->flags & RAM_RESIZEABLE)) { | |
1820 | error_setg_errno(errp, EINVAL, | |
1821 | "Length mismatch: %s: 0x" RAM_ADDR_FMT | |
1822 | " in != 0x" RAM_ADDR_FMT, block->idstr, | |
1823 | newsize, block->used_length); | |
1824 | return -EINVAL; | |
1825 | } | |
1826 | ||
1827 | if (block->max_length < newsize) { | |
1828 | error_setg_errno(errp, EINVAL, | |
1829 | "Length too large: %s: 0x" RAM_ADDR_FMT | |
1830 | " > 0x" RAM_ADDR_FMT, block->idstr, | |
1831 | newsize, block->max_length); | |
1832 | return -EINVAL; | |
1833 | } | |
1834 | ||
1835 | cpu_physical_memory_clear_dirty_range(block->offset, block->used_length); | |
1836 | block->used_length = newsize; | |
1837 | cpu_physical_memory_set_dirty_range(block->offset, block->used_length, | |
1838 | DIRTY_CLIENTS_ALL); | |
1839 | memory_region_set_size(block->mr, newsize); | |
1840 | if (block->resized) { | |
1841 | block->resized(block->idstr, newsize, block->host); | |
1842 | } | |
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | /* Called with ram_list.mutex held */ | |
1847 | static void dirty_memory_extend(ram_addr_t old_ram_size, | |
1848 | ram_addr_t new_ram_size) | |
1849 | { | |
1850 | ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size, | |
1851 | DIRTY_MEMORY_BLOCK_SIZE); | |
1852 | ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size, | |
1853 | DIRTY_MEMORY_BLOCK_SIZE); | |
1854 | int i; | |
1855 | ||
1856 | /* Only need to extend if block count increased */ | |
1857 | if (new_num_blocks <= old_num_blocks) { | |
1858 | return; | |
1859 | } | |
1860 | ||
1861 | for (i = 0; i < DIRTY_MEMORY_NUM; i++) { | |
1862 | DirtyMemoryBlocks *old_blocks; | |
1863 | DirtyMemoryBlocks *new_blocks; | |
1864 | int j; | |
1865 | ||
1866 | old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]); | |
1867 | new_blocks = g_malloc(sizeof(*new_blocks) + | |
1868 | sizeof(new_blocks->blocks[0]) * new_num_blocks); | |
1869 | ||
1870 | if (old_num_blocks) { | |
1871 | memcpy(new_blocks->blocks, old_blocks->blocks, | |
1872 | old_num_blocks * sizeof(old_blocks->blocks[0])); | |
1873 | } | |
1874 | ||
1875 | for (j = old_num_blocks; j < new_num_blocks; j++) { | |
1876 | new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE); | |
1877 | } | |
1878 | ||
1879 | atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks); | |
1880 | ||
1881 | if (old_blocks) { | |
1882 | g_free_rcu(old_blocks, rcu); | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | ||
1887 | static void ram_block_add(RAMBlock *new_block, Error **errp) | |
1888 | { | |
1889 | RAMBlock *block; | |
1890 | RAMBlock *last_block = NULL; | |
1891 | ram_addr_t old_ram_size, new_ram_size; | |
1892 | Error *err = NULL; | |
1893 | ||
1894 | old_ram_size = last_ram_page(); | |
1895 | ||
1896 | qemu_mutex_lock_ramlist(); | |
1897 | new_block->offset = find_ram_offset(new_block->max_length); | |
1898 | ||
1899 | if (!new_block->host) { | |
1900 | if (xen_enabled()) { | |
1901 | xen_ram_alloc(new_block->offset, new_block->max_length, | |
1902 | new_block->mr, &err); | |
1903 | if (err) { | |
1904 | error_propagate(errp, err); | |
1905 | qemu_mutex_unlock_ramlist(); | |
1906 | return; | |
1907 | } | |
1908 | } else { | |
1909 | new_block->host = phys_mem_alloc(new_block->max_length, | |
1910 | &new_block->mr->align); | |
1911 | if (!new_block->host) { | |
1912 | error_setg_errno(errp, errno, | |
1913 | "cannot set up guest memory '%s'", | |
1914 | memory_region_name(new_block->mr)); | |
1915 | qemu_mutex_unlock_ramlist(); | |
1916 | return; | |
1917 | } | |
1918 | memory_try_enable_merging(new_block->host, new_block->max_length); | |
1919 | } | |
1920 | } | |
1921 | ||
1922 | new_ram_size = MAX(old_ram_size, | |
1923 | (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS); | |
1924 | if (new_ram_size > old_ram_size) { | |
1925 | dirty_memory_extend(old_ram_size, new_ram_size); | |
1926 | } | |
1927 | /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ, | |
1928 | * QLIST (which has an RCU-friendly variant) does not have insertion at | |
1929 | * tail, so save the last element in last_block. | |
1930 | */ | |
1931 | RAMBLOCK_FOREACH(block) { | |
1932 | last_block = block; | |
1933 | if (block->max_length < new_block->max_length) { | |
1934 | break; | |
1935 | } | |
1936 | } | |
1937 | if (block) { | |
1938 | QLIST_INSERT_BEFORE_RCU(block, new_block, next); | |
1939 | } else if (last_block) { | |
1940 | QLIST_INSERT_AFTER_RCU(last_block, new_block, next); | |
1941 | } else { /* list is empty */ | |
1942 | QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next); | |
1943 | } | |
1944 | ram_list.mru_block = NULL; | |
1945 | ||
1946 | /* Write list before version */ | |
1947 | smp_wmb(); | |
1948 | ram_list.version++; | |
1949 | qemu_mutex_unlock_ramlist(); | |
1950 | ||
1951 | cpu_physical_memory_set_dirty_range(new_block->offset, | |
1952 | new_block->used_length, | |
1953 | DIRTY_CLIENTS_ALL); | |
1954 | ||
1955 | if (new_block->host) { | |
1956 | qemu_ram_setup_dump(new_block->host, new_block->max_length); | |
1957 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE); | |
1958 | /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */ | |
1959 | qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK); | |
1960 | ram_block_notify_add(new_block->host, new_block->max_length); | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | #ifdef __linux__ | |
1965 | RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, | |
1966 | bool share, int fd, | |
1967 | Error **errp) | |
1968 | { | |
1969 | RAMBlock *new_block; | |
1970 | Error *local_err = NULL; | |
1971 | int64_t file_size; | |
1972 | ||
1973 | if (xen_enabled()) { | |
1974 | error_setg(errp, "-mem-path not supported with Xen"); | |
1975 | return NULL; | |
1976 | } | |
1977 | ||
1978 | if (kvm_enabled() && !kvm_has_sync_mmu()) { | |
1979 | error_setg(errp, | |
1980 | "host lacks kvm mmu notifiers, -mem-path unsupported"); | |
1981 | return NULL; | |
1982 | } | |
1983 | ||
1984 | if (phys_mem_alloc != qemu_anon_ram_alloc) { | |
1985 | /* | |
1986 | * file_ram_alloc() needs to allocate just like | |
1987 | * phys_mem_alloc, but we haven't bothered to provide | |
1988 | * a hook there. | |
1989 | */ | |
1990 | error_setg(errp, | |
1991 | "-mem-path not supported with this accelerator"); | |
1992 | return NULL; | |
1993 | } | |
1994 | ||
1995 | size = HOST_PAGE_ALIGN(size); | |
1996 | file_size = get_file_size(fd); | |
1997 | if (file_size > 0 && file_size < size) { | |
1998 | error_setg(errp, "backing store %s size 0x%" PRIx64 | |
1999 | " does not match 'size' option 0x" RAM_ADDR_FMT, | |
2000 | mem_path, file_size, size); | |
2001 | return NULL; | |
2002 | } | |
2003 | ||
2004 | new_block = g_malloc0(sizeof(*new_block)); | |
2005 | new_block->mr = mr; | |
2006 | new_block->used_length = size; | |
2007 | new_block->max_length = size; | |
2008 | new_block->flags = share ? RAM_SHARED : 0; | |
2009 | new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp); | |
2010 | if (!new_block->host) { | |
2011 | g_free(new_block); | |
2012 | return NULL; | |
2013 | } | |
2014 | ||
2015 | ram_block_add(new_block, &local_err); | |
2016 | if (local_err) { | |
2017 | g_free(new_block); | |
2018 | error_propagate(errp, local_err); | |
2019 | return NULL; | |
2020 | } | |
2021 | return new_block; | |
2022 | ||
2023 | } | |
2024 | ||
2025 | ||
2026 | RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr, | |
2027 | bool share, const char *mem_path, | |
2028 | Error **errp) | |
2029 | { | |
2030 | int fd; | |
2031 | bool created; | |
2032 | RAMBlock *block; | |
2033 | ||
2034 | fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp); | |
2035 | if (fd < 0) { | |
2036 | return NULL; | |
2037 | } | |
2038 | ||
2039 | block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp); | |
2040 | if (!block) { | |
2041 | if (created) { | |
2042 | unlink(mem_path); | |
2043 | } | |
2044 | close(fd); | |
2045 | return NULL; | |
2046 | } | |
2047 | ||
2048 | return block; | |
2049 | } | |
2050 | #endif | |
2051 | ||
2052 | static | |
2053 | RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size, | |
2054 | void (*resized)(const char*, | |
2055 | uint64_t length, | |
2056 | void *host), | |
2057 | void *host, bool resizeable, | |
2058 | MemoryRegion *mr, Error **errp) | |
2059 | { | |
2060 | RAMBlock *new_block; | |
2061 | Error *local_err = NULL; | |
2062 | ||
2063 | size = HOST_PAGE_ALIGN(size); | |
2064 | max_size = HOST_PAGE_ALIGN(max_size); | |
2065 | new_block = g_malloc0(sizeof(*new_block)); | |
2066 | new_block->mr = mr; | |
2067 | new_block->resized = resized; | |
2068 | new_block->used_length = size; | |
2069 | new_block->max_length = max_size; | |
2070 | assert(max_size >= size); | |
2071 | new_block->fd = -1; | |
2072 | new_block->page_size = getpagesize(); | |
2073 | new_block->host = host; | |
2074 | if (host) { | |
2075 | new_block->flags |= RAM_PREALLOC; | |
2076 | } | |
2077 | if (resizeable) { | |
2078 | new_block->flags |= RAM_RESIZEABLE; | |
2079 | } | |
2080 | ram_block_add(new_block, &local_err); | |
2081 | if (local_err) { | |
2082 | g_free(new_block); | |
2083 | error_propagate(errp, local_err); | |
2084 | return NULL; | |
2085 | } | |
2086 | return new_block; | |
2087 | } | |
2088 | ||
2089 | RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host, | |
2090 | MemoryRegion *mr, Error **errp) | |
2091 | { | |
2092 | return qemu_ram_alloc_internal(size, size, NULL, host, false, mr, errp); | |
2093 | } | |
2094 | ||
2095 | RAMBlock *qemu_ram_alloc(ram_addr_t size, MemoryRegion *mr, Error **errp) | |
2096 | { | |
2097 | return qemu_ram_alloc_internal(size, size, NULL, NULL, false, mr, errp); | |
2098 | } | |
2099 | ||
2100 | RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz, | |
2101 | void (*resized)(const char*, | |
2102 | uint64_t length, | |
2103 | void *host), | |
2104 | MemoryRegion *mr, Error **errp) | |
2105 | { | |
2106 | return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true, mr, errp); | |
2107 | } | |
2108 | ||
2109 | static void reclaim_ramblock(RAMBlock *block) | |
2110 | { | |
2111 | if (block->flags & RAM_PREALLOC) { | |
2112 | ; | |
2113 | } else if (xen_enabled()) { | |
2114 | xen_invalidate_map_cache_entry(block->host); | |
2115 | #ifndef _WIN32 | |
2116 | } else if (block->fd >= 0) { | |
2117 | qemu_ram_munmap(block->host, block->max_length); | |
2118 | close(block->fd); | |
2119 | #endif | |
2120 | } else { | |
2121 | qemu_anon_ram_free(block->host, block->max_length); | |
2122 | } | |
2123 | g_free(block); | |
2124 | } | |
2125 | ||
2126 | void qemu_ram_free(RAMBlock *block) | |
2127 | { | |
2128 | if (!block) { | |
2129 | return; | |
2130 | } | |
2131 | ||
2132 | if (block->host) { | |
2133 | ram_block_notify_remove(block->host, block->max_length); | |
2134 | } | |
2135 | ||
2136 | qemu_mutex_lock_ramlist(); | |
2137 | QLIST_REMOVE_RCU(block, next); | |
2138 | ram_list.mru_block = NULL; | |
2139 | /* Write list before version */ | |
2140 | smp_wmb(); | |
2141 | ram_list.version++; | |
2142 | call_rcu(block, reclaim_ramblock, rcu); | |
2143 | qemu_mutex_unlock_ramlist(); | |
2144 | } | |
2145 | ||
2146 | #ifndef _WIN32 | |
2147 | void qemu_ram_remap(ram_addr_t addr, ram_addr_t length) | |
2148 | { | |
2149 | RAMBlock *block; | |
2150 | ram_addr_t offset; | |
2151 | int flags; | |
2152 | void *area, *vaddr; | |
2153 | ||
2154 | RAMBLOCK_FOREACH(block) { | |
2155 | offset = addr - block->offset; | |
2156 | if (offset < block->max_length) { | |
2157 | vaddr = ramblock_ptr(block, offset); | |
2158 | if (block->flags & RAM_PREALLOC) { | |
2159 | ; | |
2160 | } else if (xen_enabled()) { | |
2161 | abort(); | |
2162 | } else { | |
2163 | flags = MAP_FIXED; | |
2164 | if (block->fd >= 0) { | |
2165 | flags |= (block->flags & RAM_SHARED ? | |
2166 | MAP_SHARED : MAP_PRIVATE); | |
2167 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2168 | flags, block->fd, offset); | |
2169 | } else { | |
2170 | /* | |
2171 | * Remap needs to match alloc. Accelerators that | |
2172 | * set phys_mem_alloc never remap. If they did, | |
2173 | * we'd need a remap hook here. | |
2174 | */ | |
2175 | assert(phys_mem_alloc == qemu_anon_ram_alloc); | |
2176 | ||
2177 | flags |= MAP_PRIVATE | MAP_ANONYMOUS; | |
2178 | area = mmap(vaddr, length, PROT_READ | PROT_WRITE, | |
2179 | flags, -1, 0); | |
2180 | } | |
2181 | if (area != vaddr) { | |
2182 | fprintf(stderr, "Could not remap addr: " | |
2183 | RAM_ADDR_FMT "@" RAM_ADDR_FMT "\n", | |
2184 | length, addr); | |
2185 | exit(1); | |
2186 | } | |
2187 | memory_try_enable_merging(vaddr, length); | |
2188 | qemu_ram_setup_dump(vaddr, length); | |
2189 | } | |
2190 | } | |
2191 | } | |
2192 | } | |
2193 | #endif /* !_WIN32 */ | |
2194 | ||
2195 | /* Return a host pointer to ram allocated with qemu_ram_alloc. | |
2196 | * This should not be used for general purpose DMA. Use address_space_map | |
2197 | * or address_space_rw instead. For local memory (e.g. video ram) that the | |
2198 | * device owns, use memory_region_get_ram_ptr. | |
2199 | * | |
2200 | * Called within RCU critical section. | |
2201 | */ | |
2202 | void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr) | |
2203 | { | |
2204 | RAMBlock *block = ram_block; | |
2205 | ||
2206 | if (block == NULL) { | |
2207 | block = qemu_get_ram_block(addr); | |
2208 | addr -= block->offset; | |
2209 | } | |
2210 | ||
2211 | if (xen_enabled() && block->host == NULL) { | |
2212 | /* We need to check if the requested address is in the RAM | |
2213 | * because we don't want to map the entire memory in QEMU. | |
2214 | * In that case just map until the end of the page. | |
2215 | */ | |
2216 | if (block->offset == 0) { | |
2217 | return xen_map_cache(addr, 0, 0, false); | |
2218 | } | |
2219 | ||
2220 | block->host = xen_map_cache(block->offset, block->max_length, 1, false); | |
2221 | } | |
2222 | return ramblock_ptr(block, addr); | |
2223 | } | |
2224 | ||
2225 | /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr | |
2226 | * but takes a size argument. | |
2227 | * | |
2228 | * Called within RCU critical section. | |
2229 | */ | |
2230 | static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr, | |
2231 | hwaddr *size, bool lock) | |
2232 | { | |
2233 | RAMBlock *block = ram_block; | |
2234 | if (*size == 0) { | |
2235 | return NULL; | |
2236 | } | |
2237 | ||
2238 | if (block == NULL) { | |
2239 | block = qemu_get_ram_block(addr); | |
2240 | addr -= block->offset; | |
2241 | } | |
2242 | *size = MIN(*size, block->max_length - addr); | |
2243 | ||
2244 | if (xen_enabled() && block->host == NULL) { | |
2245 | /* We need to check if the requested address is in the RAM | |
2246 | * because we don't want to map the entire memory in QEMU. | |
2247 | * In that case just map the requested area. | |
2248 | */ | |
2249 | if (block->offset == 0) { | |
2250 | return xen_map_cache(addr, *size, lock, lock); | |
2251 | } | |
2252 | ||
2253 | block->host = xen_map_cache(block->offset, block->max_length, 1, lock); | |
2254 | } | |
2255 | ||
2256 | return ramblock_ptr(block, addr); | |
2257 | } | |
2258 | ||
2259 | /* | |
2260 | * Translates a host ptr back to a RAMBlock, a ram_addr and an offset | |
2261 | * in that RAMBlock. | |
2262 | * | |
2263 | * ptr: Host pointer to look up | |
2264 | * round_offset: If true round the result offset down to a page boundary | |
2265 | * *ram_addr: set to result ram_addr | |
2266 | * *offset: set to result offset within the RAMBlock | |
2267 | * | |
2268 | * Returns: RAMBlock (or NULL if not found) | |
2269 | * | |
2270 | * By the time this function returns, the returned pointer is not protected | |
2271 | * by RCU anymore. If the caller is not within an RCU critical section and | |
2272 | * does not hold the iothread lock, it must have other means of protecting the | |
2273 | * pointer, such as a reference to the region that includes the incoming | |
2274 | * ram_addr_t. | |
2275 | */ | |
2276 | RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, | |
2277 | ram_addr_t *offset) | |
2278 | { | |
2279 | RAMBlock *block; | |
2280 | uint8_t *host = ptr; | |
2281 | ||
2282 | if (xen_enabled()) { | |
2283 | ram_addr_t ram_addr; | |
2284 | rcu_read_lock(); | |
2285 | ram_addr = xen_ram_addr_from_mapcache(ptr); | |
2286 | block = qemu_get_ram_block(ram_addr); | |
2287 | if (block) { | |
2288 | *offset = ram_addr - block->offset; | |
2289 | } | |
2290 | rcu_read_unlock(); | |
2291 | return block; | |
2292 | } | |
2293 | ||
2294 | rcu_read_lock(); | |
2295 | block = atomic_rcu_read(&ram_list.mru_block); | |
2296 | if (block && block->host && host - block->host < block->max_length) { | |
2297 | goto found; | |
2298 | } | |
2299 | ||
2300 | RAMBLOCK_FOREACH(block) { | |
2301 | /* This case append when the block is not mapped. */ | |
2302 | if (block->host == NULL) { | |
2303 | continue; | |
2304 | } | |
2305 | if (host - block->host < block->max_length) { | |
2306 | goto found; | |
2307 | } | |
2308 | } | |
2309 | ||
2310 | rcu_read_unlock(); | |
2311 | return NULL; | |
2312 | ||
2313 | found: | |
2314 | *offset = (host - block->host); | |
2315 | if (round_offset) { | |
2316 | *offset &= TARGET_PAGE_MASK; | |
2317 | } | |
2318 | rcu_read_unlock(); | |
2319 | return block; | |
2320 | } | |
2321 | ||
2322 | /* | |
2323 | * Finds the named RAMBlock | |
2324 | * | |
2325 | * name: The name of RAMBlock to find | |
2326 | * | |
2327 | * Returns: RAMBlock (or NULL if not found) | |
2328 | */ | |
2329 | RAMBlock *qemu_ram_block_by_name(const char *name) | |
2330 | { | |
2331 | RAMBlock *block; | |
2332 | ||
2333 | RAMBLOCK_FOREACH(block) { | |
2334 | if (!strcmp(name, block->idstr)) { | |
2335 | return block; | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | return NULL; | |
2340 | } | |
2341 | ||
2342 | /* Some of the softmmu routines need to translate from a host pointer | |
2343 | (typically a TLB entry) back to a ram offset. */ | |
2344 | ram_addr_t qemu_ram_addr_from_host(void *ptr) | |
2345 | { | |
2346 | RAMBlock *block; | |
2347 | ram_addr_t offset; | |
2348 | ||
2349 | block = qemu_ram_block_from_host(ptr, false, &offset); | |
2350 | if (!block) { | |
2351 | return RAM_ADDR_INVALID; | |
2352 | } | |
2353 | ||
2354 | return block->offset + offset; | |
2355 | } | |
2356 | ||
2357 | /* Called within RCU critical section. */ | |
2358 | static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | |
2359 | uint64_t val, unsigned size) | |
2360 | { | |
2361 | bool locked = false; | |
2362 | ||
2363 | assert(tcg_enabled()); | |
2364 | if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) { | |
2365 | locked = true; | |
2366 | tb_lock(); | |
2367 | tb_invalidate_phys_page_fast(ram_addr, size); | |
2368 | } | |
2369 | switch (size) { | |
2370 | case 1: | |
2371 | stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2372 | break; | |
2373 | case 2: | |
2374 | stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2375 | break; | |
2376 | case 4: | |
2377 | stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2378 | break; | |
2379 | case 8: | |
2380 | stq_p(qemu_map_ram_ptr(NULL, ram_addr), val); | |
2381 | break; | |
2382 | default: | |
2383 | abort(); | |
2384 | } | |
2385 | ||
2386 | if (locked) { | |
2387 | tb_unlock(); | |
2388 | } | |
2389 | ||
2390 | /* Set both VGA and migration bits for simplicity and to remove | |
2391 | * the notdirty callback faster. | |
2392 | */ | |
2393 | cpu_physical_memory_set_dirty_range(ram_addr, size, | |
2394 | DIRTY_CLIENTS_NOCODE); | |
2395 | /* we remove the notdirty callback only if the code has been | |
2396 | flushed */ | |
2397 | if (!cpu_physical_memory_is_clean(ram_addr)) { | |
2398 | tlb_set_dirty(current_cpu, current_cpu->mem_io_vaddr); | |
2399 | } | |
2400 | } | |
2401 | ||
2402 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, | |
2403 | unsigned size, bool is_write) | |
2404 | { | |
2405 | return is_write; | |
2406 | } | |
2407 | ||
2408 | static const MemoryRegionOps notdirty_mem_ops = { | |
2409 | .write = notdirty_mem_write, | |
2410 | .valid.accepts = notdirty_mem_accepts, | |
2411 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2412 | .valid = { | |
2413 | .min_access_size = 1, | |
2414 | .max_access_size = 8, | |
2415 | .unaligned = false, | |
2416 | }, | |
2417 | .impl = { | |
2418 | .min_access_size = 1, | |
2419 | .max_access_size = 8, | |
2420 | .unaligned = false, | |
2421 | }, | |
2422 | }; | |
2423 | ||
2424 | /* Generate a debug exception if a watchpoint has been hit. */ | |
2425 | static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags) | |
2426 | { | |
2427 | CPUState *cpu = current_cpu; | |
2428 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
2429 | CPUArchState *env = cpu->env_ptr; | |
2430 | target_ulong pc, cs_base; | |
2431 | target_ulong vaddr; | |
2432 | CPUWatchpoint *wp; | |
2433 | uint32_t cpu_flags; | |
2434 | ||
2435 | assert(tcg_enabled()); | |
2436 | if (cpu->watchpoint_hit) { | |
2437 | /* We re-entered the check after replacing the TB. Now raise | |
2438 | * the debug interrupt so that is will trigger after the | |
2439 | * current instruction. */ | |
2440 | cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); | |
2441 | return; | |
2442 | } | |
2443 | vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; | |
2444 | vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len); | |
2445 | QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { | |
2446 | if (cpu_watchpoint_address_matches(wp, vaddr, len) | |
2447 | && (wp->flags & flags)) { | |
2448 | if (flags == BP_MEM_READ) { | |
2449 | wp->flags |= BP_WATCHPOINT_HIT_READ; | |
2450 | } else { | |
2451 | wp->flags |= BP_WATCHPOINT_HIT_WRITE; | |
2452 | } | |
2453 | wp->hitaddr = vaddr; | |
2454 | wp->hitattrs = attrs; | |
2455 | if (!cpu->watchpoint_hit) { | |
2456 | if (wp->flags & BP_CPU && | |
2457 | !cc->debug_check_watchpoint(cpu, wp)) { | |
2458 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2459 | continue; | |
2460 | } | |
2461 | cpu->watchpoint_hit = wp; | |
2462 | ||
2463 | /* Both tb_lock and iothread_mutex will be reset when | |
2464 | * cpu_loop_exit or cpu_loop_exit_noexc longjmp | |
2465 | * back into the cpu_exec main loop. | |
2466 | */ | |
2467 | tb_lock(); | |
2468 | tb_check_watchpoint(cpu); | |
2469 | if (wp->flags & BP_STOP_BEFORE_ACCESS) { | |
2470 | cpu->exception_index = EXCP_DEBUG; | |
2471 | cpu_loop_exit(cpu); | |
2472 | } else { | |
2473 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags); | |
2474 | tb_gen_code(cpu, pc, cs_base, cpu_flags, 1); | |
2475 | cpu_loop_exit_noexc(cpu); | |
2476 | } | |
2477 | } | |
2478 | } else { | |
2479 | wp->flags &= ~BP_WATCHPOINT_HIT; | |
2480 | } | |
2481 | } | |
2482 | } | |
2483 | ||
2484 | /* Watchpoint access routines. Watchpoints are inserted using TLB tricks, | |
2485 | so these check for a hit then pass through to the normal out-of-line | |
2486 | phys routines. */ | |
2487 | static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata, | |
2488 | unsigned size, MemTxAttrs attrs) | |
2489 | { | |
2490 | MemTxResult res; | |
2491 | uint64_t data; | |
2492 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); | |
2493 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
2494 | ||
2495 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ); | |
2496 | switch (size) { | |
2497 | case 1: | |
2498 | data = address_space_ldub(as, addr, attrs, &res); | |
2499 | break; | |
2500 | case 2: | |
2501 | data = address_space_lduw(as, addr, attrs, &res); | |
2502 | break; | |
2503 | case 4: | |
2504 | data = address_space_ldl(as, addr, attrs, &res); | |
2505 | break; | |
2506 | case 8: | |
2507 | data = address_space_ldq(as, addr, attrs, &res); | |
2508 | break; | |
2509 | default: abort(); | |
2510 | } | |
2511 | *pdata = data; | |
2512 | return res; | |
2513 | } | |
2514 | ||
2515 | static MemTxResult watch_mem_write(void *opaque, hwaddr addr, | |
2516 | uint64_t val, unsigned size, | |
2517 | MemTxAttrs attrs) | |
2518 | { | |
2519 | MemTxResult res; | |
2520 | int asidx = cpu_asidx_from_attrs(current_cpu, attrs); | |
2521 | AddressSpace *as = current_cpu->cpu_ases[asidx].as; | |
2522 | ||
2523 | check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE); | |
2524 | switch (size) { | |
2525 | case 1: | |
2526 | address_space_stb(as, addr, val, attrs, &res); | |
2527 | break; | |
2528 | case 2: | |
2529 | address_space_stw(as, addr, val, attrs, &res); | |
2530 | break; | |
2531 | case 4: | |
2532 | address_space_stl(as, addr, val, attrs, &res); | |
2533 | break; | |
2534 | case 8: | |
2535 | address_space_stq(as, addr, val, attrs, &res); | |
2536 | break; | |
2537 | default: abort(); | |
2538 | } | |
2539 | return res; | |
2540 | } | |
2541 | ||
2542 | static const MemoryRegionOps watch_mem_ops = { | |
2543 | .read_with_attrs = watch_mem_read, | |
2544 | .write_with_attrs = watch_mem_write, | |
2545 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2546 | .valid = { | |
2547 | .min_access_size = 1, | |
2548 | .max_access_size = 8, | |
2549 | .unaligned = false, | |
2550 | }, | |
2551 | .impl = { | |
2552 | .min_access_size = 1, | |
2553 | .max_access_size = 8, | |
2554 | .unaligned = false, | |
2555 | }, | |
2556 | }; | |
2557 | ||
2558 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | |
2559 | const uint8_t *buf, int len); | |
2560 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
2561 | bool is_write); | |
2562 | ||
2563 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, | |
2564 | unsigned len, MemTxAttrs attrs) | |
2565 | { | |
2566 | subpage_t *subpage = opaque; | |
2567 | uint8_t buf[8]; | |
2568 | MemTxResult res; | |
2569 | ||
2570 | #if defined(DEBUG_SUBPAGE) | |
2571 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, | |
2572 | subpage, len, addr); | |
2573 | #endif | |
2574 | res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); | |
2575 | if (res) { | |
2576 | return res; | |
2577 | } | |
2578 | switch (len) { | |
2579 | case 1: | |
2580 | *data = ldub_p(buf); | |
2581 | return MEMTX_OK; | |
2582 | case 2: | |
2583 | *data = lduw_p(buf); | |
2584 | return MEMTX_OK; | |
2585 | case 4: | |
2586 | *data = ldl_p(buf); | |
2587 | return MEMTX_OK; | |
2588 | case 8: | |
2589 | *data = ldq_p(buf); | |
2590 | return MEMTX_OK; | |
2591 | default: | |
2592 | abort(); | |
2593 | } | |
2594 | } | |
2595 | ||
2596 | static MemTxResult subpage_write(void *opaque, hwaddr addr, | |
2597 | uint64_t value, unsigned len, MemTxAttrs attrs) | |
2598 | { | |
2599 | subpage_t *subpage = opaque; | |
2600 | uint8_t buf[8]; | |
2601 | ||
2602 | #if defined(DEBUG_SUBPAGE) | |
2603 | printf("%s: subpage %p len %u addr " TARGET_FMT_plx | |
2604 | " value %"PRIx64"\n", | |
2605 | __func__, subpage, len, addr, value); | |
2606 | #endif | |
2607 | switch (len) { | |
2608 | case 1: | |
2609 | stb_p(buf, value); | |
2610 | break; | |
2611 | case 2: | |
2612 | stw_p(buf, value); | |
2613 | break; | |
2614 | case 4: | |
2615 | stl_p(buf, value); | |
2616 | break; | |
2617 | case 8: | |
2618 | stq_p(buf, value); | |
2619 | break; | |
2620 | default: | |
2621 | abort(); | |
2622 | } | |
2623 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); | |
2624 | } | |
2625 | ||
2626 | static bool subpage_accepts(void *opaque, hwaddr addr, | |
2627 | unsigned len, bool is_write) | |
2628 | { | |
2629 | subpage_t *subpage = opaque; | |
2630 | #if defined(DEBUG_SUBPAGE) | |
2631 | printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", | |
2632 | __func__, subpage, is_write ? 'w' : 'r', len, addr); | |
2633 | #endif | |
2634 | ||
2635 | return flatview_access_valid(subpage->fv, addr + subpage->base, | |
2636 | len, is_write); | |
2637 | } | |
2638 | ||
2639 | static const MemoryRegionOps subpage_ops = { | |
2640 | .read_with_attrs = subpage_read, | |
2641 | .write_with_attrs = subpage_write, | |
2642 | .impl.min_access_size = 1, | |
2643 | .impl.max_access_size = 8, | |
2644 | .valid.min_access_size = 1, | |
2645 | .valid.max_access_size = 8, | |
2646 | .valid.accepts = subpage_accepts, | |
2647 | .endianness = DEVICE_NATIVE_ENDIAN, | |
2648 | }; | |
2649 | ||
2650 | static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, | |
2651 | uint16_t section) | |
2652 | { | |
2653 | int idx, eidx; | |
2654 | ||
2655 | if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE) | |
2656 | return -1; | |
2657 | idx = SUBPAGE_IDX(start); | |
2658 | eidx = SUBPAGE_IDX(end); | |
2659 | #if defined(DEBUG_SUBPAGE) | |
2660 | printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n", | |
2661 | __func__, mmio, start, end, idx, eidx, section); | |
2662 | #endif | |
2663 | for (; idx <= eidx; idx++) { | |
2664 | mmio->sub_section[idx] = section; | |
2665 | } | |
2666 | ||
2667 | return 0; | |
2668 | } | |
2669 | ||
2670 | static subpage_t *subpage_init(FlatView *fv, hwaddr base) | |
2671 | { | |
2672 | subpage_t *mmio; | |
2673 | ||
2674 | mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); | |
2675 | mmio->fv = fv; | |
2676 | mmio->base = base; | |
2677 | memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio, | |
2678 | NULL, TARGET_PAGE_SIZE); | |
2679 | mmio->iomem.subpage = true; | |
2680 | #if defined(DEBUG_SUBPAGE) | |
2681 | printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, | |
2682 | mmio, base, TARGET_PAGE_SIZE); | |
2683 | #endif | |
2684 | subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); | |
2685 | ||
2686 | return mmio; | |
2687 | } | |
2688 | ||
2689 | static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr) | |
2690 | { | |
2691 | assert(fv); | |
2692 | MemoryRegionSection section = { | |
2693 | .fv = fv, | |
2694 | .mr = mr, | |
2695 | .offset_within_address_space = 0, | |
2696 | .offset_within_region = 0, | |
2697 | .size = int128_2_64(), | |
2698 | }; | |
2699 | ||
2700 | return phys_section_add(map, §ion); | |
2701 | } | |
2702 | ||
2703 | MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) | |
2704 | { | |
2705 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | |
2706 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | |
2707 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); | |
2708 | MemoryRegionSection *sections = d->map.sections; | |
2709 | ||
2710 | return sections[index & ~TARGET_PAGE_MASK].mr; | |
2711 | } | |
2712 | ||
2713 | static void io_mem_init(void) | |
2714 | { | |
2715 | memory_region_init_io(&io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX); | |
2716 | memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL, | |
2717 | NULL, UINT64_MAX); | |
2718 | ||
2719 | /* io_mem_notdirty calls tb_invalidate_phys_page_fast, | |
2720 | * which can be called without the iothread mutex. | |
2721 | */ | |
2722 | memory_region_init_io(&io_mem_notdirty, NULL, ¬dirty_mem_ops, NULL, | |
2723 | NULL, UINT64_MAX); | |
2724 | memory_region_clear_global_locking(&io_mem_notdirty); | |
2725 | ||
2726 | memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL, | |
2727 | NULL, UINT64_MAX); | |
2728 | } | |
2729 | ||
2730 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv) | |
2731 | { | |
2732 | AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); | |
2733 | uint16_t n; | |
2734 | ||
2735 | n = dummy_section(&d->map, fv, &io_mem_unassigned); | |
2736 | assert(n == PHYS_SECTION_UNASSIGNED); | |
2737 | n = dummy_section(&d->map, fv, &io_mem_notdirty); | |
2738 | assert(n == PHYS_SECTION_NOTDIRTY); | |
2739 | n = dummy_section(&d->map, fv, &io_mem_rom); | |
2740 | assert(n == PHYS_SECTION_ROM); | |
2741 | n = dummy_section(&d->map, fv, &io_mem_watch); | |
2742 | assert(n == PHYS_SECTION_WATCH); | |
2743 | ||
2744 | d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; | |
2745 | ||
2746 | return d; | |
2747 | } | |
2748 | ||
2749 | void address_space_dispatch_free(AddressSpaceDispatch *d) | |
2750 | { | |
2751 | phys_sections_free(&d->map); | |
2752 | g_free(d); | |
2753 | } | |
2754 | ||
2755 | static void tcg_commit(MemoryListener *listener) | |
2756 | { | |
2757 | CPUAddressSpace *cpuas; | |
2758 | AddressSpaceDispatch *d; | |
2759 | ||
2760 | /* since each CPU stores ram addresses in its TLB cache, we must | |
2761 | reset the modified entries */ | |
2762 | cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener); | |
2763 | cpu_reloading_memory_map(); | |
2764 | /* The CPU and TLB are protected by the iothread lock. | |
2765 | * We reload the dispatch pointer now because cpu_reloading_memory_map() | |
2766 | * may have split the RCU critical section. | |
2767 | */ | |
2768 | d = address_space_to_dispatch(cpuas->as); | |
2769 | atomic_rcu_set(&cpuas->memory_dispatch, d); | |
2770 | tlb_flush(cpuas->cpu); | |
2771 | } | |
2772 | ||
2773 | static void memory_map_init(void) | |
2774 | { | |
2775 | system_memory = g_malloc(sizeof(*system_memory)); | |
2776 | ||
2777 | memory_region_init(system_memory, NULL, "system", UINT64_MAX); | |
2778 | address_space_init(&address_space_memory, system_memory, "memory"); | |
2779 | ||
2780 | system_io = g_malloc(sizeof(*system_io)); | |
2781 | memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io", | |
2782 | 65536); | |
2783 | address_space_init(&address_space_io, system_io, "I/O"); | |
2784 | } | |
2785 | ||
2786 | MemoryRegion *get_system_memory(void) | |
2787 | { | |
2788 | return system_memory; | |
2789 | } | |
2790 | ||
2791 | MemoryRegion *get_system_io(void) | |
2792 | { | |
2793 | return system_io; | |
2794 | } | |
2795 | ||
2796 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
2797 | ||
2798 | /* physical memory access (slow version, mainly for debug) */ | |
2799 | #if defined(CONFIG_USER_ONLY) | |
2800 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, | |
2801 | uint8_t *buf, int len, int is_write) | |
2802 | { | |
2803 | int l, flags; | |
2804 | target_ulong page; | |
2805 | void * p; | |
2806 | ||
2807 | while (len > 0) { | |
2808 | page = addr & TARGET_PAGE_MASK; | |
2809 | l = (page + TARGET_PAGE_SIZE) - addr; | |
2810 | if (l > len) | |
2811 | l = len; | |
2812 | flags = page_get_flags(page); | |
2813 | if (!(flags & PAGE_VALID)) | |
2814 | return -1; | |
2815 | if (is_write) { | |
2816 | if (!(flags & PAGE_WRITE)) | |
2817 | return -1; | |
2818 | /* XXX: this code should not depend on lock_user */ | |
2819 | if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) | |
2820 | return -1; | |
2821 | memcpy(p, buf, l); | |
2822 | unlock_user(p, addr, l); | |
2823 | } else { | |
2824 | if (!(flags & PAGE_READ)) | |
2825 | return -1; | |
2826 | /* XXX: this code should not depend on lock_user */ | |
2827 | if (!(p = lock_user(VERIFY_READ, addr, l, 1))) | |
2828 | return -1; | |
2829 | memcpy(buf, p, l); | |
2830 | unlock_user(p, addr, 0); | |
2831 | } | |
2832 | len -= l; | |
2833 | buf += l; | |
2834 | addr += l; | |
2835 | } | |
2836 | return 0; | |
2837 | } | |
2838 | ||
2839 | #else | |
2840 | ||
2841 | static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr, | |
2842 | hwaddr length) | |
2843 | { | |
2844 | uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr); | |
2845 | addr += memory_region_get_ram_addr(mr); | |
2846 | ||
2847 | /* No early return if dirty_log_mask is or becomes 0, because | |
2848 | * cpu_physical_memory_set_dirty_range will still call | |
2849 | * xen_modified_memory. | |
2850 | */ | |
2851 | if (dirty_log_mask) { | |
2852 | dirty_log_mask = | |
2853 | cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask); | |
2854 | } | |
2855 | if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) { | |
2856 | assert(tcg_enabled()); | |
2857 | tb_lock(); | |
2858 | tb_invalidate_phys_range(addr, addr + length); | |
2859 | tb_unlock(); | |
2860 | dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE); | |
2861 | } | |
2862 | cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask); | |
2863 | } | |
2864 | ||
2865 | static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) | |
2866 | { | |
2867 | unsigned access_size_max = mr->ops->valid.max_access_size; | |
2868 | ||
2869 | /* Regions are assumed to support 1-4 byte accesses unless | |
2870 | otherwise specified. */ | |
2871 | if (access_size_max == 0) { | |
2872 | access_size_max = 4; | |
2873 | } | |
2874 | ||
2875 | /* Bound the maximum access by the alignment of the address. */ | |
2876 | if (!mr->ops->impl.unaligned) { | |
2877 | unsigned align_size_max = addr & -addr; | |
2878 | if (align_size_max != 0 && align_size_max < access_size_max) { | |
2879 | access_size_max = align_size_max; | |
2880 | } | |
2881 | } | |
2882 | ||
2883 | /* Don't attempt accesses larger than the maximum. */ | |
2884 | if (l > access_size_max) { | |
2885 | l = access_size_max; | |
2886 | } | |
2887 | l = pow2floor(l); | |
2888 | ||
2889 | return l; | |
2890 | } | |
2891 | ||
2892 | static bool prepare_mmio_access(MemoryRegion *mr) | |
2893 | { | |
2894 | bool unlocked = !qemu_mutex_iothread_locked(); | |
2895 | bool release_lock = false; | |
2896 | ||
2897 | if (unlocked && mr->global_locking) { | |
2898 | qemu_mutex_lock_iothread(); | |
2899 | unlocked = false; | |
2900 | release_lock = true; | |
2901 | } | |
2902 | if (mr->flush_coalesced_mmio) { | |
2903 | if (unlocked) { | |
2904 | qemu_mutex_lock_iothread(); | |
2905 | } | |
2906 | qemu_flush_coalesced_mmio_buffer(); | |
2907 | if (unlocked) { | |
2908 | qemu_mutex_unlock_iothread(); | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | return release_lock; | |
2913 | } | |
2914 | ||
2915 | /* Called within RCU critical section. */ | |
2916 | static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, | |
2917 | MemTxAttrs attrs, | |
2918 | const uint8_t *buf, | |
2919 | int len, hwaddr addr1, | |
2920 | hwaddr l, MemoryRegion *mr) | |
2921 | { | |
2922 | uint8_t *ptr; | |
2923 | uint64_t val; | |
2924 | MemTxResult result = MEMTX_OK; | |
2925 | bool release_lock = false; | |
2926 | ||
2927 | for (;;) { | |
2928 | if (!memory_access_is_direct(mr, true)) { | |
2929 | release_lock |= prepare_mmio_access(mr); | |
2930 | l = memory_access_size(mr, l, addr1); | |
2931 | /* XXX: could force current_cpu to NULL to avoid | |
2932 | potential bugs */ | |
2933 | switch (l) { | |
2934 | case 8: | |
2935 | /* 64 bit write access */ | |
2936 | val = ldq_p(buf); | |
2937 | result |= memory_region_dispatch_write(mr, addr1, val, 8, | |
2938 | attrs); | |
2939 | break; | |
2940 | case 4: | |
2941 | /* 32 bit write access */ | |
2942 | val = (uint32_t)ldl_p(buf); | |
2943 | result |= memory_region_dispatch_write(mr, addr1, val, 4, | |
2944 | attrs); | |
2945 | break; | |
2946 | case 2: | |
2947 | /* 16 bit write access */ | |
2948 | val = lduw_p(buf); | |
2949 | result |= memory_region_dispatch_write(mr, addr1, val, 2, | |
2950 | attrs); | |
2951 | break; | |
2952 | case 1: | |
2953 | /* 8 bit write access */ | |
2954 | val = ldub_p(buf); | |
2955 | result |= memory_region_dispatch_write(mr, addr1, val, 1, | |
2956 | attrs); | |
2957 | break; | |
2958 | default: | |
2959 | abort(); | |
2960 | } | |
2961 | } else { | |
2962 | /* RAM case */ | |
2963 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | |
2964 | memcpy(ptr, buf, l); | |
2965 | invalidate_and_set_dirty(mr, addr1, l); | |
2966 | } | |
2967 | ||
2968 | if (release_lock) { | |
2969 | qemu_mutex_unlock_iothread(); | |
2970 | release_lock = false; | |
2971 | } | |
2972 | ||
2973 | len -= l; | |
2974 | buf += l; | |
2975 | addr += l; | |
2976 | ||
2977 | if (!len) { | |
2978 | break; | |
2979 | } | |
2980 | ||
2981 | l = len; | |
2982 | mr = flatview_translate(fv, addr, &addr1, &l, true); | |
2983 | } | |
2984 | ||
2985 | return result; | |
2986 | } | |
2987 | ||
2988 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | |
2989 | const uint8_t *buf, int len) | |
2990 | { | |
2991 | hwaddr l; | |
2992 | hwaddr addr1; | |
2993 | MemoryRegion *mr; | |
2994 | MemTxResult result = MEMTX_OK; | |
2995 | ||
2996 | if (len > 0) { | |
2997 | rcu_read_lock(); | |
2998 | l = len; | |
2999 | mr = flatview_translate(fv, addr, &addr1, &l, true); | |
3000 | result = flatview_write_continue(fv, addr, attrs, buf, len, | |
3001 | addr1, l, mr); | |
3002 | rcu_read_unlock(); | |
3003 | } | |
3004 | ||
3005 | return result; | |
3006 | } | |
3007 | ||
3008 | MemTxResult address_space_write(AddressSpace *as, hwaddr addr, | |
3009 | MemTxAttrs attrs, | |
3010 | const uint8_t *buf, int len) | |
3011 | { | |
3012 | return flatview_write(address_space_to_flatview(as), addr, attrs, buf, len); | |
3013 | } | |
3014 | ||
3015 | /* Called within RCU critical section. */ | |
3016 | MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, | |
3017 | MemTxAttrs attrs, uint8_t *buf, | |
3018 | int len, hwaddr addr1, hwaddr l, | |
3019 | MemoryRegion *mr) | |
3020 | { | |
3021 | uint8_t *ptr; | |
3022 | uint64_t val; | |
3023 | MemTxResult result = MEMTX_OK; | |
3024 | bool release_lock = false; | |
3025 | ||
3026 | for (;;) { | |
3027 | if (!memory_access_is_direct(mr, false)) { | |
3028 | /* I/O case */ | |
3029 | release_lock |= prepare_mmio_access(mr); | |
3030 | l = memory_access_size(mr, l, addr1); | |
3031 | switch (l) { | |
3032 | case 8: | |
3033 | /* 64 bit read access */ | |
3034 | result |= memory_region_dispatch_read(mr, addr1, &val, 8, | |
3035 | attrs); | |
3036 | stq_p(buf, val); | |
3037 | break; | |
3038 | case 4: | |
3039 | /* 32 bit read access */ | |
3040 | result |= memory_region_dispatch_read(mr, addr1, &val, 4, | |
3041 | attrs); | |
3042 | stl_p(buf, val); | |
3043 | break; | |
3044 | case 2: | |
3045 | /* 16 bit read access */ | |
3046 | result |= memory_region_dispatch_read(mr, addr1, &val, 2, | |
3047 | attrs); | |
3048 | stw_p(buf, val); | |
3049 | break; | |
3050 | case 1: | |
3051 | /* 8 bit read access */ | |
3052 | result |= memory_region_dispatch_read(mr, addr1, &val, 1, | |
3053 | attrs); | |
3054 | stb_p(buf, val); | |
3055 | break; | |
3056 | default: | |
3057 | abort(); | |
3058 | } | |
3059 | } else { | |
3060 | /* RAM case */ | |
3061 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | |
3062 | memcpy(buf, ptr, l); | |
3063 | } | |
3064 | ||
3065 | if (release_lock) { | |
3066 | qemu_mutex_unlock_iothread(); | |
3067 | release_lock = false; | |
3068 | } | |
3069 | ||
3070 | len -= l; | |
3071 | buf += l; | |
3072 | addr += l; | |
3073 | ||
3074 | if (!len) { | |
3075 | break; | |
3076 | } | |
3077 | ||
3078 | l = len; | |
3079 | mr = flatview_translate(fv, addr, &addr1, &l, false); | |
3080 | } | |
3081 | ||
3082 | return result; | |
3083 | } | |
3084 | ||
3085 | MemTxResult flatview_read_full(FlatView *fv, hwaddr addr, | |
3086 | MemTxAttrs attrs, uint8_t *buf, int len) | |
3087 | { | |
3088 | hwaddr l; | |
3089 | hwaddr addr1; | |
3090 | MemoryRegion *mr; | |
3091 | MemTxResult result = MEMTX_OK; | |
3092 | ||
3093 | if (len > 0) { | |
3094 | rcu_read_lock(); | |
3095 | l = len; | |
3096 | mr = flatview_translate(fv, addr, &addr1, &l, false); | |
3097 | result = flatview_read_continue(fv, addr, attrs, buf, len, | |
3098 | addr1, l, mr); | |
3099 | rcu_read_unlock(); | |
3100 | } | |
3101 | ||
3102 | return result; | |
3103 | } | |
3104 | ||
3105 | static MemTxResult flatview_rw(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | |
3106 | uint8_t *buf, int len, bool is_write) | |
3107 | { | |
3108 | if (is_write) { | |
3109 | return flatview_write(fv, addr, attrs, (uint8_t *)buf, len); | |
3110 | } else { | |
3111 | return flatview_read(fv, addr, attrs, (uint8_t *)buf, len); | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, | |
3116 | MemTxAttrs attrs, uint8_t *buf, | |
3117 | int len, bool is_write) | |
3118 | { | |
3119 | return flatview_rw(address_space_to_flatview(as), | |
3120 | addr, attrs, buf, len, is_write); | |
3121 | } | |
3122 | ||
3123 | void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, | |
3124 | int len, int is_write) | |
3125 | { | |
3126 | address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, | |
3127 | buf, len, is_write); | |
3128 | } | |
3129 | ||
3130 | enum write_rom_type { | |
3131 | WRITE_DATA, | |
3132 | FLUSH_CACHE, | |
3133 | }; | |
3134 | ||
3135 | static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, | |
3136 | hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type) | |
3137 | { | |
3138 | hwaddr l; | |
3139 | uint8_t *ptr; | |
3140 | hwaddr addr1; | |
3141 | MemoryRegion *mr; | |
3142 | ||
3143 | rcu_read_lock(); | |
3144 | while (len > 0) { | |
3145 | l = len; | |
3146 | mr = address_space_translate(as, addr, &addr1, &l, true); | |
3147 | ||
3148 | if (!(memory_region_is_ram(mr) || | |
3149 | memory_region_is_romd(mr))) { | |
3150 | l = memory_access_size(mr, l, addr1); | |
3151 | } else { | |
3152 | /* ROM/RAM case */ | |
3153 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); | |
3154 | switch (type) { | |
3155 | case WRITE_DATA: | |
3156 | memcpy(ptr, buf, l); | |
3157 | invalidate_and_set_dirty(mr, addr1, l); | |
3158 | break; | |
3159 | case FLUSH_CACHE: | |
3160 | flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); | |
3161 | break; | |
3162 | } | |
3163 | } | |
3164 | len -= l; | |
3165 | buf += l; | |
3166 | addr += l; | |
3167 | } | |
3168 | rcu_read_unlock(); | |
3169 | } | |
3170 | ||
3171 | /* used for ROM loading : can write in RAM and ROM */ | |
3172 | void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, | |
3173 | const uint8_t *buf, int len) | |
3174 | { | |
3175 | cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA); | |
3176 | } | |
3177 | ||
3178 | void cpu_flush_icache_range(hwaddr start, int len) | |
3179 | { | |
3180 | /* | |
3181 | * This function should do the same thing as an icache flush that was | |
3182 | * triggered from within the guest. For TCG we are always cache coherent, | |
3183 | * so there is no need to flush anything. For KVM / Xen we need to flush | |
3184 | * the host's instruction cache at least. | |
3185 | */ | |
3186 | if (tcg_enabled()) { | |
3187 | return; | |
3188 | } | |
3189 | ||
3190 | cpu_physical_memory_write_rom_internal(&address_space_memory, | |
3191 | start, NULL, len, FLUSH_CACHE); | |
3192 | } | |
3193 | ||
3194 | typedef struct { | |
3195 | MemoryRegion *mr; | |
3196 | void *buffer; | |
3197 | hwaddr addr; | |
3198 | hwaddr len; | |
3199 | bool in_use; | |
3200 | } BounceBuffer; | |
3201 | ||
3202 | static BounceBuffer bounce; | |
3203 | ||
3204 | typedef struct MapClient { | |
3205 | QEMUBH *bh; | |
3206 | QLIST_ENTRY(MapClient) link; | |
3207 | } MapClient; | |
3208 | ||
3209 | QemuMutex map_client_list_lock; | |
3210 | static QLIST_HEAD(map_client_list, MapClient) map_client_list | |
3211 | = QLIST_HEAD_INITIALIZER(map_client_list); | |
3212 | ||
3213 | static void cpu_unregister_map_client_do(MapClient *client) | |
3214 | { | |
3215 | QLIST_REMOVE(client, link); | |
3216 | g_free(client); | |
3217 | } | |
3218 | ||
3219 | static void cpu_notify_map_clients_locked(void) | |
3220 | { | |
3221 | MapClient *client; | |
3222 | ||
3223 | while (!QLIST_EMPTY(&map_client_list)) { | |
3224 | client = QLIST_FIRST(&map_client_list); | |
3225 | qemu_bh_schedule(client->bh); | |
3226 | cpu_unregister_map_client_do(client); | |
3227 | } | |
3228 | } | |
3229 | ||
3230 | void cpu_register_map_client(QEMUBH *bh) | |
3231 | { | |
3232 | MapClient *client = g_malloc(sizeof(*client)); | |
3233 | ||
3234 | qemu_mutex_lock(&map_client_list_lock); | |
3235 | client->bh = bh; | |
3236 | QLIST_INSERT_HEAD(&map_client_list, client, link); | |
3237 | if (!atomic_read(&bounce.in_use)) { | |
3238 | cpu_notify_map_clients_locked(); | |
3239 | } | |
3240 | qemu_mutex_unlock(&map_client_list_lock); | |
3241 | } | |
3242 | ||
3243 | void cpu_exec_init_all(void) | |
3244 | { | |
3245 | qemu_mutex_init(&ram_list.mutex); | |
3246 | /* The data structures we set up here depend on knowing the page size, | |
3247 | * so no more changes can be made after this point. | |
3248 | * In an ideal world, nothing we did before we had finished the | |
3249 | * machine setup would care about the target page size, and we could | |
3250 | * do this much later, rather than requiring board models to state | |
3251 | * up front what their requirements are. | |
3252 | */ | |
3253 | finalize_target_page_bits(); | |
3254 | io_mem_init(); | |
3255 | memory_map_init(); | |
3256 | qemu_mutex_init(&map_client_list_lock); | |
3257 | } | |
3258 | ||
3259 | void cpu_unregister_map_client(QEMUBH *bh) | |
3260 | { | |
3261 | MapClient *client; | |
3262 | ||
3263 | qemu_mutex_lock(&map_client_list_lock); | |
3264 | QLIST_FOREACH(client, &map_client_list, link) { | |
3265 | if (client->bh == bh) { | |
3266 | cpu_unregister_map_client_do(client); | |
3267 | break; | |
3268 | } | |
3269 | } | |
3270 | qemu_mutex_unlock(&map_client_list_lock); | |
3271 | } | |
3272 | ||
3273 | static void cpu_notify_map_clients(void) | |
3274 | { | |
3275 | qemu_mutex_lock(&map_client_list_lock); | |
3276 | cpu_notify_map_clients_locked(); | |
3277 | qemu_mutex_unlock(&map_client_list_lock); | |
3278 | } | |
3279 | ||
3280 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | |
3281 | bool is_write) | |
3282 | { | |
3283 | MemoryRegion *mr; | |
3284 | hwaddr l, xlat; | |
3285 | ||
3286 | rcu_read_lock(); | |
3287 | while (len > 0) { | |
3288 | l = len; | |
3289 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); | |
3290 | if (!memory_access_is_direct(mr, is_write)) { | |
3291 | l = memory_access_size(mr, l, addr); | |
3292 | if (!memory_region_access_valid(mr, xlat, l, is_write)) { | |
3293 | rcu_read_unlock(); | |
3294 | return false; | |
3295 | } | |
3296 | } | |
3297 | ||
3298 | len -= l; | |
3299 | addr += l; | |
3300 | } | |
3301 | rcu_read_unlock(); | |
3302 | return true; | |
3303 | } | |
3304 | ||
3305 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, | |
3306 | int len, bool is_write) | |
3307 | { | |
3308 | return flatview_access_valid(address_space_to_flatview(as), | |
3309 | addr, len, is_write); | |
3310 | } | |
3311 | ||
3312 | static hwaddr | |
3313 | flatview_extend_translation(FlatView *fv, hwaddr addr, | |
3314 | hwaddr target_len, | |
3315 | MemoryRegion *mr, hwaddr base, hwaddr len, | |
3316 | bool is_write) | |
3317 | { | |
3318 | hwaddr done = 0; | |
3319 | hwaddr xlat; | |
3320 | MemoryRegion *this_mr; | |
3321 | ||
3322 | for (;;) { | |
3323 | target_len -= len; | |
3324 | addr += len; | |
3325 | done += len; | |
3326 | if (target_len == 0) { | |
3327 | return done; | |
3328 | } | |
3329 | ||
3330 | len = target_len; | |
3331 | this_mr = flatview_translate(fv, addr, &xlat, | |
3332 | &len, is_write); | |
3333 | if (this_mr != mr || xlat != base + done) { | |
3334 | return done; | |
3335 | } | |
3336 | } | |
3337 | } | |
3338 | ||
3339 | /* Map a physical memory region into a host virtual address. | |
3340 | * May map a subset of the requested range, given by and returned in *plen. | |
3341 | * May return NULL if resources needed to perform the mapping are exhausted. | |
3342 | * Use only for reads OR writes - not for read-modify-write operations. | |
3343 | * Use cpu_register_map_client() to know when retrying the map operation is | |
3344 | * likely to succeed. | |
3345 | */ | |
3346 | void *address_space_map(AddressSpace *as, | |
3347 | hwaddr addr, | |
3348 | hwaddr *plen, | |
3349 | bool is_write) | |
3350 | { | |
3351 | hwaddr len = *plen; | |
3352 | hwaddr l, xlat; | |
3353 | MemoryRegion *mr; | |
3354 | void *ptr; | |
3355 | FlatView *fv = address_space_to_flatview(as); | |
3356 | ||
3357 | if (len == 0) { | |
3358 | return NULL; | |
3359 | } | |
3360 | ||
3361 | l = len; | |
3362 | rcu_read_lock(); | |
3363 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); | |
3364 | ||
3365 | if (!memory_access_is_direct(mr, is_write)) { | |
3366 | if (atomic_xchg(&bounce.in_use, true)) { | |
3367 | rcu_read_unlock(); | |
3368 | return NULL; | |
3369 | } | |
3370 | /* Avoid unbounded allocations */ | |
3371 | l = MIN(l, TARGET_PAGE_SIZE); | |
3372 | bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l); | |
3373 | bounce.addr = addr; | |
3374 | bounce.len = l; | |
3375 | ||
3376 | memory_region_ref(mr); | |
3377 | bounce.mr = mr; | |
3378 | if (!is_write) { | |
3379 | flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED, | |
3380 | bounce.buffer, l); | |
3381 | } | |
3382 | ||
3383 | rcu_read_unlock(); | |
3384 | *plen = l; | |
3385 | return bounce.buffer; | |
3386 | } | |
3387 | ||
3388 | ||
3389 | memory_region_ref(mr); | |
3390 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, | |
3391 | l, is_write); | |
3392 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); | |
3393 | rcu_read_unlock(); | |
3394 | ||
3395 | return ptr; | |
3396 | } | |
3397 | ||
3398 | /* Unmaps a memory region previously mapped by address_space_map(). | |
3399 | * Will also mark the memory as dirty if is_write == 1. access_len gives | |
3400 | * the amount of memory that was actually read or written by the caller. | |
3401 | */ | |
3402 | void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, | |
3403 | int is_write, hwaddr access_len) | |
3404 | { | |
3405 | if (buffer != bounce.buffer) { | |
3406 | MemoryRegion *mr; | |
3407 | ram_addr_t addr1; | |
3408 | ||
3409 | mr = memory_region_from_host(buffer, &addr1); | |
3410 | assert(mr != NULL); | |
3411 | if (is_write) { | |
3412 | invalidate_and_set_dirty(mr, addr1, access_len); | |
3413 | } | |
3414 | if (xen_enabled()) { | |
3415 | xen_invalidate_map_cache_entry(buffer); | |
3416 | } | |
3417 | memory_region_unref(mr); | |
3418 | return; | |
3419 | } | |
3420 | if (is_write) { | |
3421 | address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED, | |
3422 | bounce.buffer, access_len); | |
3423 | } | |
3424 | qemu_vfree(bounce.buffer); | |
3425 | bounce.buffer = NULL; | |
3426 | memory_region_unref(bounce.mr); | |
3427 | atomic_mb_set(&bounce.in_use, false); | |
3428 | cpu_notify_map_clients(); | |
3429 | } | |
3430 | ||
3431 | void *cpu_physical_memory_map(hwaddr addr, | |
3432 | hwaddr *plen, | |
3433 | int is_write) | |
3434 | { | |
3435 | return address_space_map(&address_space_memory, addr, plen, is_write); | |
3436 | } | |
3437 | ||
3438 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, | |
3439 | int is_write, hwaddr access_len) | |
3440 | { | |
3441 | return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); | |
3442 | } | |
3443 | ||
3444 | #define ARG1_DECL AddressSpace *as | |
3445 | #define ARG1 as | |
3446 | #define SUFFIX | |
3447 | #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__) | |
3448 | #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write) | |
3449 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) | |
3450 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3451 | #define RCU_READ_LOCK(...) rcu_read_lock() | |
3452 | #define RCU_READ_UNLOCK(...) rcu_read_unlock() | |
3453 | #include "memory_ldst.inc.c" | |
3454 | ||
3455 | int64_t address_space_cache_init(MemoryRegionCache *cache, | |
3456 | AddressSpace *as, | |
3457 | hwaddr addr, | |
3458 | hwaddr len, | |
3459 | bool is_write) | |
3460 | { | |
3461 | cache->len = len; | |
3462 | cache->as = as; | |
3463 | cache->xlat = addr; | |
3464 | return len; | |
3465 | } | |
3466 | ||
3467 | void address_space_cache_invalidate(MemoryRegionCache *cache, | |
3468 | hwaddr addr, | |
3469 | hwaddr access_len) | |
3470 | { | |
3471 | } | |
3472 | ||
3473 | void address_space_cache_destroy(MemoryRegionCache *cache) | |
3474 | { | |
3475 | cache->as = NULL; | |
3476 | } | |
3477 | ||
3478 | #define ARG1_DECL MemoryRegionCache *cache | |
3479 | #define ARG1 cache | |
3480 | #define SUFFIX _cached | |
3481 | #define TRANSLATE(addr, ...) \ | |
3482 | address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__) | |
3483 | #define IS_DIRECT(mr, is_write) true | |
3484 | #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs) | |
3485 | #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len) | |
3486 | #define RCU_READ_LOCK() rcu_read_lock() | |
3487 | #define RCU_READ_UNLOCK() rcu_read_unlock() | |
3488 | #include "memory_ldst.inc.c" | |
3489 | ||
3490 | /* virtual memory access for debug (includes writing to ROM) */ | |
3491 | int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, | |
3492 | uint8_t *buf, int len, int is_write) | |
3493 | { | |
3494 | int l; | |
3495 | hwaddr phys_addr; | |
3496 | target_ulong page; | |
3497 | ||
3498 | cpu_synchronize_state(cpu); | |
3499 | while (len > 0) { | |
3500 | int asidx; | |
3501 | MemTxAttrs attrs; | |
3502 | ||
3503 | page = addr & TARGET_PAGE_MASK; | |
3504 | phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs); | |
3505 | asidx = cpu_asidx_from_attrs(cpu, attrs); | |
3506 | /* if no physical page mapped, return an error */ | |
3507 | if (phys_addr == -1) | |
3508 | return -1; | |
3509 | l = (page + TARGET_PAGE_SIZE) - addr; | |
3510 | if (l > len) | |
3511 | l = len; | |
3512 | phys_addr += (addr & ~TARGET_PAGE_MASK); | |
3513 | if (is_write) { | |
3514 | cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, | |
3515 | phys_addr, buf, l); | |
3516 | } else { | |
3517 | address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, | |
3518 | MEMTXATTRS_UNSPECIFIED, | |
3519 | buf, l, 0); | |
3520 | } | |
3521 | len -= l; | |
3522 | buf += l; | |
3523 | addr += l; | |
3524 | } | |
3525 | return 0; | |
3526 | } | |
3527 | ||
3528 | /* | |
3529 | * Allows code that needs to deal with migration bitmaps etc to still be built | |
3530 | * target independent. | |
3531 | */ | |
3532 | size_t qemu_target_page_size(void) | |
3533 | { | |
3534 | return TARGET_PAGE_SIZE; | |
3535 | } | |
3536 | ||
3537 | int qemu_target_page_bits(void) | |
3538 | { | |
3539 | return TARGET_PAGE_BITS; | |
3540 | } | |
3541 | ||
3542 | int qemu_target_page_bits_min(void) | |
3543 | { | |
3544 | return TARGET_PAGE_BITS_MIN; | |
3545 | } | |
3546 | #endif | |
3547 | ||
3548 | /* | |
3549 | * A helper function for the _utterly broken_ virtio device model to find out if | |
3550 | * it's running on a big endian machine. Don't do this at home kids! | |
3551 | */ | |
3552 | bool target_words_bigendian(void); | |
3553 | bool target_words_bigendian(void) | |
3554 | { | |
3555 | #if defined(TARGET_WORDS_BIGENDIAN) | |
3556 | return true; | |
3557 | #else | |
3558 | return false; | |
3559 | #endif | |
3560 | } | |
3561 | ||
3562 | #ifndef CONFIG_USER_ONLY | |
3563 | bool cpu_physical_memory_is_io(hwaddr phys_addr) | |
3564 | { | |
3565 | MemoryRegion*mr; | |
3566 | hwaddr l = 1; | |
3567 | bool res; | |
3568 | ||
3569 | rcu_read_lock(); | |
3570 | mr = address_space_translate(&address_space_memory, | |
3571 | phys_addr, &phys_addr, &l, false); | |
3572 | ||
3573 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); | |
3574 | rcu_read_unlock(); | |
3575 | return res; | |
3576 | } | |
3577 | ||
3578 | int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque) | |
3579 | { | |
3580 | RAMBlock *block; | |
3581 | int ret = 0; | |
3582 | ||
3583 | rcu_read_lock(); | |
3584 | RAMBLOCK_FOREACH(block) { | |
3585 | ret = func(block->idstr, block->host, block->offset, | |
3586 | block->used_length, opaque); | |
3587 | if (ret) { | |
3588 | break; | |
3589 | } | |
3590 | } | |
3591 | rcu_read_unlock(); | |
3592 | return ret; | |
3593 | } | |
3594 | ||
3595 | /* | |
3596 | * Unmap pages of memory from start to start+length such that | |
3597 | * they a) read as 0, b) Trigger whatever fault mechanism | |
3598 | * the OS provides for postcopy. | |
3599 | * The pages must be unmapped by the end of the function. | |
3600 | * Returns: 0 on success, none-0 on failure | |
3601 | * | |
3602 | */ | |
3603 | int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length) | |
3604 | { | |
3605 | int ret = -1; | |
3606 | ||
3607 | uint8_t *host_startaddr = rb->host + start; | |
3608 | ||
3609 | if ((uintptr_t)host_startaddr & (rb->page_size - 1)) { | |
3610 | error_report("ram_block_discard_range: Unaligned start address: %p", | |
3611 | host_startaddr); | |
3612 | goto err; | |
3613 | } | |
3614 | ||
3615 | if ((start + length) <= rb->used_length) { | |
3616 | uint8_t *host_endaddr = host_startaddr + length; | |
3617 | if ((uintptr_t)host_endaddr & (rb->page_size - 1)) { | |
3618 | error_report("ram_block_discard_range: Unaligned end address: %p", | |
3619 | host_endaddr); | |
3620 | goto err; | |
3621 | } | |
3622 | ||
3623 | errno = ENOTSUP; /* If we are missing MADVISE etc */ | |
3624 | ||
3625 | if (rb->page_size == qemu_host_page_size) { | |
3626 | #if defined(CONFIG_MADVISE) | |
3627 | /* Note: We need the madvise MADV_DONTNEED behaviour of definitely | |
3628 | * freeing the page. | |
3629 | */ | |
3630 | ret = madvise(host_startaddr, length, MADV_DONTNEED); | |
3631 | #endif | |
3632 | } else { | |
3633 | /* Huge page case - unfortunately it can't do DONTNEED, but | |
3634 | * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the | |
3635 | * huge page file. | |
3636 | */ | |
3637 | #ifdef CONFIG_FALLOCATE_PUNCH_HOLE | |
3638 | ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, | |
3639 | start, length); | |
3640 | #endif | |
3641 | } | |
3642 | if (ret) { | |
3643 | ret = -errno; | |
3644 | error_report("ram_block_discard_range: Failed to discard range " | |
3645 | "%s:%" PRIx64 " +%zx (%d)", | |
3646 | rb->idstr, start, length, ret); | |
3647 | } | |
3648 | } else { | |
3649 | error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64 | |
3650 | "/%zx/" RAM_ADDR_FMT")", | |
3651 | rb->idstr, start, length, rb->used_length); | |
3652 | } | |
3653 | ||
3654 | err: | |
3655 | return ret; | |
3656 | } | |
3657 | ||
3658 | #endif | |
3659 | ||
3660 | void page_size_init(void) | |
3661 | { | |
3662 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
3663 | TARGET_PAGE_SIZE */ | |
3664 | if (qemu_host_page_size == 0) { | |
3665 | qemu_host_page_size = qemu_real_host_page_size; | |
3666 | } | |
3667 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
3668 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
3669 | } | |
3670 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; | |
3671 | } | |
3672 | ||
3673 | #if !defined(CONFIG_USER_ONLY) | |
3674 | ||
3675 | static void mtree_print_phys_entries(fprintf_function mon, void *f, | |
3676 | int start, int end, int skip, int ptr) | |
3677 | { | |
3678 | if (start == end - 1) { | |
3679 | mon(f, "\t%3d ", start); | |
3680 | } else { | |
3681 | mon(f, "\t%3d..%-3d ", start, end - 1); | |
3682 | } | |
3683 | mon(f, " skip=%d ", skip); | |
3684 | if (ptr == PHYS_MAP_NODE_NIL) { | |
3685 | mon(f, " ptr=NIL"); | |
3686 | } else if (!skip) { | |
3687 | mon(f, " ptr=#%d", ptr); | |
3688 | } else { | |
3689 | mon(f, " ptr=[%d]", ptr); | |
3690 | } | |
3691 | mon(f, "\n"); | |
3692 | } | |
3693 | ||
3694 | #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \ | |
3695 | int128_sub((size), int128_one())) : 0) | |
3696 | ||
3697 | void mtree_print_dispatch(fprintf_function mon, void *f, | |
3698 | AddressSpaceDispatch *d, MemoryRegion *root) | |
3699 | { | |
3700 | int i; | |
3701 | ||
3702 | mon(f, " Dispatch\n"); | |
3703 | mon(f, " Physical sections\n"); | |
3704 | ||
3705 | for (i = 0; i < d->map.sections_nb; ++i) { | |
3706 | MemoryRegionSection *s = d->map.sections + i; | |
3707 | const char *names[] = { " [unassigned]", " [not dirty]", | |
3708 | " [ROM]", " [watch]" }; | |
3709 | ||
3710 | mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s", | |
3711 | i, | |
3712 | s->offset_within_address_space, | |
3713 | s->offset_within_address_space + MR_SIZE(s->mr->size), | |
3714 | s->mr->name ? s->mr->name : "(noname)", | |
3715 | i < ARRAY_SIZE(names) ? names[i] : "", | |
3716 | s->mr == root ? " [ROOT]" : "", | |
3717 | s == d->mru_section ? " [MRU]" : "", | |
3718 | s->mr->is_iommu ? " [iommu]" : ""); | |
3719 | ||
3720 | if (s->mr->alias) { | |
3721 | mon(f, " alias=%s", s->mr->alias->name ? | |
3722 | s->mr->alias->name : "noname"); | |
3723 | } | |
3724 | mon(f, "\n"); | |
3725 | } | |
3726 | ||
3727 | mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n", | |
3728 | P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip); | |
3729 | for (i = 0; i < d->map.nodes_nb; ++i) { | |
3730 | int j, jprev; | |
3731 | PhysPageEntry prev; | |
3732 | Node *n = d->map.nodes + i; | |
3733 | ||
3734 | mon(f, " [%d]\n", i); | |
3735 | ||
3736 | for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) { | |
3737 | PhysPageEntry *pe = *n + j; | |
3738 | ||
3739 | if (pe->ptr == prev.ptr && pe->skip == prev.skip) { | |
3740 | continue; | |
3741 | } | |
3742 | ||
3743 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3744 | ||
3745 | jprev = j; | |
3746 | prev = *pe; | |
3747 | } | |
3748 | ||
3749 | if (jprev != ARRAY_SIZE(*n)) { | |
3750 | mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr); | |
3751 | } | |
3752 | } | |
3753 | } | |
3754 | ||
3755 | #endif |