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1 | /* Subroutines for insn-output.c for Tensilica's Xtensa architecture. | |
2 | Copyright (C) 2001-2017 Free Software Foundation, Inc. | |
3 | Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. | |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | #include "system.h" | |
23 | #include "coretypes.h" | |
24 | #include "backend.h" | |
25 | #include "target.h" | |
26 | #include "rtl.h" | |
27 | #include "tree.h" | |
28 | #include "gimple.h" | |
29 | #include "cfghooks.h" | |
30 | #include "df.h" | |
31 | #include "memmodel.h" | |
32 | #include "tm_p.h" | |
33 | #include "stringpool.h" | |
34 | #include "attribs.h" | |
35 | #include "optabs.h" | |
36 | #include "regs.h" | |
37 | #include "emit-rtl.h" | |
38 | #include "recog.h" | |
39 | #include "diagnostic-core.h" | |
40 | #include "cfgrtl.h" | |
41 | #include "output.h" | |
42 | #include "fold-const.h" | |
43 | #include "stor-layout.h" | |
44 | #include "calls.h" | |
45 | #include "varasm.h" | |
46 | #include "alias.h" | |
47 | #include "explow.h" | |
48 | #include "expr.h" | |
49 | #include "reload.h" | |
50 | #include "langhooks.h" | |
51 | #include "gimplify.h" | |
52 | #include "builtins.h" | |
53 | #include "dumpfile.h" | |
54 | #include "hw-doloop.h" | |
55 | #include "rtl-iter.h" | |
56 | ||
57 | /* This file should be included last. */ | |
58 | #include "target-def.h" | |
59 | ||
60 | /* Enumeration for all of the relational tests, so that we can build | |
61 | arrays indexed by the test type, and not worry about the order | |
62 | of EQ, NE, etc. */ | |
63 | ||
64 | enum internal_test | |
65 | { | |
66 | ITEST_EQ, | |
67 | ITEST_NE, | |
68 | ITEST_GT, | |
69 | ITEST_GE, | |
70 | ITEST_LT, | |
71 | ITEST_LE, | |
72 | ITEST_GTU, | |
73 | ITEST_GEU, | |
74 | ITEST_LTU, | |
75 | ITEST_LEU, | |
76 | ITEST_MAX | |
77 | }; | |
78 | ||
79 | /* Array giving truth value on whether or not a given hard register | |
80 | can support a given mode. */ | |
81 | static char xtensa_hard_regno_mode_ok_p | |
82 | [(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
83 | ||
84 | /* Largest block move to handle in-line. */ | |
85 | #define LARGEST_MOVE_RATIO 15 | |
86 | ||
87 | /* Define the structure for the machine field in struct function. */ | |
88 | struct GTY(()) machine_function | |
89 | { | |
90 | int accesses_prev_frame; | |
91 | bool need_a7_copy; | |
92 | bool vararg_a7; | |
93 | rtx vararg_a7_copy; | |
94 | rtx_insn *set_frame_ptr_insn; | |
95 | /* Current frame size calculated by compute_frame_size. */ | |
96 | unsigned current_frame_size; | |
97 | /* Callee-save area size in the current frame calculated by | |
98 | compute_frame_size. */ | |
99 | int callee_save_size; | |
100 | bool frame_laid_out; | |
101 | bool epilogue_done; | |
102 | }; | |
103 | ||
104 | /* Vector, indexed by hard register number, which contains 1 for a | |
105 | register that is allowable in a candidate for leaf function | |
106 | treatment. */ | |
107 | ||
108 | const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] = | |
109 | { | |
110 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
111 | 1, 1, 1, | |
112 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
113 | 1 | |
114 | }; | |
115 | ||
116 | static void xtensa_option_override (void); | |
117 | static enum internal_test map_test_to_internal_test (enum rtx_code); | |
118 | static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *); | |
119 | static rtx gen_float_relational (enum rtx_code, rtx, rtx); | |
120 | static rtx gen_conditional_move (enum rtx_code, machine_mode, rtx, rtx); | |
121 | static rtx fixup_subreg_mem (rtx); | |
122 | static struct machine_function * xtensa_init_machine_status (void); | |
123 | static rtx xtensa_legitimize_tls_address (rtx); | |
124 | static rtx xtensa_legitimize_address (rtx, rtx, machine_mode); | |
125 | static bool xtensa_mode_dependent_address_p (const_rtx, addr_space_t); | |
126 | static bool xtensa_return_in_msb (const_tree); | |
127 | static void printx (FILE *, signed int); | |
128 | static rtx xtensa_builtin_saveregs (void); | |
129 | static bool xtensa_legitimate_address_p (machine_mode, rtx, bool); | |
130 | static unsigned int xtensa_multibss_section_type_flags (tree, const char *, | |
131 | int) ATTRIBUTE_UNUSED; | |
132 | static section *xtensa_select_rtx_section (machine_mode, rtx, | |
133 | unsigned HOST_WIDE_INT); | |
134 | static bool xtensa_rtx_costs (rtx, machine_mode, int, int, int *, bool); | |
135 | static int xtensa_register_move_cost (machine_mode, reg_class_t, | |
136 | reg_class_t); | |
137 | static int xtensa_memory_move_cost (machine_mode, reg_class_t, bool); | |
138 | static tree xtensa_build_builtin_va_list (void); | |
139 | static bool xtensa_return_in_memory (const_tree, const_tree); | |
140 | static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *, | |
141 | gimple_seq *); | |
142 | static void xtensa_function_arg_advance (cumulative_args_t, machine_mode, | |
143 | const_tree, bool); | |
144 | static rtx xtensa_function_arg (cumulative_args_t, machine_mode, | |
145 | const_tree, bool); | |
146 | static rtx xtensa_function_incoming_arg (cumulative_args_t, | |
147 | machine_mode, const_tree, bool); | |
148 | static rtx xtensa_function_value (const_tree, const_tree, bool); | |
149 | static rtx xtensa_libcall_value (machine_mode, const_rtx); | |
150 | static bool xtensa_function_value_regno_p (const unsigned int); | |
151 | static unsigned int xtensa_function_arg_boundary (machine_mode, | |
152 | const_tree); | |
153 | static void xtensa_init_builtins (void); | |
154 | static tree xtensa_fold_builtin (tree, int, tree *, bool); | |
155 | static rtx xtensa_expand_builtin (tree, rtx, rtx, machine_mode, int); | |
156 | static void xtensa_va_start (tree, rtx); | |
157 | static bool xtensa_frame_pointer_required (void); | |
158 | static rtx xtensa_static_chain (const_tree, bool); | |
159 | static void xtensa_asm_trampoline_template (FILE *); | |
160 | static void xtensa_trampoline_init (rtx, tree, rtx); | |
161 | static bool xtensa_output_addr_const_extra (FILE *, rtx); | |
162 | static bool xtensa_cannot_force_const_mem (machine_mode, rtx); | |
163 | ||
164 | static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t); | |
165 | static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t); | |
166 | static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t, | |
167 | machine_mode, | |
168 | struct secondary_reload_info *); | |
169 | ||
170 | static bool constantpool_address_p (const_rtx addr); | |
171 | static bool xtensa_legitimate_constant_p (machine_mode, rtx); | |
172 | static void xtensa_reorg (void); | |
173 | static bool xtensa_can_use_doloop_p (const widest_int &, const widest_int &, | |
174 | unsigned int, bool); | |
175 | static const char *xtensa_invalid_within_doloop (const rtx_insn *); | |
176 | ||
177 | static bool xtensa_member_type_forces_blk (const_tree, | |
178 | machine_mode mode); | |
179 | ||
180 | static void xtensa_conditional_register_usage (void); | |
181 | static unsigned int xtensa_hard_regno_nregs (unsigned int, machine_mode); | |
182 | static bool xtensa_hard_regno_mode_ok (unsigned int, machine_mode); | |
183 | static bool xtensa_modes_tieable_p (machine_mode, machine_mode); | |
184 | static HOST_WIDE_INT xtensa_constant_alignment (const_tree, HOST_WIDE_INT); | |
185 | static HOST_WIDE_INT xtensa_starting_frame_offset (void); | |
186 | static unsigned HOST_WIDE_INT xtensa_asan_shadow_offset (void); | |
187 | ||
188 | \f | |
189 | ||
190 | /* These hooks specify assembly directives for creating certain kinds | |
191 | of integer object. */ | |
192 | ||
193 | #undef TARGET_ASM_ALIGNED_SI_OP | |
194 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
195 | ||
196 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
197 | #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section | |
198 | ||
199 | #undef TARGET_LEGITIMIZE_ADDRESS | |
200 | #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address | |
201 | #undef TARGET_MODE_DEPENDENT_ADDRESS_P | |
202 | #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p | |
203 | ||
204 | #undef TARGET_REGISTER_MOVE_COST | |
205 | #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost | |
206 | #undef TARGET_MEMORY_MOVE_COST | |
207 | #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost | |
208 | #undef TARGET_RTX_COSTS | |
209 | #define TARGET_RTX_COSTS xtensa_rtx_costs | |
210 | #undef TARGET_ADDRESS_COST | |
211 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 | |
212 | ||
213 | #undef TARGET_MEMBER_TYPE_FORCES_BLK | |
214 | #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk | |
215 | ||
216 | #undef TARGET_BUILD_BUILTIN_VA_LIST | |
217 | #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list | |
218 | ||
219 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
220 | #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start | |
221 | ||
222 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
223 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
224 | #undef TARGET_PROMOTE_PROTOTYPES | |
225 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
226 | ||
227 | #undef TARGET_RETURN_IN_MEMORY | |
228 | #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory | |
229 | #undef TARGET_FUNCTION_VALUE | |
230 | #define TARGET_FUNCTION_VALUE xtensa_function_value | |
231 | #undef TARGET_LIBCALL_VALUE | |
232 | #define TARGET_LIBCALL_VALUE xtensa_libcall_value | |
233 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
234 | #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p | |
235 | ||
236 | #undef TARGET_SPLIT_COMPLEX_ARG | |
237 | #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true | |
238 | #undef TARGET_MUST_PASS_IN_STACK | |
239 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
240 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
241 | #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance | |
242 | #undef TARGET_FUNCTION_ARG | |
243 | #define TARGET_FUNCTION_ARG xtensa_function_arg | |
244 | #undef TARGET_FUNCTION_INCOMING_ARG | |
245 | #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg | |
246 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
247 | #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary | |
248 | ||
249 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
250 | #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs | |
251 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
252 | #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr | |
253 | ||
254 | #undef TARGET_RETURN_IN_MSB | |
255 | #define TARGET_RETURN_IN_MSB xtensa_return_in_msb | |
256 | ||
257 | #undef TARGET_INIT_BUILTINS | |
258 | #define TARGET_INIT_BUILTINS xtensa_init_builtins | |
259 | #undef TARGET_FOLD_BUILTIN | |
260 | #define TARGET_FOLD_BUILTIN xtensa_fold_builtin | |
261 | #undef TARGET_EXPAND_BUILTIN | |
262 | #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin | |
263 | ||
264 | #undef TARGET_PREFERRED_RELOAD_CLASS | |
265 | #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class | |
266 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
267 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class | |
268 | ||
269 | #undef TARGET_SECONDARY_RELOAD | |
270 | #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload | |
271 | ||
272 | #undef TARGET_HAVE_TLS | |
273 | #define TARGET_HAVE_TLS (TARGET_THREADPTR && HAVE_AS_TLS) | |
274 | ||
275 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
276 | #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem | |
277 | ||
278 | #undef TARGET_LRA_P | |
279 | #define TARGET_LRA_P hook_bool_void_false | |
280 | ||
281 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
282 | #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p | |
283 | ||
284 | #undef TARGET_FRAME_POINTER_REQUIRED | |
285 | #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required | |
286 | ||
287 | #undef TARGET_STATIC_CHAIN | |
288 | #define TARGET_STATIC_CHAIN xtensa_static_chain | |
289 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
290 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template | |
291 | #undef TARGET_TRAMPOLINE_INIT | |
292 | #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init | |
293 | ||
294 | #undef TARGET_OPTION_OVERRIDE | |
295 | #define TARGET_OPTION_OVERRIDE xtensa_option_override | |
296 | ||
297 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA | |
298 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra | |
299 | ||
300 | #undef TARGET_LEGITIMATE_CONSTANT_P | |
301 | #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p | |
302 | ||
303 | #undef TARGET_MACHINE_DEPENDENT_REORG | |
304 | #define TARGET_MACHINE_DEPENDENT_REORG xtensa_reorg | |
305 | ||
306 | #undef TARGET_CAN_USE_DOLOOP_P | |
307 | #define TARGET_CAN_USE_DOLOOP_P xtensa_can_use_doloop_p | |
308 | ||
309 | #undef TARGET_INVALID_WITHIN_DOLOOP | |
310 | #define TARGET_INVALID_WITHIN_DOLOOP xtensa_invalid_within_doloop | |
311 | ||
312 | #undef TARGET_CONDITIONAL_REGISTER_USAGE | |
313 | #define TARGET_CONDITIONAL_REGISTER_USAGE xtensa_conditional_register_usage | |
314 | ||
315 | #undef TARGET_HARD_REGNO_NREGS | |
316 | #define TARGET_HARD_REGNO_NREGS xtensa_hard_regno_nregs | |
317 | #undef TARGET_HARD_REGNO_MODE_OK | |
318 | #define TARGET_HARD_REGNO_MODE_OK xtensa_hard_regno_mode_ok | |
319 | ||
320 | #undef TARGET_MODES_TIEABLE_P | |
321 | #define TARGET_MODES_TIEABLE_P xtensa_modes_tieable_p | |
322 | ||
323 | #undef TARGET_CONSTANT_ALIGNMENT | |
324 | #define TARGET_CONSTANT_ALIGNMENT xtensa_constant_alignment | |
325 | ||
326 | #undef TARGET_STARTING_FRAME_OFFSET | |
327 | #define TARGET_STARTING_FRAME_OFFSET xtensa_starting_frame_offset | |
328 | ||
329 | #undef TARGET_ASAN_SHADOW_OFFSET | |
330 | #define TARGET_ASAN_SHADOW_OFFSET xtensa_asan_shadow_offset | |
331 | ||
332 | struct gcc_target targetm = TARGET_INITIALIZER; | |
333 | ||
334 | \f | |
335 | /* Functions to test Xtensa immediate operand validity. */ | |
336 | ||
337 | bool | |
338 | xtensa_simm8 (HOST_WIDE_INT v) | |
339 | { | |
340 | return v >= -128 && v <= 127; | |
341 | } | |
342 | ||
343 | ||
344 | bool | |
345 | xtensa_simm8x256 (HOST_WIDE_INT v) | |
346 | { | |
347 | return (v & 255) == 0 && (v >= -32768 && v <= 32512); | |
348 | } | |
349 | ||
350 | ||
351 | bool | |
352 | xtensa_simm12b (HOST_WIDE_INT v) | |
353 | { | |
354 | return v >= -2048 && v <= 2047; | |
355 | } | |
356 | ||
357 | ||
358 | static bool | |
359 | xtensa_uimm8 (HOST_WIDE_INT v) | |
360 | { | |
361 | return v >= 0 && v <= 255; | |
362 | } | |
363 | ||
364 | ||
365 | static bool | |
366 | xtensa_uimm8x2 (HOST_WIDE_INT v) | |
367 | { | |
368 | return (v & 1) == 0 && (v >= 0 && v <= 510); | |
369 | } | |
370 | ||
371 | ||
372 | static bool | |
373 | xtensa_uimm8x4 (HOST_WIDE_INT v) | |
374 | { | |
375 | return (v & 3) == 0 && (v >= 0 && v <= 1020); | |
376 | } | |
377 | ||
378 | ||
379 | static bool | |
380 | xtensa_b4const (HOST_WIDE_INT v) | |
381 | { | |
382 | switch (v) | |
383 | { | |
384 | case -1: | |
385 | case 1: | |
386 | case 2: | |
387 | case 3: | |
388 | case 4: | |
389 | case 5: | |
390 | case 6: | |
391 | case 7: | |
392 | case 8: | |
393 | case 10: | |
394 | case 12: | |
395 | case 16: | |
396 | case 32: | |
397 | case 64: | |
398 | case 128: | |
399 | case 256: | |
400 | return true; | |
401 | } | |
402 | return false; | |
403 | } | |
404 | ||
405 | ||
406 | bool | |
407 | xtensa_b4const_or_zero (HOST_WIDE_INT v) | |
408 | { | |
409 | if (v == 0) | |
410 | return true; | |
411 | return xtensa_b4const (v); | |
412 | } | |
413 | ||
414 | ||
415 | bool | |
416 | xtensa_b4constu (HOST_WIDE_INT v) | |
417 | { | |
418 | switch (v) | |
419 | { | |
420 | case 32768: | |
421 | case 65536: | |
422 | case 2: | |
423 | case 3: | |
424 | case 4: | |
425 | case 5: | |
426 | case 6: | |
427 | case 7: | |
428 | case 8: | |
429 | case 10: | |
430 | case 12: | |
431 | case 16: | |
432 | case 32: | |
433 | case 64: | |
434 | case 128: | |
435 | case 256: | |
436 | return true; | |
437 | } | |
438 | return false; | |
439 | } | |
440 | ||
441 | ||
442 | bool | |
443 | xtensa_mask_immediate (HOST_WIDE_INT v) | |
444 | { | |
445 | #define MAX_MASK_SIZE 16 | |
446 | int mask_size; | |
447 | ||
448 | for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++) | |
449 | { | |
450 | if ((v & 1) == 0) | |
451 | return false; | |
452 | v = v >> 1; | |
453 | if (v == 0) | |
454 | return true; | |
455 | } | |
456 | ||
457 | return false; | |
458 | } | |
459 | ||
460 | ||
461 | /* This is just like the standard true_regnum() function except that it | |
462 | works even when reg_renumber is not initialized. */ | |
463 | ||
464 | int | |
465 | xt_true_regnum (rtx x) | |
466 | { | |
467 | if (GET_CODE (x) == REG) | |
468 | { | |
469 | if (reg_renumber | |
470 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
471 | && reg_renumber[REGNO (x)] >= 0) | |
472 | return reg_renumber[REGNO (x)]; | |
473 | return REGNO (x); | |
474 | } | |
475 | if (GET_CODE (x) == SUBREG) | |
476 | { | |
477 | int base = xt_true_regnum (SUBREG_REG (x)); | |
478 | if (base >= 0 && base < FIRST_PSEUDO_REGISTER) | |
479 | return base + subreg_regno_offset (REGNO (SUBREG_REG (x)), | |
480 | GET_MODE (SUBREG_REG (x)), | |
481 | SUBREG_BYTE (x), GET_MODE (x)); | |
482 | } | |
483 | return -1; | |
484 | } | |
485 | ||
486 | ||
487 | int | |
488 | xtensa_valid_move (machine_mode mode, rtx *operands) | |
489 | { | |
490 | /* Either the destination or source must be a register, and the | |
491 | MAC16 accumulator doesn't count. */ | |
492 | ||
493 | if (register_operand (operands[0], mode)) | |
494 | { | |
495 | int dst_regnum = xt_true_regnum (operands[0]); | |
496 | ||
497 | if (xtensa_tls_referenced_p (operands[1])) | |
498 | return FALSE; | |
499 | ||
500 | /* The stack pointer can only be assigned with a MOVSP opcode. */ | |
501 | if (dst_regnum == STACK_POINTER_REGNUM) | |
502 | return !TARGET_WINDOWED_ABI | |
503 | || (mode == SImode | |
504 | && register_operand (operands[1], mode) | |
505 | && !ACC_REG_P (xt_true_regnum (operands[1]))); | |
506 | ||
507 | if (!ACC_REG_P (dst_regnum)) | |
508 | return true; | |
509 | } | |
510 | if (register_operand (operands[1], mode)) | |
511 | { | |
512 | int src_regnum = xt_true_regnum (operands[1]); | |
513 | if (!ACC_REG_P (src_regnum)) | |
514 | return true; | |
515 | } | |
516 | return FALSE; | |
517 | } | |
518 | ||
519 | ||
520 | int | |
521 | smalloffset_mem_p (rtx op) | |
522 | { | |
523 | if (GET_CODE (op) == MEM) | |
524 | { | |
525 | rtx addr = XEXP (op, 0); | |
526 | if (GET_CODE (addr) == REG) | |
527 | return BASE_REG_P (addr, 0); | |
528 | if (GET_CODE (addr) == PLUS) | |
529 | { | |
530 | rtx offset = XEXP (addr, 0); | |
531 | HOST_WIDE_INT val; | |
532 | if (GET_CODE (offset) != CONST_INT) | |
533 | offset = XEXP (addr, 1); | |
534 | if (GET_CODE (offset) != CONST_INT) | |
535 | return FALSE; | |
536 | ||
537 | val = INTVAL (offset); | |
538 | return (val & 3) == 0 && (val >= 0 && val <= 60); | |
539 | } | |
540 | } | |
541 | return FALSE; | |
542 | } | |
543 | ||
544 | ||
545 | static bool | |
546 | constantpool_address_p (const_rtx addr) | |
547 | { | |
548 | const_rtx sym = addr; | |
549 | ||
550 | if (GET_CODE (addr) == CONST) | |
551 | { | |
552 | rtx offset; | |
553 | ||
554 | /* Only handle (PLUS (SYM, OFFSET)) form. */ | |
555 | addr = XEXP (addr, 0); | |
556 | if (GET_CODE (addr) != PLUS) | |
557 | return false; | |
558 | ||
559 | /* Make sure the address is word aligned. */ | |
560 | offset = XEXP (addr, 1); | |
561 | if ((!CONST_INT_P (offset)) | |
562 | || ((INTVAL (offset) & 3) != 0)) | |
563 | return false; | |
564 | ||
565 | sym = XEXP (addr, 0); | |
566 | } | |
567 | ||
568 | if ((GET_CODE (sym) == SYMBOL_REF) | |
569 | && CONSTANT_POOL_ADDRESS_P (sym)) | |
570 | return true; | |
571 | return false; | |
572 | } | |
573 | ||
574 | ||
575 | int | |
576 | constantpool_mem_p (rtx op) | |
577 | { | |
578 | if (GET_CODE (op) == SUBREG) | |
579 | op = SUBREG_REG (op); | |
580 | if (GET_CODE (op) == MEM) | |
581 | return constantpool_address_p (XEXP (op, 0)); | |
582 | return FALSE; | |
583 | } | |
584 | ||
585 | ||
586 | /* Return TRUE if X is a thread-local symbol. */ | |
587 | ||
588 | static bool | |
589 | xtensa_tls_symbol_p (rtx x) | |
590 | { | |
591 | if (! TARGET_HAVE_TLS) | |
592 | return false; | |
593 | ||
594 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
595 | } | |
596 | ||
597 | ||
598 | void | |
599 | xtensa_extend_reg (rtx dst, rtx src) | |
600 | { | |
601 | rtx temp = gen_reg_rtx (SImode); | |
602 | rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src))); | |
603 | ||
604 | /* Generate paradoxical subregs as needed so that the modes match. */ | |
605 | src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0); | |
606 | dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0); | |
607 | ||
608 | emit_insn (gen_ashlsi3 (temp, src, shift)); | |
609 | emit_insn (gen_ashrsi3 (dst, temp, shift)); | |
610 | } | |
611 | ||
612 | ||
613 | bool | |
614 | xtensa_mem_offset (unsigned v, machine_mode mode) | |
615 | { | |
616 | switch (mode) | |
617 | { | |
618 | case E_BLKmode: | |
619 | /* Handle the worst case for block moves. See xtensa_expand_block_move | |
620 | where we emit an optimized block move operation if the block can be | |
621 | moved in < "move_ratio" pieces. The worst case is when the block is | |
622 | aligned but has a size of (3 mod 4) (does this happen?) so that the | |
623 | last piece requires a byte load/store. */ | |
624 | return (xtensa_uimm8 (v) | |
625 | && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO)); | |
626 | ||
627 | case E_QImode: | |
628 | return xtensa_uimm8 (v); | |
629 | ||
630 | case E_HImode: | |
631 | return xtensa_uimm8x2 (v); | |
632 | ||
633 | case E_DImode: | |
634 | case E_DFmode: | |
635 | return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4)); | |
636 | ||
637 | default: | |
638 | break; | |
639 | } | |
640 | ||
641 | return xtensa_uimm8x4 (v); | |
642 | } | |
643 | ||
644 | ||
645 | /* Make normal rtx_code into something we can index from an array. */ | |
646 | ||
647 | static enum internal_test | |
648 | map_test_to_internal_test (enum rtx_code test_code) | |
649 | { | |
650 | enum internal_test test = ITEST_MAX; | |
651 | ||
652 | switch (test_code) | |
653 | { | |
654 | default: break; | |
655 | case EQ: test = ITEST_EQ; break; | |
656 | case NE: test = ITEST_NE; break; | |
657 | case GT: test = ITEST_GT; break; | |
658 | case GE: test = ITEST_GE; break; | |
659 | case LT: test = ITEST_LT; break; | |
660 | case LE: test = ITEST_LE; break; | |
661 | case GTU: test = ITEST_GTU; break; | |
662 | case GEU: test = ITEST_GEU; break; | |
663 | case LTU: test = ITEST_LTU; break; | |
664 | case LEU: test = ITEST_LEU; break; | |
665 | } | |
666 | ||
667 | return test; | |
668 | } | |
669 | ||
670 | ||
671 | /* Generate the code to compare two integer values. The return value is | |
672 | the comparison expression. */ | |
673 | ||
674 | static rtx | |
675 | gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ | |
676 | rtx cmp0, /* first operand to compare */ | |
677 | rtx cmp1, /* second operand to compare */ | |
678 | int *p_invert /* whether branch needs to reverse test */) | |
679 | { | |
680 | struct cmp_info | |
681 | { | |
682 | enum rtx_code test_code; /* test code to use in insn */ | |
683 | bool (*const_range_p) (HOST_WIDE_INT); /* range check function */ | |
684 | int const_add; /* constant to add (convert LE -> LT) */ | |
685 | int reverse_regs; /* reverse registers in test */ | |
686 | int invert_const; /* != 0 if invert value if cmp1 is constant */ | |
687 | int invert_reg; /* != 0 if invert value if cmp1 is register */ | |
688 | int unsignedp; /* != 0 for unsigned comparisons. */ | |
689 | }; | |
690 | ||
691 | static struct cmp_info info[ (int)ITEST_MAX ] = { | |
692 | ||
693 | { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */ | |
694 | { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */ | |
695 | ||
696 | { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */ | |
697 | { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */ | |
698 | { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */ | |
699 | { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */ | |
700 | ||
701 | { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */ | |
702 | { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */ | |
703 | { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */ | |
704 | { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */ | |
705 | }; | |
706 | ||
707 | enum internal_test test; | |
708 | machine_mode mode; | |
709 | struct cmp_info *p_info; | |
710 | ||
711 | test = map_test_to_internal_test (test_code); | |
712 | gcc_assert (test != ITEST_MAX); | |
713 | ||
714 | p_info = &info[ (int)test ]; | |
715 | ||
716 | mode = GET_MODE (cmp0); | |
717 | if (mode == VOIDmode) | |
718 | mode = GET_MODE (cmp1); | |
719 | ||
720 | /* Make sure we can handle any constants given to us. */ | |
721 | if (GET_CODE (cmp1) == CONST_INT) | |
722 | { | |
723 | HOST_WIDE_INT value = INTVAL (cmp1); | |
724 | unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value; | |
725 | ||
726 | /* if the immediate overflows or does not fit in the immediate field, | |
727 | spill it to a register */ | |
728 | ||
729 | if ((p_info->unsignedp ? | |
730 | (uvalue + p_info->const_add > uvalue) : | |
731 | (value + p_info->const_add > value)) != (p_info->const_add > 0)) | |
732 | { | |
733 | cmp1 = force_reg (mode, cmp1); | |
734 | } | |
735 | else if (!(p_info->const_range_p) (value + p_info->const_add)) | |
736 | { | |
737 | cmp1 = force_reg (mode, cmp1); | |
738 | } | |
739 | } | |
740 | else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG)) | |
741 | { | |
742 | cmp1 = force_reg (mode, cmp1); | |
743 | } | |
744 | ||
745 | /* See if we need to invert the result. */ | |
746 | *p_invert = ((GET_CODE (cmp1) == CONST_INT) | |
747 | ? p_info->invert_const | |
748 | : p_info->invert_reg); | |
749 | ||
750 | /* Comparison to constants, may involve adding 1 to change a LT into LE. | |
751 | Comparison between two registers, may involve switching operands. */ | |
752 | if (GET_CODE (cmp1) == CONST_INT) | |
753 | { | |
754 | if (p_info->const_add != 0) | |
755 | cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add); | |
756 | ||
757 | } | |
758 | else if (p_info->reverse_regs) | |
759 | { | |
760 | rtx temp = cmp0; | |
761 | cmp0 = cmp1; | |
762 | cmp1 = temp; | |
763 | } | |
764 | ||
765 | return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1); | |
766 | } | |
767 | ||
768 | ||
769 | /* Generate the code to compare two float values. The return value is | |
770 | the comparison expression. */ | |
771 | ||
772 | static rtx | |
773 | gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ | |
774 | rtx cmp0, /* first operand to compare */ | |
775 | rtx cmp1 /* second operand to compare */) | |
776 | { | |
777 | rtx (*gen_fn) (rtx, rtx, rtx); | |
778 | rtx brtmp; | |
779 | int reverse_regs, invert; | |
780 | ||
781 | switch (test_code) | |
782 | { | |
783 | case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break; | |
784 | case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break; | |
785 | case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break; | |
786 | case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break; | |
787 | case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break; | |
788 | case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break; | |
789 | case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break; | |
790 | case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break; | |
791 | case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break; | |
792 | case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break; | |
793 | case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break; | |
794 | case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break; | |
795 | case UNORDERED: | |
796 | reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break; | |
797 | case ORDERED: | |
798 | reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break; | |
799 | default: | |
800 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); | |
801 | reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */ | |
802 | } | |
803 | ||
804 | if (reverse_regs) | |
805 | { | |
806 | rtx temp = cmp0; | |
807 | cmp0 = cmp1; | |
808 | cmp1 = temp; | |
809 | } | |
810 | ||
811 | brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM); | |
812 | emit_insn (gen_fn (brtmp, cmp0, cmp1)); | |
813 | ||
814 | return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx); | |
815 | } | |
816 | ||
817 | ||
818 | void | |
819 | xtensa_expand_conditional_branch (rtx *operands, machine_mode mode) | |
820 | { | |
821 | enum rtx_code test_code = GET_CODE (operands[0]); | |
822 | rtx cmp0 = operands[1]; | |
823 | rtx cmp1 = operands[2]; | |
824 | rtx cmp; | |
825 | int invert; | |
826 | rtx label1, label2; | |
827 | ||
828 | switch (mode) | |
829 | { | |
830 | case E_DFmode: | |
831 | default: | |
832 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); | |
833 | ||
834 | case E_SImode: | |
835 | invert = FALSE; | |
836 | cmp = gen_int_relational (test_code, cmp0, cmp1, &invert); | |
837 | break; | |
838 | ||
839 | case E_SFmode: | |
840 | if (!TARGET_HARD_FLOAT) | |
841 | fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, | |
842 | cmp0, cmp1)); | |
843 | invert = FALSE; | |
844 | cmp = gen_float_relational (test_code, cmp0, cmp1); | |
845 | break; | |
846 | } | |
847 | ||
848 | /* Generate the branch. */ | |
849 | ||
850 | label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]); | |
851 | label2 = pc_rtx; | |
852 | ||
853 | if (invert) | |
854 | { | |
855 | label2 = label1; | |
856 | label1 = pc_rtx; | |
857 | } | |
858 | ||
859 | emit_jump_insn (gen_rtx_SET (pc_rtx, | |
860 | gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, | |
861 | label1, | |
862 | label2))); | |
863 | } | |
864 | ||
865 | ||
866 | static rtx | |
867 | gen_conditional_move (enum rtx_code code, machine_mode mode, | |
868 | rtx op0, rtx op1) | |
869 | { | |
870 | if (mode == SImode) | |
871 | { | |
872 | rtx cmp; | |
873 | ||
874 | /* Jump optimization calls get_condition() which canonicalizes | |
875 | comparisons like (GE x <const>) to (GT x <const-1>). | |
876 | Transform those comparisons back to GE, since that is the | |
877 | comparison supported in Xtensa. We shouldn't have to | |
878 | transform <LE x const> comparisons, because neither | |
879 | xtensa_expand_conditional_branch() nor get_condition() will | |
880 | produce them. */ | |
881 | ||
882 | if ((code == GT) && (op1 == constm1_rtx)) | |
883 | { | |
884 | code = GE; | |
885 | op1 = const0_rtx; | |
886 | } | |
887 | cmp = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx); | |
888 | ||
889 | if (boolean_operator (cmp, VOIDmode)) | |
890 | { | |
891 | /* Swap the operands to make const0 second. */ | |
892 | if (op0 == const0_rtx) | |
893 | { | |
894 | op0 = op1; | |
895 | op1 = const0_rtx; | |
896 | } | |
897 | ||
898 | /* If not comparing against zero, emit a comparison (subtract). */ | |
899 | if (op1 != const0_rtx) | |
900 | { | |
901 | op0 = expand_binop (SImode, sub_optab, op0, op1, | |
902 | 0, 0, OPTAB_LIB_WIDEN); | |
903 | op1 = const0_rtx; | |
904 | } | |
905 | } | |
906 | else if (branch_operator (cmp, VOIDmode)) | |
907 | { | |
908 | /* Swap the operands to make const0 second. */ | |
909 | if (op0 == const0_rtx) | |
910 | { | |
911 | op0 = op1; | |
912 | op1 = const0_rtx; | |
913 | ||
914 | switch (code) | |
915 | { | |
916 | case LT: code = GE; break; | |
917 | case GE: code = LT; break; | |
918 | default: gcc_unreachable (); | |
919 | } | |
920 | } | |
921 | ||
922 | if (op1 != const0_rtx) | |
923 | return 0; | |
924 | } | |
925 | else | |
926 | return 0; | |
927 | ||
928 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); | |
929 | } | |
930 | ||
931 | if (TARGET_HARD_FLOAT && mode == SFmode) | |
932 | return gen_float_relational (code, op0, op1); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
937 | ||
938 | int | |
939 | xtensa_expand_conditional_move (rtx *operands, int isflt) | |
940 | { | |
941 | rtx dest = operands[0]; | |
942 | rtx cmp = operands[1]; | |
943 | machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0)); | |
944 | rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); | |
945 | ||
946 | if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode, | |
947 | XEXP (cmp, 0), XEXP (cmp, 1)))) | |
948 | return 0; | |
949 | ||
950 | if (isflt) | |
951 | gen_fn = (cmp_mode == SImode | |
952 | ? gen_movsfcc_internal0 | |
953 | : gen_movsfcc_internal1); | |
954 | else | |
955 | gen_fn = (cmp_mode == SImode | |
956 | ? gen_movsicc_internal0 | |
957 | : gen_movsicc_internal1); | |
958 | ||
959 | emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp)); | |
960 | return 1; | |
961 | } | |
962 | ||
963 | ||
964 | int | |
965 | xtensa_expand_scc (rtx operands[4], machine_mode cmp_mode) | |
966 | { | |
967 | rtx dest = operands[0]; | |
968 | rtx cmp; | |
969 | rtx one_tmp, zero_tmp; | |
970 | rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); | |
971 | ||
972 | if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode, | |
973 | operands[2], operands[3]))) | |
974 | return 0; | |
975 | ||
976 | one_tmp = gen_reg_rtx (SImode); | |
977 | zero_tmp = gen_reg_rtx (SImode); | |
978 | emit_insn (gen_movsi (one_tmp, const_true_rtx)); | |
979 | emit_insn (gen_movsi (zero_tmp, const0_rtx)); | |
980 | ||
981 | gen_fn = (cmp_mode == SImode | |
982 | ? gen_movsicc_internal0 | |
983 | : gen_movsicc_internal1); | |
984 | emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp)); | |
985 | return 1; | |
986 | } | |
987 | ||
988 | ||
989 | /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is | |
990 | for the output, i.e., the input operands are twice as big as MODE. */ | |
991 | ||
992 | void | |
993 | xtensa_split_operand_pair (rtx operands[4], machine_mode mode) | |
994 | { | |
995 | switch (GET_CODE (operands[1])) | |
996 | { | |
997 | case REG: | |
998 | operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1); | |
999 | operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); | |
1000 | break; | |
1001 | ||
1002 | case MEM: | |
1003 | operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode)); | |
1004 | operands[2] = adjust_address (operands[1], mode, 0); | |
1005 | break; | |
1006 | ||
1007 | case CONST_INT: | |
1008 | case CONST_DOUBLE: | |
1009 | split_double (operands[1], &operands[2], &operands[3]); | |
1010 | break; | |
1011 | ||
1012 | default: | |
1013 | gcc_unreachable (); | |
1014 | } | |
1015 | ||
1016 | switch (GET_CODE (operands[0])) | |
1017 | { | |
1018 | case REG: | |
1019 | operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1); | |
1020 | operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); | |
1021 | break; | |
1022 | ||
1023 | case MEM: | |
1024 | operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode)); | |
1025 | operands[0] = adjust_address (operands[0], mode, 0); | |
1026 | break; | |
1027 | ||
1028 | default: | |
1029 | gcc_unreachable (); | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | ||
1034 | /* Emit insns to move operands[1] into operands[0]. | |
1035 | Return 1 if we have written out everything that needs to be done to | |
1036 | do the move. Otherwise, return 0 and the caller will emit the move | |
1037 | normally. */ | |
1038 | ||
1039 | int | |
1040 | xtensa_emit_move_sequence (rtx *operands, machine_mode mode) | |
1041 | { | |
1042 | rtx src = operands[1]; | |
1043 | ||
1044 | if (CONSTANT_P (src) | |
1045 | && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src)))) | |
1046 | { | |
1047 | rtx dst = operands[0]; | |
1048 | ||
1049 | if (xtensa_tls_referenced_p (src)) | |
1050 | { | |
1051 | rtx addend = NULL; | |
1052 | ||
1053 | if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS) | |
1054 | { | |
1055 | addend = XEXP (XEXP (src, 0), 1); | |
1056 | src = XEXP (XEXP (src, 0), 0); | |
1057 | } | |
1058 | ||
1059 | src = xtensa_legitimize_tls_address (src); | |
1060 | if (addend) | |
1061 | { | |
1062 | src = gen_rtx_PLUS (mode, src, addend); | |
1063 | src = force_operand (src, dst); | |
1064 | } | |
1065 | emit_move_insn (dst, src); | |
1066 | return 1; | |
1067 | } | |
1068 | ||
1069 | if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) | |
1070 | { | |
1071 | src = force_const_mem (SImode, src); | |
1072 | operands[1] = src; | |
1073 | } | |
1074 | ||
1075 | /* PC-relative loads are always SImode, and CONST16 is only | |
1076 | supported in the movsi pattern, so add a SUBREG for any other | |
1077 | (smaller) mode. */ | |
1078 | ||
1079 | if (mode != SImode) | |
1080 | { | |
1081 | if (register_operand (dst, mode)) | |
1082 | { | |
1083 | emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src); | |
1084 | return 1; | |
1085 | } | |
1086 | else | |
1087 | { | |
1088 | src = force_reg (SImode, src); | |
1089 | src = gen_lowpart_SUBREG (mode, src); | |
1090 | operands[1] = src; | |
1091 | } | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | if (!(reload_in_progress | reload_completed) | |
1096 | && !xtensa_valid_move (mode, operands)) | |
1097 | operands[1] = force_reg (mode, operands[1]); | |
1098 | ||
1099 | operands[1] = xtensa_copy_incoming_a7 (operands[1]); | |
1100 | ||
1101 | /* During reload we don't want to emit (subreg:X (mem:Y)) since that | |
1102 | instruction won't be recognized after reload, so we remove the | |
1103 | subreg and adjust mem accordingly. */ | |
1104 | if (reload_in_progress) | |
1105 | { | |
1106 | operands[0] = fixup_subreg_mem (operands[0]); | |
1107 | operands[1] = fixup_subreg_mem (operands[1]); | |
1108 | } | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | ||
1113 | static rtx | |
1114 | fixup_subreg_mem (rtx x) | |
1115 | { | |
1116 | if (GET_CODE (x) == SUBREG | |
1117 | && GET_CODE (SUBREG_REG (x)) == REG | |
1118 | && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) | |
1119 | { | |
1120 | rtx temp = | |
1121 | gen_rtx_SUBREG (GET_MODE (x), | |
1122 | reg_equiv_mem (REGNO (SUBREG_REG (x))), | |
1123 | SUBREG_BYTE (x)); | |
1124 | x = alter_subreg (&temp, true); | |
1125 | } | |
1126 | return x; | |
1127 | } | |
1128 | ||
1129 | ||
1130 | /* Check if an incoming argument in a7 is expected to be used soon and | |
1131 | if OPND is a register or register pair that includes a7. If so, | |
1132 | create a new pseudo and copy a7 into that pseudo at the very | |
1133 | beginning of the function, followed by the special "set_frame_ptr" | |
1134 | unspec_volatile insn. The return value is either the original | |
1135 | operand, if it is not a7, or the new pseudo containing a copy of | |
1136 | the incoming argument. This is necessary because the register | |
1137 | allocator will ignore conflicts with a7 and may either assign some | |
1138 | other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering | |
1139 | the incoming argument in a7. By copying the argument out of a7 as | |
1140 | the very first thing, and then immediately following that with an | |
1141 | unspec_volatile to keep the scheduler away, we should avoid any | |
1142 | problems. Putting the set_frame_ptr insn at the beginning, with | |
1143 | only the a7 copy before it, also makes it easier for the prologue | |
1144 | expander to initialize the frame pointer after the a7 copy and to | |
1145 | fix up the a7 copy to use the stack pointer instead of the frame | |
1146 | pointer. */ | |
1147 | ||
1148 | rtx | |
1149 | xtensa_copy_incoming_a7 (rtx opnd) | |
1150 | { | |
1151 | rtx entry_insns = 0; | |
1152 | rtx reg, tmp; | |
1153 | machine_mode mode; | |
1154 | ||
1155 | if (!cfun->machine->need_a7_copy) | |
1156 | return opnd; | |
1157 | ||
1158 | /* This function should never be called again once a7 has been copied. */ | |
1159 | gcc_assert (!cfun->machine->set_frame_ptr_insn); | |
1160 | ||
1161 | mode = GET_MODE (opnd); | |
1162 | ||
1163 | /* The operand using a7 may come in a later instruction, so just return | |
1164 | the original operand if it doesn't use a7. */ | |
1165 | reg = opnd; | |
1166 | if (GET_CODE (reg) == SUBREG) | |
1167 | { | |
1168 | gcc_assert (SUBREG_BYTE (reg) == 0); | |
1169 | reg = SUBREG_REG (reg); | |
1170 | } | |
1171 | if (GET_CODE (reg) != REG | |
1172 | || REGNO (reg) > A7_REG | |
1173 | || REGNO (reg) + hard_regno_nregs (A7_REG, mode) <= A7_REG) | |
1174 | return opnd; | |
1175 | ||
1176 | /* 1-word args will always be in a7; 2-word args in a6/a7. */ | |
1177 | gcc_assert (REGNO (reg) + hard_regno_nregs (A7_REG, mode) - 1 == A7_REG); | |
1178 | ||
1179 | cfun->machine->need_a7_copy = false; | |
1180 | ||
1181 | /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to | |
1182 | create the REG for a7 so that hard_frame_pointer_rtx is not used. */ | |
1183 | ||
1184 | start_sequence (); | |
1185 | tmp = gen_reg_rtx (mode); | |
1186 | ||
1187 | switch (mode) | |
1188 | { | |
1189 | case E_DFmode: | |
1190 | case E_DImode: | |
1191 | /* Copy the value out of A7 here but keep the first word in A6 until | |
1192 | after the set_frame_ptr insn. Otherwise, the register allocator | |
1193 | may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming | |
1194 | value. */ | |
1195 | emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4), | |
1196 | gen_raw_REG (SImode, A7_REG))); | |
1197 | break; | |
1198 | case E_SFmode: | |
1199 | emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1200 | break; | |
1201 | case E_SImode: | |
1202 | emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1203 | break; | |
1204 | case E_HImode: | |
1205 | emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1206 | break; | |
1207 | case E_QImode: | |
1208 | emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG))); | |
1209 | break; | |
1210 | default: | |
1211 | gcc_unreachable (); | |
1212 | } | |
1213 | ||
1214 | cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ()); | |
1215 | ||
1216 | /* For DF and DI mode arguments, copy the incoming value in A6 now. */ | |
1217 | if (mode == DFmode || mode == DImode) | |
1218 | emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0), | |
1219 | gen_rtx_REG (SImode, A7_REG - 1))); | |
1220 | entry_insns = get_insns (); | |
1221 | end_sequence (); | |
1222 | ||
1223 | if (cfun->machine->vararg_a7) | |
1224 | { | |
1225 | /* This is called from within builtin_saveregs, which will insert the | |
1226 | saveregs code at the function entry, ahead of anything placed at | |
1227 | the function entry now. Instead, save the sequence to be inserted | |
1228 | at the beginning of the saveregs code. */ | |
1229 | cfun->machine->vararg_a7_copy = entry_insns; | |
1230 | } | |
1231 | else | |
1232 | { | |
1233 | /* Put entry_insns after the NOTE that starts the function. If | |
1234 | this is inside a start_sequence, make the outer-level insn | |
1235 | chain current, so the code is placed at the start of the | |
1236 | function. */ | |
1237 | push_topmost_sequence (); | |
1238 | /* Do not use entry_of_function() here. This is called from within | |
1239 | expand_function_start, when the CFG still holds GIMPLE. */ | |
1240 | emit_insn_after (entry_insns, get_insns ()); | |
1241 | pop_topmost_sequence (); | |
1242 | } | |
1243 | ||
1244 | return tmp; | |
1245 | } | |
1246 | ||
1247 | ||
1248 | /* Try to expand a block move operation to a sequence of RTL move | |
1249 | instructions. If not optimizing, or if the block size is not a | |
1250 | constant, or if the block is too large, the expansion fails and GCC | |
1251 | falls back to calling memcpy(). | |
1252 | ||
1253 | operands[0] is the destination | |
1254 | operands[1] is the source | |
1255 | operands[2] is the length | |
1256 | operands[3] is the alignment */ | |
1257 | ||
1258 | int | |
1259 | xtensa_expand_block_move (rtx *operands) | |
1260 | { | |
1261 | static const machine_mode mode_from_align[] = | |
1262 | { | |
1263 | VOIDmode, QImode, HImode, VOIDmode, SImode, | |
1264 | }; | |
1265 | ||
1266 | rtx dst_mem = operands[0]; | |
1267 | rtx src_mem = operands[1]; | |
1268 | HOST_WIDE_INT bytes, align; | |
1269 | int num_pieces, move_ratio; | |
1270 | rtx temp[2]; | |
1271 | machine_mode mode[2]; | |
1272 | int amount[2]; | |
1273 | bool active[2]; | |
1274 | int phase = 0; | |
1275 | int next; | |
1276 | int offset_ld = 0; | |
1277 | int offset_st = 0; | |
1278 | rtx x; | |
1279 | ||
1280 | /* If this is not a fixed size move, just call memcpy. */ | |
1281 | if (!optimize || (GET_CODE (operands[2]) != CONST_INT)) | |
1282 | return 0; | |
1283 | ||
1284 | bytes = INTVAL (operands[2]); | |
1285 | align = INTVAL (operands[3]); | |
1286 | ||
1287 | /* Anything to move? */ | |
1288 | if (bytes <= 0) | |
1289 | return 0; | |
1290 | ||
1291 | if (align > MOVE_MAX) | |
1292 | align = MOVE_MAX; | |
1293 | ||
1294 | /* Decide whether to expand inline based on the optimization level. */ | |
1295 | move_ratio = 4; | |
1296 | if (optimize > 2) | |
1297 | move_ratio = LARGEST_MOVE_RATIO; | |
1298 | num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */ | |
1299 | if (num_pieces > move_ratio) | |
1300 | return 0; | |
1301 | ||
1302 | x = XEXP (dst_mem, 0); | |
1303 | if (!REG_P (x)) | |
1304 | { | |
1305 | x = force_reg (Pmode, x); | |
1306 | dst_mem = replace_equiv_address (dst_mem, x); | |
1307 | } | |
1308 | ||
1309 | x = XEXP (src_mem, 0); | |
1310 | if (!REG_P (x)) | |
1311 | { | |
1312 | x = force_reg (Pmode, x); | |
1313 | src_mem = replace_equiv_address (src_mem, x); | |
1314 | } | |
1315 | ||
1316 | active[0] = active[1] = false; | |
1317 | ||
1318 | do | |
1319 | { | |
1320 | next = phase; | |
1321 | phase ^= 1; | |
1322 | ||
1323 | if (bytes > 0) | |
1324 | { | |
1325 | int next_amount; | |
1326 | ||
1327 | next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1)); | |
1328 | next_amount = MIN (next_amount, align); | |
1329 | ||
1330 | amount[next] = next_amount; | |
1331 | mode[next] = mode_from_align[next_amount]; | |
1332 | temp[next] = gen_reg_rtx (mode[next]); | |
1333 | ||
1334 | x = adjust_address (src_mem, mode[next], offset_ld); | |
1335 | emit_insn (gen_rtx_SET (temp[next], x)); | |
1336 | ||
1337 | offset_ld += next_amount; | |
1338 | bytes -= next_amount; | |
1339 | active[next] = true; | |
1340 | } | |
1341 | ||
1342 | if (active[phase]) | |
1343 | { | |
1344 | active[phase] = false; | |
1345 | ||
1346 | x = adjust_address (dst_mem, mode[phase], offset_st); | |
1347 | emit_insn (gen_rtx_SET (x, temp[phase])); | |
1348 | ||
1349 | offset_st += amount[phase]; | |
1350 | } | |
1351 | } | |
1352 | while (active[next]); | |
1353 | ||
1354 | return 1; | |
1355 | } | |
1356 | ||
1357 | ||
1358 | void | |
1359 | xtensa_expand_nonlocal_goto (rtx *operands) | |
1360 | { | |
1361 | rtx goto_handler = operands[1]; | |
1362 | rtx containing_fp = operands[3]; | |
1363 | ||
1364 | /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code | |
1365 | is too big to generate in-line. */ | |
1366 | ||
1367 | if (GET_CODE (containing_fp) != REG) | |
1368 | containing_fp = force_reg (Pmode, containing_fp); | |
1369 | ||
1370 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"), | |
1371 | LCT_NORMAL, VOIDmode, | |
1372 | containing_fp, Pmode, | |
1373 | goto_handler, Pmode); | |
1374 | } | |
1375 | ||
1376 | ||
1377 | static struct machine_function * | |
1378 | xtensa_init_machine_status (void) | |
1379 | { | |
1380 | return ggc_cleared_alloc<machine_function> (); | |
1381 | } | |
1382 | ||
1383 | ||
1384 | /* Shift VAL of mode MODE left by COUNT bits. */ | |
1385 | ||
1386 | static inline rtx | |
1387 | xtensa_expand_mask_and_shift (rtx val, machine_mode mode, rtx count) | |
1388 | { | |
1389 | val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
1390 | NULL_RTX, 1, OPTAB_DIRECT); | |
1391 | return expand_simple_binop (SImode, ASHIFT, val, count, | |
1392 | NULL_RTX, 1, OPTAB_DIRECT); | |
1393 | } | |
1394 | ||
1395 | ||
1396 | /* Structure to hold the initial parameters for a compare_and_swap operation | |
1397 | in HImode and QImode. */ | |
1398 | ||
1399 | struct alignment_context | |
1400 | { | |
1401 | rtx memsi; /* SI aligned memory location. */ | |
1402 | rtx shift; /* Bit offset with regard to lsb. */ | |
1403 | rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
1404 | rtx modemaski; /* ~modemask */ | |
1405 | }; | |
1406 | ||
1407 | ||
1408 | /* Initialize structure AC for word access to HI and QI mode memory. */ | |
1409 | ||
1410 | static void | |
1411 | init_alignment_context (struct alignment_context *ac, rtx mem) | |
1412 | { | |
1413 | machine_mode mode = GET_MODE (mem); | |
1414 | rtx byteoffset = NULL_RTX; | |
1415 | bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
1416 | ||
1417 | if (aligned) | |
1418 | ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
1419 | else | |
1420 | { | |
1421 | /* Alignment is unknown. */ | |
1422 | rtx addr, align; | |
1423 | ||
1424 | /* Force the address into a register. */ | |
1425 | addr = force_reg (Pmode, XEXP (mem, 0)); | |
1426 | ||
1427 | /* Align it to SImode. */ | |
1428 | align = expand_simple_binop (Pmode, AND, addr, | |
1429 | GEN_INT (-GET_MODE_SIZE (SImode)), | |
1430 | NULL_RTX, 1, OPTAB_DIRECT); | |
1431 | /* Generate MEM. */ | |
1432 | ac->memsi = gen_rtx_MEM (SImode, align); | |
1433 | MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
1434 | set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); | |
1435 | set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); | |
1436 | ||
1437 | byteoffset = expand_simple_binop (Pmode, AND, addr, | |
1438 | GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
1439 | NULL_RTX, 1, OPTAB_DIRECT); | |
1440 | } | |
1441 | ||
1442 | /* Calculate shiftcount. */ | |
1443 | if (TARGET_BIG_ENDIAN) | |
1444 | { | |
1445 | ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
1446 | if (!aligned) | |
1447 | ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
1448 | NULL_RTX, 1, OPTAB_DIRECT); | |
1449 | } | |
1450 | else | |
1451 | { | |
1452 | if (aligned) | |
1453 | ac->shift = NULL_RTX; | |
1454 | else | |
1455 | ac->shift = byteoffset; | |
1456 | } | |
1457 | ||
1458 | if (ac->shift != NULL_RTX) | |
1459 | { | |
1460 | /* Shift is the byte count, but we need the bitcount. */ | |
1461 | gcc_assert (exact_log2 (BITS_PER_UNIT) >= 0); | |
1462 | ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, | |
1463 | GEN_INT (exact_log2 (BITS_PER_UNIT)), | |
1464 | NULL_RTX, 1, OPTAB_DIRECT); | |
1465 | ac->modemask = expand_simple_binop (SImode, ASHIFT, | |
1466 | GEN_INT (GET_MODE_MASK (mode)), | |
1467 | ac->shift, | |
1468 | NULL_RTX, 1, OPTAB_DIRECT); | |
1469 | } | |
1470 | else | |
1471 | ac->modemask = GEN_INT (GET_MODE_MASK (mode)); | |
1472 | ||
1473 | ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); | |
1474 | } | |
1475 | ||
1476 | ||
1477 | /* Expand an atomic compare and swap operation for HImode and QImode. | |
1478 | MEM is the memory location, CMP the old value to compare MEM with | |
1479 | and NEW_RTX the value to set if CMP == MEM. */ | |
1480 | ||
1481 | void | |
1482 | xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx) | |
1483 | { | |
1484 | machine_mode mode = GET_MODE (mem); | |
1485 | struct alignment_context ac; | |
1486 | rtx tmp, cmpv, newv, val; | |
1487 | rtx oldval = gen_reg_rtx (SImode); | |
1488 | rtx res = gen_reg_rtx (SImode); | |
1489 | rtx_code_label *csloop = gen_label_rtx (); | |
1490 | rtx_code_label *csend = gen_label_rtx (); | |
1491 | ||
1492 | init_alignment_context (&ac, mem); | |
1493 | ||
1494 | if (ac.shift != NULL_RTX) | |
1495 | { | |
1496 | cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift); | |
1497 | new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift); | |
1498 | } | |
1499 | ||
1500 | /* Load the surrounding word into VAL with the MEM value masked out. */ | |
1501 | val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi, | |
1502 | ac.modemaski, NULL_RTX, 1, | |
1503 | OPTAB_DIRECT)); | |
1504 | emit_label (csloop); | |
1505 | ||
1506 | /* Patch CMP and NEW_RTX into VAL at correct position. */ | |
1507 | cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, | |
1508 | NULL_RTX, 1, OPTAB_DIRECT)); | |
1509 | newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val, | |
1510 | NULL_RTX, 1, OPTAB_DIRECT)); | |
1511 | ||
1512 | /* Jump to end if we're done. */ | |
1513 | emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv)); | |
1514 | emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend); | |
1515 | ||
1516 | /* Check for changes outside mode. */ | |
1517 | emit_move_insn (oldval, val); | |
1518 | tmp = expand_simple_binop (SImode, AND, res, ac.modemaski, | |
1519 | val, 1, OPTAB_DIRECT); | |
1520 | if (tmp != val) | |
1521 | emit_move_insn (val, tmp); | |
1522 | ||
1523 | /* Loop internal if so. */ | |
1524 | emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop); | |
1525 | ||
1526 | emit_label (csend); | |
1527 | ||
1528 | /* Return the correct part of the bitfield. */ | |
1529 | convert_move (target, | |
1530 | (ac.shift == NULL_RTX ? res | |
1531 | : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, | |
1532 | NULL_RTX, 1, OPTAB_DIRECT)), | |
1533 | 1); | |
1534 | } | |
1535 | ||
1536 | ||
1537 | /* Expand an atomic operation CODE of mode MODE (either HImode or QImode -- | |
1538 | the default expansion works fine for SImode). MEM is the memory location | |
1539 | and VAL the value to play with. If AFTER is true then store the value | |
1540 | MEM holds after the operation, if AFTER is false then store the value MEM | |
1541 | holds before the operation. If TARGET is zero then discard that value, else | |
1542 | store it to TARGET. */ | |
1543 | ||
1544 | void | |
1545 | xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val, | |
1546 | bool after) | |
1547 | { | |
1548 | machine_mode mode = GET_MODE (mem); | |
1549 | struct alignment_context ac; | |
1550 | rtx_code_label *csloop = gen_label_rtx (); | |
1551 | rtx cmp, tmp; | |
1552 | rtx old = gen_reg_rtx (SImode); | |
1553 | rtx new_rtx = gen_reg_rtx (SImode); | |
1554 | rtx orig = NULL_RTX; | |
1555 | ||
1556 | init_alignment_context (&ac, mem); | |
1557 | ||
1558 | /* Prepare values before the compare-and-swap loop. */ | |
1559 | if (ac.shift != NULL_RTX) | |
1560 | val = xtensa_expand_mask_and_shift (val, mode, ac.shift); | |
1561 | switch (code) | |
1562 | { | |
1563 | case PLUS: | |
1564 | case MINUS: | |
1565 | orig = gen_reg_rtx (SImode); | |
1566 | convert_move (orig, val, 1); | |
1567 | break; | |
1568 | ||
1569 | case SET: | |
1570 | case IOR: | |
1571 | case XOR: | |
1572 | break; | |
1573 | ||
1574 | case MULT: /* NAND */ | |
1575 | case AND: | |
1576 | /* val = "11..1<val>11..1" */ | |
1577 | val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
1578 | NULL_RTX, 1, OPTAB_DIRECT); | |
1579 | break; | |
1580 | ||
1581 | default: | |
1582 | gcc_unreachable (); | |
1583 | } | |
1584 | ||
1585 | /* Load full word. Subsequent loads are performed by S32C1I. */ | |
1586 | cmp = force_reg (SImode, ac.memsi); | |
1587 | ||
1588 | emit_label (csloop); | |
1589 | emit_move_insn (old, cmp); | |
1590 | ||
1591 | switch (code) | |
1592 | { | |
1593 | case PLUS: | |
1594 | case MINUS: | |
1595 | val = expand_simple_binop (SImode, code, old, orig, | |
1596 | NULL_RTX, 1, OPTAB_DIRECT); | |
1597 | val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
1598 | NULL_RTX, 1, OPTAB_DIRECT); | |
1599 | /* FALLTHRU */ | |
1600 | case SET: | |
1601 | tmp = expand_simple_binop (SImode, AND, old, ac.modemaski, | |
1602 | NULL_RTX, 1, OPTAB_DIRECT); | |
1603 | tmp = expand_simple_binop (SImode, IOR, tmp, val, | |
1604 | new_rtx, 1, OPTAB_DIRECT); | |
1605 | break; | |
1606 | ||
1607 | case AND: | |
1608 | case IOR: | |
1609 | case XOR: | |
1610 | tmp = expand_simple_binop (SImode, code, old, val, | |
1611 | new_rtx, 1, OPTAB_DIRECT); | |
1612 | break; | |
1613 | ||
1614 | case MULT: /* NAND */ | |
1615 | tmp = expand_simple_binop (SImode, XOR, old, ac.modemask, | |
1616 | NULL_RTX, 1, OPTAB_DIRECT); | |
1617 | tmp = expand_simple_binop (SImode, AND, tmp, val, | |
1618 | new_rtx, 1, OPTAB_DIRECT); | |
1619 | break; | |
1620 | ||
1621 | default: | |
1622 | gcc_unreachable (); | |
1623 | } | |
1624 | ||
1625 | if (tmp != new_rtx) | |
1626 | emit_move_insn (new_rtx, tmp); | |
1627 | emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx)); | |
1628 | emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop); | |
1629 | ||
1630 | if (target) | |
1631 | { | |
1632 | tmp = (after ? new_rtx : cmp); | |
1633 | convert_move (target, | |
1634 | (ac.shift == NULL_RTX ? tmp | |
1635 | : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift, | |
1636 | NULL_RTX, 1, OPTAB_DIRECT)), | |
1637 | 1); | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | ||
1642 | void | |
1643 | xtensa_setup_frame_addresses (void) | |
1644 | { | |
1645 | /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */ | |
1646 | cfun->machine->accesses_prev_frame = 1; | |
1647 | ||
1648 | if (TARGET_WINDOWED_ABI) | |
1649 | emit_library_call | |
1650 | (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"), | |
1651 | LCT_NORMAL, VOIDmode); | |
1652 | } | |
1653 | ||
1654 | ||
1655 | /* Emit the assembly for the end of a zero-cost loop. Normally we just emit | |
1656 | a comment showing where the end of the loop is. However, if there is a | |
1657 | label or a branch at the end of the loop then we need to place a nop | |
1658 | there. If the loop ends with a label we need the nop so that branches | |
1659 | targeting that label will target the nop (and thus remain in the loop), | |
1660 | instead of targeting the instruction after the loop (and thus exiting | |
1661 | the loop). If the loop ends with a branch, we need the nop in case the | |
1662 | branch is targeting a location inside the loop. When the branch | |
1663 | executes it will cause the loop count to be decremented even if it is | |
1664 | taken (because it is the last instruction in the loop), so we need to | |
1665 | nop after the branch to prevent the loop count from being decremented | |
1666 | when the branch is taken. */ | |
1667 | ||
1668 | void | |
1669 | xtensa_emit_loop_end (rtx_insn *insn, rtx *operands) | |
1670 | { | |
1671 | char done = 0; | |
1672 | ||
1673 | for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn)) | |
1674 | { | |
1675 | switch (GET_CODE (insn)) | |
1676 | { | |
1677 | case NOTE: | |
1678 | case BARRIER: | |
1679 | break; | |
1680 | ||
1681 | case CODE_LABEL: | |
1682 | output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); | |
1683 | done = 1; | |
1684 | break; | |
1685 | ||
1686 | default: | |
1687 | { | |
1688 | rtx body = PATTERN (insn); | |
1689 | ||
1690 | if (JUMP_P (body)) | |
1691 | { | |
1692 | output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); | |
1693 | done = 1; | |
1694 | } | |
1695 | else if ((GET_CODE (body) != USE) | |
1696 | && (GET_CODE (body) != CLOBBER)) | |
1697 | done = 1; | |
1698 | } | |
1699 | break; | |
1700 | } | |
1701 | } | |
1702 | ||
1703 | output_asm_insn ("%1_LEND:", operands); | |
1704 | } | |
1705 | ||
1706 | ||
1707 | char * | |
1708 | xtensa_emit_branch (bool inverted, bool immed, rtx *operands) | |
1709 | { | |
1710 | static char result[64]; | |
1711 | enum rtx_code code; | |
1712 | const char *op; | |
1713 | ||
1714 | code = GET_CODE (operands[3]); | |
1715 | switch (code) | |
1716 | { | |
1717 | case EQ: op = inverted ? "ne" : "eq"; break; | |
1718 | case NE: op = inverted ? "eq" : "ne"; break; | |
1719 | case LT: op = inverted ? "ge" : "lt"; break; | |
1720 | case GE: op = inverted ? "lt" : "ge"; break; | |
1721 | case LTU: op = inverted ? "geu" : "ltu"; break; | |
1722 | case GEU: op = inverted ? "ltu" : "geu"; break; | |
1723 | default: gcc_unreachable (); | |
1724 | } | |
1725 | ||
1726 | if (immed) | |
1727 | { | |
1728 | if (INTVAL (operands[1]) == 0) | |
1729 | sprintf (result, "b%sz%s\t%%0, %%2", op, | |
1730 | (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : ""); | |
1731 | else | |
1732 | sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
1733 | } | |
1734 | else | |
1735 | sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
1736 | ||
1737 | return result; | |
1738 | } | |
1739 | ||
1740 | ||
1741 | char * | |
1742 | xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands) | |
1743 | { | |
1744 | static char result[64]; | |
1745 | const char *op; | |
1746 | ||
1747 | switch (GET_CODE (operands[3])) | |
1748 | { | |
1749 | case EQ: op = inverted ? "bs" : "bc"; break; | |
1750 | case NE: op = inverted ? "bc" : "bs"; break; | |
1751 | default: gcc_unreachable (); | |
1752 | } | |
1753 | ||
1754 | if (immed) | |
1755 | { | |
1756 | unsigned bitnum = INTVAL (operands[1]) & 0x1f; | |
1757 | operands[1] = GEN_INT (bitnum); | |
1758 | sprintf (result, "b%si\t%%0, %%d1, %%2", op); | |
1759 | } | |
1760 | else | |
1761 | sprintf (result, "b%s\t%%0, %%1, %%2", op); | |
1762 | ||
1763 | return result; | |
1764 | } | |
1765 | ||
1766 | ||
1767 | char * | |
1768 | xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) | |
1769 | { | |
1770 | static char result[64]; | |
1771 | enum rtx_code code; | |
1772 | const char *op; | |
1773 | ||
1774 | code = GET_CODE (operands[4]); | |
1775 | if (isbool) | |
1776 | { | |
1777 | switch (code) | |
1778 | { | |
1779 | case EQ: op = inverted ? "t" : "f"; break; | |
1780 | case NE: op = inverted ? "f" : "t"; break; | |
1781 | default: gcc_unreachable (); | |
1782 | } | |
1783 | } | |
1784 | else | |
1785 | { | |
1786 | switch (code) | |
1787 | { | |
1788 | case EQ: op = inverted ? "nez" : "eqz"; break; | |
1789 | case NE: op = inverted ? "eqz" : "nez"; break; | |
1790 | case LT: op = inverted ? "gez" : "ltz"; break; | |
1791 | case GE: op = inverted ? "ltz" : "gez"; break; | |
1792 | default: gcc_unreachable (); | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | sprintf (result, "mov%s%s\t%%0, %%%d, %%1", | |
1797 | op, isfp ? ".s" : "", inverted ? 3 : 2); | |
1798 | return result; | |
1799 | } | |
1800 | ||
1801 | ||
1802 | char * | |
1803 | xtensa_emit_call (int callop, rtx *operands) | |
1804 | { | |
1805 | static char result[64]; | |
1806 | rtx tgt = operands[callop]; | |
1807 | ||
1808 | if (GET_CODE (tgt) == CONST_INT) | |
1809 | sprintf (result, "call%d\t" HOST_WIDE_INT_PRINT_HEX, | |
1810 | WINDOW_SIZE, INTVAL (tgt)); | |
1811 | else if (register_operand (tgt, VOIDmode)) | |
1812 | sprintf (result, "callx%d\t%%%d", WINDOW_SIZE, callop); | |
1813 | else | |
1814 | sprintf (result, "call%d\t%%%d", WINDOW_SIZE, callop); | |
1815 | ||
1816 | return result; | |
1817 | } | |
1818 | ||
1819 | ||
1820 | bool | |
1821 | xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict) | |
1822 | { | |
1823 | /* Allow constant pool addresses. */ | |
1824 | if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD | |
1825 | && ! TARGET_CONST16 && constantpool_address_p (addr) | |
1826 | && ! xtensa_tls_referenced_p (addr)) | |
1827 | return true; | |
1828 | ||
1829 | while (GET_CODE (addr) == SUBREG) | |
1830 | addr = SUBREG_REG (addr); | |
1831 | ||
1832 | /* Allow base registers. */ | |
1833 | if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict)) | |
1834 | return true; | |
1835 | ||
1836 | /* Check for "register + offset" addressing. */ | |
1837 | if (GET_CODE (addr) == PLUS) | |
1838 | { | |
1839 | rtx xplus0 = XEXP (addr, 0); | |
1840 | rtx xplus1 = XEXP (addr, 1); | |
1841 | enum rtx_code code0; | |
1842 | enum rtx_code code1; | |
1843 | ||
1844 | while (GET_CODE (xplus0) == SUBREG) | |
1845 | xplus0 = SUBREG_REG (xplus0); | |
1846 | code0 = GET_CODE (xplus0); | |
1847 | ||
1848 | while (GET_CODE (xplus1) == SUBREG) | |
1849 | xplus1 = SUBREG_REG (xplus1); | |
1850 | code1 = GET_CODE (xplus1); | |
1851 | ||
1852 | /* Swap operands if necessary so the register is first. */ | |
1853 | if (code0 != REG && code1 == REG) | |
1854 | { | |
1855 | xplus0 = XEXP (addr, 1); | |
1856 | xplus1 = XEXP (addr, 0); | |
1857 | code0 = GET_CODE (xplus0); | |
1858 | code1 = GET_CODE (xplus1); | |
1859 | } | |
1860 | ||
1861 | if (code0 == REG && BASE_REG_P (xplus0, strict) | |
1862 | && code1 == CONST_INT | |
1863 | && xtensa_mem_offset (INTVAL (xplus1), mode)) | |
1864 | return true; | |
1865 | } | |
1866 | ||
1867 | return false; | |
1868 | } | |
1869 | ||
1870 | ||
1871 | /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */ | |
1872 | ||
1873 | static GTY(()) rtx xtensa_tls_module_base_symbol; | |
1874 | ||
1875 | static rtx | |
1876 | xtensa_tls_module_base (void) | |
1877 | { | |
1878 | if (! xtensa_tls_module_base_symbol) | |
1879 | { | |
1880 | xtensa_tls_module_base_symbol = | |
1881 | gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_"); | |
1882 | SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol) | |
1883 | |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT; | |
1884 | } | |
1885 | ||
1886 | return xtensa_tls_module_base_symbol; | |
1887 | } | |
1888 | ||
1889 | ||
1890 | static rtx_insn * | |
1891 | xtensa_call_tls_desc (rtx sym, rtx *retp) | |
1892 | { | |
1893 | rtx fn, arg, a_io; | |
1894 | rtx_insn *call_insn, *insns; | |
1895 | ||
1896 | start_sequence (); | |
1897 | fn = gen_reg_rtx (Pmode); | |
1898 | arg = gen_reg_rtx (Pmode); | |
1899 | a_io = gen_rtx_REG (Pmode, WINDOW_SIZE + 2); | |
1900 | ||
1901 | emit_insn (gen_tls_func (fn, sym)); | |
1902 | emit_insn (gen_tls_arg (arg, sym)); | |
1903 | emit_move_insn (a_io, arg); | |
1904 | call_insn = emit_call_insn (gen_tls_call (a_io, fn, sym, const1_rtx)); | |
1905 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), a_io); | |
1906 | insns = get_insns (); | |
1907 | end_sequence (); | |
1908 | ||
1909 | *retp = a_io; | |
1910 | return insns; | |
1911 | } | |
1912 | ||
1913 | ||
1914 | static rtx | |
1915 | xtensa_legitimize_tls_address (rtx x) | |
1916 | { | |
1917 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); | |
1918 | rtx dest, tp, ret, modbase, base, addend; | |
1919 | rtx_insn *insns; | |
1920 | ||
1921 | dest = gen_reg_rtx (Pmode); | |
1922 | switch (model) | |
1923 | { | |
1924 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1925 | insns = xtensa_call_tls_desc (x, &ret); | |
1926 | emit_libcall_block (insns, dest, ret, x); | |
1927 | break; | |
1928 | ||
1929 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1930 | base = gen_reg_rtx (Pmode); | |
1931 | modbase = xtensa_tls_module_base (); | |
1932 | insns = xtensa_call_tls_desc (modbase, &ret); | |
1933 | emit_libcall_block (insns, base, ret, modbase); | |
1934 | addend = force_reg (SImode, gen_sym_DTPOFF (x)); | |
1935 | emit_insn (gen_addsi3 (dest, base, addend)); | |
1936 | break; | |
1937 | ||
1938 | case TLS_MODEL_INITIAL_EXEC: | |
1939 | case TLS_MODEL_LOCAL_EXEC: | |
1940 | tp = gen_reg_rtx (SImode); | |
1941 | emit_insn (gen_get_thread_pointersi (tp)); | |
1942 | addend = force_reg (SImode, gen_sym_TPOFF (x)); | |
1943 | emit_insn (gen_addsi3 (dest, tp, addend)); | |
1944 | break; | |
1945 | ||
1946 | default: | |
1947 | gcc_unreachable (); | |
1948 | } | |
1949 | ||
1950 | return dest; | |
1951 | } | |
1952 | ||
1953 | ||
1954 | rtx | |
1955 | xtensa_legitimize_address (rtx x, | |
1956 | rtx oldx ATTRIBUTE_UNUSED, | |
1957 | machine_mode mode) | |
1958 | { | |
1959 | if (xtensa_tls_symbol_p (x)) | |
1960 | return xtensa_legitimize_tls_address (x); | |
1961 | ||
1962 | if (GET_CODE (x) == PLUS) | |
1963 | { | |
1964 | rtx plus0 = XEXP (x, 0); | |
1965 | rtx plus1 = XEXP (x, 1); | |
1966 | ||
1967 | if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) | |
1968 | { | |
1969 | plus0 = XEXP (x, 1); | |
1970 | plus1 = XEXP (x, 0); | |
1971 | } | |
1972 | ||
1973 | /* Try to split up the offset to use an ADDMI instruction. */ | |
1974 | if (GET_CODE (plus0) == REG | |
1975 | && GET_CODE (plus1) == CONST_INT | |
1976 | && !xtensa_mem_offset (INTVAL (plus1), mode) | |
1977 | && !xtensa_simm8 (INTVAL (plus1)) | |
1978 | && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode) | |
1979 | && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) | |
1980 | { | |
1981 | rtx temp = gen_reg_rtx (Pmode); | |
1982 | rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff); | |
1983 | emit_insn (gen_rtx_SET (temp, gen_rtx_PLUS (Pmode, plus0, | |
1984 | addmi_offset))); | |
1985 | return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff)); | |
1986 | } | |
1987 | } | |
1988 | ||
1989 | return x; | |
1990 | } | |
1991 | ||
1992 | /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. | |
1993 | ||
1994 | Treat constant-pool references as "mode dependent" since they can | |
1995 | only be accessed with SImode loads. This works around a bug in the | |
1996 | combiner where a constant pool reference is temporarily converted | |
1997 | to an HImode load, which is then assumed to zero-extend based on | |
1998 | our definition of LOAD_EXTEND_OP. This is wrong because the high | |
1999 | bits of a 16-bit value in the constant pool are now sign-extended | |
2000 | by default. */ | |
2001 | ||
2002 | static bool | |
2003 | xtensa_mode_dependent_address_p (const_rtx addr, | |
2004 | addr_space_t as ATTRIBUTE_UNUSED) | |
2005 | { | |
2006 | return constantpool_address_p (addr); | |
2007 | } | |
2008 | ||
2009 | /* Return TRUE if X contains any TLS symbol references. */ | |
2010 | ||
2011 | bool | |
2012 | xtensa_tls_referenced_p (rtx x) | |
2013 | { | |
2014 | if (! TARGET_HAVE_TLS) | |
2015 | return false; | |
2016 | ||
2017 | subrtx_iterator::array_type array; | |
2018 | FOR_EACH_SUBRTX (iter, array, x, ALL) | |
2019 | { | |
2020 | const_rtx x = *iter; | |
2021 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) | |
2022 | return true; | |
2023 | ||
2024 | /* Ignore TLS references that have already been legitimized. */ | |
2025 | if (GET_CODE (x) == UNSPEC) | |
2026 | switch (XINT (x, 1)) | |
2027 | { | |
2028 | case UNSPEC_TPOFF: | |
2029 | case UNSPEC_DTPOFF: | |
2030 | case UNSPEC_TLS_FUNC: | |
2031 | case UNSPEC_TLS_ARG: | |
2032 | case UNSPEC_TLS_CALL: | |
2033 | iter.skip_subrtxes (); | |
2034 | break; | |
2035 | default: | |
2036 | break; | |
2037 | } | |
2038 | } | |
2039 | return false; | |
2040 | } | |
2041 | ||
2042 | ||
2043 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
2044 | ||
2045 | static bool | |
2046 | xtensa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
2047 | { | |
2048 | return xtensa_tls_referenced_p (x); | |
2049 | } | |
2050 | ||
2051 | ||
2052 | /* Return the debugger register number to use for 'regno'. */ | |
2053 | ||
2054 | int | |
2055 | xtensa_dbx_register_number (int regno) | |
2056 | { | |
2057 | int first = -1; | |
2058 | ||
2059 | if (GP_REG_P (regno)) | |
2060 | { | |
2061 | regno -= GP_REG_FIRST; | |
2062 | first = 0; | |
2063 | } | |
2064 | else if (BR_REG_P (regno)) | |
2065 | { | |
2066 | regno -= BR_REG_FIRST; | |
2067 | first = 16; | |
2068 | } | |
2069 | else if (FP_REG_P (regno)) | |
2070 | { | |
2071 | regno -= FP_REG_FIRST; | |
2072 | first = 48; | |
2073 | } | |
2074 | else if (ACC_REG_P (regno)) | |
2075 | { | |
2076 | first = 0x200; /* Start of Xtensa special registers. */ | |
2077 | regno = 16; /* ACCLO is special register 16. */ | |
2078 | } | |
2079 | ||
2080 | /* When optimizing, we sometimes get asked about pseudo-registers | |
2081 | that don't represent hard registers. Return 0 for these. */ | |
2082 | if (first == -1) | |
2083 | return 0; | |
2084 | ||
2085 | return first + regno; | |
2086 | } | |
2087 | ||
2088 | ||
2089 | /* Argument support functions. */ | |
2090 | ||
2091 | /* Initialize CUMULATIVE_ARGS for a function. */ | |
2092 | ||
2093 | void | |
2094 | init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming) | |
2095 | { | |
2096 | cum->arg_words = 0; | |
2097 | cum->incoming = incoming; | |
2098 | } | |
2099 | ||
2100 | ||
2101 | /* Advance the argument to the next argument position. */ | |
2102 | ||
2103 | static void | |
2104 | xtensa_function_arg_advance (cumulative_args_t cum, machine_mode mode, | |
2105 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
2106 | { | |
2107 | int words, max; | |
2108 | int *arg_words; | |
2109 | ||
2110 | arg_words = &get_cumulative_args (cum)->arg_words; | |
2111 | max = MAX_ARGS_IN_REGISTERS; | |
2112 | ||
2113 | words = (((mode != BLKmode) | |
2114 | ? (int) GET_MODE_SIZE (mode) | |
2115 | : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2116 | ||
2117 | if (*arg_words < max | |
2118 | && (targetm.calls.must_pass_in_stack (mode, type) | |
2119 | || *arg_words + words > max)) | |
2120 | *arg_words = max; | |
2121 | ||
2122 | *arg_words += words; | |
2123 | } | |
2124 | ||
2125 | ||
2126 | /* Return an RTL expression containing the register for the given mode, | |
2127 | or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero | |
2128 | if this is an incoming argument to the current function. */ | |
2129 | ||
2130 | static rtx | |
2131 | xtensa_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, | |
2132 | const_tree type, bool incoming_p) | |
2133 | { | |
2134 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); | |
2135 | int regbase, words, max; | |
2136 | int *arg_words; | |
2137 | int regno; | |
2138 | ||
2139 | arg_words = &cum->arg_words; | |
2140 | regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST); | |
2141 | max = MAX_ARGS_IN_REGISTERS; | |
2142 | ||
2143 | words = (((mode != BLKmode) | |
2144 | ? (int) GET_MODE_SIZE (mode) | |
2145 | : int_size_in_bytes (type)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2146 | ||
2147 | if (type && (TYPE_ALIGN (type) > BITS_PER_WORD)) | |
2148 | { | |
2149 | int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_WORD; | |
2150 | *arg_words = (*arg_words + align - 1) & -align; | |
2151 | } | |
2152 | ||
2153 | if (*arg_words + words > max) | |
2154 | return (rtx)0; | |
2155 | ||
2156 | regno = regbase + *arg_words; | |
2157 | ||
2158 | if (cum->incoming && regno <= A7_REG && regno + words > A7_REG) | |
2159 | cfun->machine->need_a7_copy = TARGET_WINDOWED_ABI; | |
2160 | ||
2161 | return gen_rtx_REG (mode, regno); | |
2162 | } | |
2163 | ||
2164 | /* Implement TARGET_FUNCTION_ARG. */ | |
2165 | ||
2166 | static rtx | |
2167 | xtensa_function_arg (cumulative_args_t cum, machine_mode mode, | |
2168 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
2169 | { | |
2170 | return xtensa_function_arg_1 (cum, mode, type, false); | |
2171 | } | |
2172 | ||
2173 | /* Implement TARGET_FUNCTION_INCOMING_ARG. */ | |
2174 | ||
2175 | static rtx | |
2176 | xtensa_function_incoming_arg (cumulative_args_t cum, machine_mode mode, | |
2177 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
2178 | { | |
2179 | return xtensa_function_arg_1 (cum, mode, type, true); | |
2180 | } | |
2181 | ||
2182 | static unsigned int | |
2183 | xtensa_function_arg_boundary (machine_mode mode, const_tree type) | |
2184 | { | |
2185 | unsigned int alignment; | |
2186 | ||
2187 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
2188 | if (alignment < PARM_BOUNDARY) | |
2189 | alignment = PARM_BOUNDARY; | |
2190 | if (alignment > STACK_BOUNDARY) | |
2191 | alignment = STACK_BOUNDARY; | |
2192 | return alignment; | |
2193 | } | |
2194 | ||
2195 | ||
2196 | static bool | |
2197 | xtensa_return_in_msb (const_tree valtype) | |
2198 | { | |
2199 | return (TARGET_BIG_ENDIAN | |
2200 | && AGGREGATE_TYPE_P (valtype) | |
2201 | && int_size_in_bytes (valtype) >= UNITS_PER_WORD); | |
2202 | } | |
2203 | ||
2204 | ||
2205 | static void | |
2206 | xtensa_option_override (void) | |
2207 | { | |
2208 | int regno; | |
2209 | machine_mode mode; | |
2210 | ||
2211 | /* Use CONST16 in the absence of L32R. | |
2212 | Set it in the TARGET_OPTION_OVERRIDE to avoid dependency on xtensa | |
2213 | configuration in the xtensa-common.c */ | |
2214 | ||
2215 | if (!TARGET_L32R) | |
2216 | target_flags |= MASK_CONST16; | |
2217 | ||
2218 | if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT) | |
2219 | error ("boolean registers required for the floating-point option"); | |
2220 | ||
2221 | /* Set up array giving whether a given register can hold a given mode. */ | |
2222 | for (mode = VOIDmode; | |
2223 | mode != MAX_MACHINE_MODE; | |
2224 | mode = (machine_mode) ((int) mode + 1)) | |
2225 | { | |
2226 | int size = GET_MODE_SIZE (mode); | |
2227 | enum mode_class mclass = GET_MODE_CLASS (mode); | |
2228 | ||
2229 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
2230 | { | |
2231 | int temp; | |
2232 | ||
2233 | if (ACC_REG_P (regno)) | |
2234 | temp = (TARGET_MAC16 | |
2235 | && (mclass == MODE_INT) && (size <= UNITS_PER_WORD)); | |
2236 | else if (GP_REG_P (regno)) | |
2237 | temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); | |
2238 | else if (FP_REG_P (regno)) | |
2239 | temp = (TARGET_HARD_FLOAT && (mode == SFmode)); | |
2240 | else if (BR_REG_P (regno)) | |
2241 | temp = (TARGET_BOOLEANS && (mode == CCmode)); | |
2242 | else | |
2243 | temp = FALSE; | |
2244 | ||
2245 | xtensa_hard_regno_mode_ok_p[(int) mode][regno] = temp; | |
2246 | } | |
2247 | } | |
2248 | ||
2249 | init_machine_status = xtensa_init_machine_status; | |
2250 | ||
2251 | /* Check PIC settings. PIC is only supported when using L32R | |
2252 | instructions, and some targets need to always use PIC. */ | |
2253 | if (flag_pic && TARGET_CONST16) | |
2254 | error ("-f%s is not supported with CONST16 instructions", | |
2255 | (flag_pic > 1 ? "PIC" : "pic")); | |
2256 | else if (TARGET_FORCE_NO_PIC) | |
2257 | flag_pic = 0; | |
2258 | else if (XTENSA_ALWAYS_PIC) | |
2259 | { | |
2260 | if (TARGET_CONST16) | |
2261 | error ("PIC is required but not supported with CONST16 instructions"); | |
2262 | flag_pic = 1; | |
2263 | } | |
2264 | /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */ | |
2265 | if (flag_pic > 1) | |
2266 | flag_pic = 1; | |
2267 | if (flag_pic && !flag_pie) | |
2268 | flag_shlib = 1; | |
2269 | ||
2270 | /* Hot/cold partitioning does not work on this architecture, because of | |
2271 | constant pools (the load instruction cannot necessarily reach that far). | |
2272 | Therefore disable it on this architecture. */ | |
2273 | if (flag_reorder_blocks_and_partition) | |
2274 | { | |
2275 | flag_reorder_blocks_and_partition = 0; | |
2276 | flag_reorder_blocks = 1; | |
2277 | } | |
2278 | } | |
2279 | ||
2280 | /* Implement TARGET_HARD_REGNO_NREGS. */ | |
2281 | ||
2282 | static unsigned int | |
2283 | xtensa_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
2284 | { | |
2285 | if (FP_REG_P (regno)) | |
2286 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_FPREG); | |
2287 | return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); | |
2288 | } | |
2289 | ||
2290 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ | |
2291 | ||
2292 | static bool | |
2293 | xtensa_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
2294 | { | |
2295 | return xtensa_hard_regno_mode_ok_p[mode][regno]; | |
2296 | } | |
2297 | ||
2298 | /* Implement TARGET_MODES_TIEABLE_P. */ | |
2299 | ||
2300 | static bool | |
2301 | xtensa_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
2302 | { | |
2303 | return ((GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2304 | || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT) | |
2305 | == (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2306 | || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT)); | |
2307 | } | |
2308 | ||
2309 | /* A C compound statement to output to stdio stream STREAM the | |
2310 | assembler syntax for an instruction operand X. X is an RTL | |
2311 | expression. | |
2312 | ||
2313 | CODE is a value that can be used to specify one of several ways | |
2314 | of printing the operand. It is used when identical operands | |
2315 | must be printed differently depending on the context. CODE | |
2316 | comes from the '%' specification that was used to request | |
2317 | printing of the operand. If the specification was just '%DIGIT' | |
2318 | then CODE is 0; if the specification was '%LTR DIGIT' then CODE | |
2319 | is the ASCII code for LTR. | |
2320 | ||
2321 | If X is a register, this macro should print the register's name. | |
2322 | The names can be found in an array 'reg_names' whose type is | |
2323 | 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'. | |
2324 | ||
2325 | When the machine description has a specification '%PUNCT' (a '%' | |
2326 | followed by a punctuation character), this macro is called with | |
2327 | a null pointer for X and the punctuation character for CODE. | |
2328 | ||
2329 | 'a', 'c', 'l', and 'n' are reserved. | |
2330 | ||
2331 | The Xtensa specific codes are: | |
2332 | ||
2333 | 'd' CONST_INT, print as signed decimal | |
2334 | 'x' CONST_INT, print as signed hexadecimal | |
2335 | 'K' CONST_INT, print number of bits in mask for EXTUI | |
2336 | 'R' CONST_INT, print (X & 0x1f) | |
2337 | 'L' CONST_INT, print ((32 - X) & 0x1f) | |
2338 | 'D' REG, print second register of double-word register operand | |
2339 | 'N' MEM, print address of next word following a memory operand | |
2340 | 'v' MEM, if memory reference is volatile, output a MEMW before it | |
2341 | 't' any constant, add "@h" suffix for top 16 bits | |
2342 | 'b' any constant, add "@l" suffix for bottom 16 bits | |
2343 | */ | |
2344 | ||
2345 | static void | |
2346 | printx (FILE *file, signed int val) | |
2347 | { | |
2348 | /* Print a hexadecimal value in a nice way. */ | |
2349 | if ((val > -0xa) && (val < 0xa)) | |
2350 | fprintf (file, "%d", val); | |
2351 | else if (val < 0) | |
2352 | fprintf (file, "-0x%x", -val); | |
2353 | else | |
2354 | fprintf (file, "0x%x", val); | |
2355 | } | |
2356 | ||
2357 | ||
2358 | void | |
2359 | print_operand (FILE *file, rtx x, int letter) | |
2360 | { | |
2361 | if (!x) | |
2362 | error ("PRINT_OPERAND null pointer"); | |
2363 | ||
2364 | switch (letter) | |
2365 | { | |
2366 | case 'D': | |
2367 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
2368 | fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]); | |
2369 | else | |
2370 | output_operand_lossage ("invalid %%D value"); | |
2371 | break; | |
2372 | ||
2373 | case 'v': | |
2374 | if (GET_CODE (x) == MEM) | |
2375 | { | |
2376 | /* For a volatile memory reference, emit a MEMW before the | |
2377 | load or store. */ | |
2378 | if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) | |
2379 | fprintf (file, "memw\n\t"); | |
2380 | } | |
2381 | else | |
2382 | output_operand_lossage ("invalid %%v value"); | |
2383 | break; | |
2384 | ||
2385 | case 'N': | |
2386 | if (GET_CODE (x) == MEM | |
2387 | && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)) | |
2388 | { | |
2389 | x = adjust_address (x, GET_MODE (x) == DFmode ? E_SFmode : E_SImode, | |
2390 | 4); | |
2391 | output_address (GET_MODE (x), XEXP (x, 0)); | |
2392 | } | |
2393 | else | |
2394 | output_operand_lossage ("invalid %%N value"); | |
2395 | break; | |
2396 | ||
2397 | case 'K': | |
2398 | if (GET_CODE (x) == CONST_INT) | |
2399 | { | |
2400 | int num_bits = 0; | |
2401 | unsigned val = INTVAL (x); | |
2402 | while (val & 1) | |
2403 | { | |
2404 | num_bits += 1; | |
2405 | val = val >> 1; | |
2406 | } | |
2407 | if ((val != 0) || (num_bits == 0) || (num_bits > 16)) | |
2408 | fatal_insn ("invalid mask", x); | |
2409 | ||
2410 | fprintf (file, "%d", num_bits); | |
2411 | } | |
2412 | else | |
2413 | output_operand_lossage ("invalid %%K value"); | |
2414 | break; | |
2415 | ||
2416 | case 'L': | |
2417 | if (GET_CODE (x) == CONST_INT) | |
2418 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 0x1f); | |
2419 | else | |
2420 | output_operand_lossage ("invalid %%L value"); | |
2421 | break; | |
2422 | ||
2423 | case 'R': | |
2424 | if (GET_CODE (x) == CONST_INT) | |
2425 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x1f); | |
2426 | else | |
2427 | output_operand_lossage ("invalid %%R value"); | |
2428 | break; | |
2429 | ||
2430 | case 'x': | |
2431 | if (GET_CODE (x) == CONST_INT) | |
2432 | printx (file, INTVAL (x)); | |
2433 | else | |
2434 | output_operand_lossage ("invalid %%x value"); | |
2435 | break; | |
2436 | ||
2437 | case 'd': | |
2438 | if (GET_CODE (x) == CONST_INT) | |
2439 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
2440 | else | |
2441 | output_operand_lossage ("invalid %%d value"); | |
2442 | break; | |
2443 | ||
2444 | case 't': | |
2445 | case 'b': | |
2446 | if (GET_CODE (x) == CONST_INT) | |
2447 | { | |
2448 | printx (file, INTVAL (x)); | |
2449 | fputs (letter == 't' ? "@h" : "@l", file); | |
2450 | } | |
2451 | else if (GET_CODE (x) == CONST_DOUBLE) | |
2452 | { | |
2453 | if (GET_MODE (x) == SFmode) | |
2454 | { | |
2455 | long l; | |
2456 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); | |
2457 | fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l'); | |
2458 | } | |
2459 | else | |
2460 | output_operand_lossage ("invalid %%t/%%b value"); | |
2461 | } | |
2462 | else if (GET_CODE (x) == CONST) | |
2463 | { | |
2464 | /* X must be a symbolic constant on ELF. Write an expression | |
2465 | suitable for 'const16' that sets the high or low 16 bits. */ | |
2466 | if (GET_CODE (XEXP (x, 0)) != PLUS | |
2467 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF | |
2468 | && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) | |
2469 | || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
2470 | output_operand_lossage ("invalid %%t/%%b value"); | |
2471 | print_operand (file, XEXP (XEXP (x, 0), 0), 0); | |
2472 | fputs (letter == 't' ? "@h" : "@l", file); | |
2473 | /* There must be a non-alphanumeric character between 'h' or 'l' | |
2474 | and the number. The '-' is added by print_operand() already. */ | |
2475 | if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) | |
2476 | fputs ("+", file); | |
2477 | print_operand (file, XEXP (XEXP (x, 0), 1), 0); | |
2478 | } | |
2479 | else | |
2480 | { | |
2481 | output_addr_const (file, x); | |
2482 | fputs (letter == 't' ? "@h" : "@l", file); | |
2483 | } | |
2484 | break; | |
2485 | ||
2486 | case 'y': | |
2487 | if (GET_CODE (x) == CONST_DOUBLE && | |
2488 | GET_MODE (x) == SFmode) | |
2489 | { | |
2490 | long l; | |
2491 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); | |
2492 | fprintf (file, "0x%08lx", l); | |
2493 | break; | |
2494 | } | |
2495 | ||
2496 | /* fall through */ | |
2497 | ||
2498 | default: | |
2499 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
2500 | fprintf (file, "%s", reg_names[xt_true_regnum (x)]); | |
2501 | else if (GET_CODE (x) == MEM) | |
2502 | output_address (GET_MODE (x), XEXP (x, 0)); | |
2503 | else if (GET_CODE (x) == CONST_INT) | |
2504 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
2505 | else | |
2506 | output_addr_const (file, x); | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | ||
2511 | /* A C compound statement to output to stdio stream STREAM the | |
2512 | assembler syntax for an instruction operand that is a memory | |
2513 | reference whose address is ADDR. ADDR is an RTL expression. */ | |
2514 | ||
2515 | void | |
2516 | print_operand_address (FILE *file, rtx addr) | |
2517 | { | |
2518 | if (!addr) | |
2519 | error ("PRINT_OPERAND_ADDRESS, null pointer"); | |
2520 | ||
2521 | switch (GET_CODE (addr)) | |
2522 | { | |
2523 | default: | |
2524 | fatal_insn ("invalid address", addr); | |
2525 | break; | |
2526 | ||
2527 | case REG: | |
2528 | fprintf (file, "%s, 0", reg_names [REGNO (addr)]); | |
2529 | break; | |
2530 | ||
2531 | case PLUS: | |
2532 | { | |
2533 | rtx reg = (rtx)0; | |
2534 | rtx offset = (rtx)0; | |
2535 | rtx arg0 = XEXP (addr, 0); | |
2536 | rtx arg1 = XEXP (addr, 1); | |
2537 | ||
2538 | if (GET_CODE (arg0) == REG) | |
2539 | { | |
2540 | reg = arg0; | |
2541 | offset = arg1; | |
2542 | } | |
2543 | else if (GET_CODE (arg1) == REG) | |
2544 | { | |
2545 | reg = arg1; | |
2546 | offset = arg0; | |
2547 | } | |
2548 | else | |
2549 | fatal_insn ("no register in address", addr); | |
2550 | ||
2551 | if (CONSTANT_P (offset)) | |
2552 | { | |
2553 | fprintf (file, "%s, ", reg_names [REGNO (reg)]); | |
2554 | output_addr_const (file, offset); | |
2555 | } | |
2556 | else | |
2557 | fatal_insn ("address offset not a constant", addr); | |
2558 | } | |
2559 | break; | |
2560 | ||
2561 | case LABEL_REF: | |
2562 | case SYMBOL_REF: | |
2563 | case CONST_INT: | |
2564 | case CONST: | |
2565 | output_addr_const (file, addr); | |
2566 | break; | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ | |
2571 | ||
2572 | static bool | |
2573 | xtensa_output_addr_const_extra (FILE *fp, rtx x) | |
2574 | { | |
2575 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) | |
2576 | { | |
2577 | switch (XINT (x, 1)) | |
2578 | { | |
2579 | case UNSPEC_TPOFF: | |
2580 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2581 | fputs ("@TPOFF", fp); | |
2582 | return true; | |
2583 | case UNSPEC_DTPOFF: | |
2584 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2585 | fputs ("@DTPOFF", fp); | |
2586 | return true; | |
2587 | case UNSPEC_PLT: | |
2588 | if (flag_pic) | |
2589 | { | |
2590 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
2591 | fputs ("@PLT", fp); | |
2592 | return true; | |
2593 | } | |
2594 | break; | |
2595 | default: | |
2596 | break; | |
2597 | } | |
2598 | } | |
2599 | return false; | |
2600 | } | |
2601 | ||
2602 | static void | |
2603 | xtensa_output_integer_literal_parts (FILE *file, rtx x, int size) | |
2604 | { | |
2605 | if (size > 4 && !(size & (size - 1))) | |
2606 | { | |
2607 | rtx first, second; | |
2608 | ||
2609 | split_double (x, &first, &second); | |
2610 | xtensa_output_integer_literal_parts (file, first, size / 2); | |
2611 | fputs (", ", file); | |
2612 | xtensa_output_integer_literal_parts (file, second, size / 2); | |
2613 | } | |
2614 | else if (size == 4) | |
2615 | { | |
2616 | output_addr_const (file, x); | |
2617 | } | |
2618 | else | |
2619 | { | |
2620 | gcc_unreachable(); | |
2621 | } | |
2622 | } | |
2623 | ||
2624 | void | |
2625 | xtensa_output_literal (FILE *file, rtx x, machine_mode mode, int labelno) | |
2626 | { | |
2627 | long value_long[2]; | |
2628 | ||
2629 | fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno); | |
2630 | ||
2631 | switch (GET_MODE_CLASS (mode)) | |
2632 | { | |
2633 | case MODE_FLOAT: | |
2634 | gcc_assert (GET_CODE (x) == CONST_DOUBLE); | |
2635 | ||
2636 | switch (mode) | |
2637 | { | |
2638 | case E_SFmode: | |
2639 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), | |
2640 | value_long[0]); | |
2641 | if (HOST_BITS_PER_LONG > 32) | |
2642 | value_long[0] &= 0xffffffff; | |
2643 | fprintf (file, "0x%08lx\n", value_long[0]); | |
2644 | break; | |
2645 | ||
2646 | case E_DFmode: | |
2647 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), | |
2648 | value_long); | |
2649 | if (HOST_BITS_PER_LONG > 32) | |
2650 | { | |
2651 | value_long[0] &= 0xffffffff; | |
2652 | value_long[1] &= 0xffffffff; | |
2653 | } | |
2654 | fprintf (file, "0x%08lx, 0x%08lx\n", | |
2655 | value_long[0], value_long[1]); | |
2656 | break; | |
2657 | ||
2658 | default: | |
2659 | gcc_unreachable (); | |
2660 | } | |
2661 | ||
2662 | break; | |
2663 | ||
2664 | case MODE_INT: | |
2665 | case MODE_PARTIAL_INT: | |
2666 | xtensa_output_integer_literal_parts (file, x, GET_MODE_SIZE (mode)); | |
2667 | fputs ("\n", file); | |
2668 | break; | |
2669 | ||
2670 | default: | |
2671 | gcc_unreachable (); | |
2672 | } | |
2673 | } | |
2674 | ||
2675 | static bool | |
2676 | xtensa_call_save_reg(int regno) | |
2677 | { | |
2678 | if (TARGET_WINDOWED_ABI) | |
2679 | return false; | |
2680 | ||
2681 | if (regno == A0_REG) | |
2682 | return crtl->profile || !crtl->is_leaf || crtl->calls_eh_return || | |
2683 | df_regs_ever_live_p (regno); | |
2684 | ||
2685 | if (crtl->calls_eh_return && regno >= 2 && regno < 4) | |
2686 | return true; | |
2687 | ||
2688 | return !fixed_regs[regno] && !call_used_regs[regno] && | |
2689 | df_regs_ever_live_p (regno); | |
2690 | } | |
2691 | ||
2692 | /* Return the bytes needed to compute the frame pointer from the current | |
2693 | stack pointer. */ | |
2694 | ||
2695 | #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) | |
2696 | #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1)) | |
2697 | ||
2698 | long | |
2699 | compute_frame_size (int size) | |
2700 | { | |
2701 | int regno; | |
2702 | ||
2703 | if (reload_completed && cfun->machine->frame_laid_out) | |
2704 | return cfun->machine->current_frame_size; | |
2705 | ||
2706 | /* Add space for the incoming static chain value. */ | |
2707 | if (cfun->static_chain_decl != NULL) | |
2708 | size += (1 * UNITS_PER_WORD); | |
2709 | ||
2710 | cfun->machine->callee_save_size = 0; | |
2711 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) | |
2712 | { | |
2713 | if (xtensa_call_save_reg(regno)) | |
2714 | cfun->machine->callee_save_size += UNITS_PER_WORD; | |
2715 | } | |
2716 | ||
2717 | cfun->machine->current_frame_size = | |
2718 | XTENSA_STACK_ALIGN (size | |
2719 | + cfun->machine->callee_save_size | |
2720 | + crtl->outgoing_args_size | |
2721 | + (WINDOW_SIZE * UNITS_PER_WORD)); | |
2722 | cfun->machine->callee_save_size = | |
2723 | XTENSA_STACK_ALIGN (cfun->machine->callee_save_size); | |
2724 | cfun->machine->frame_laid_out = true; | |
2725 | return cfun->machine->current_frame_size; | |
2726 | } | |
2727 | ||
2728 | ||
2729 | bool | |
2730 | xtensa_frame_pointer_required (void) | |
2731 | { | |
2732 | /* The code to expand builtin_frame_addr and builtin_return_addr | |
2733 | currently uses the hard_frame_pointer instead of frame_pointer. | |
2734 | This seems wrong but maybe it's necessary for other architectures. | |
2735 | This function is derived from the i386 code. */ | |
2736 | ||
2737 | if (cfun->machine->accesses_prev_frame) | |
2738 | return true; | |
2739 | ||
2740 | return false; | |
2741 | } | |
2742 | ||
2743 | HOST_WIDE_INT | |
2744 | xtensa_initial_elimination_offset (int from, int to ATTRIBUTE_UNUSED) | |
2745 | { | |
2746 | long frame_size = compute_frame_size (get_frame_size ()); | |
2747 | HOST_WIDE_INT offset; | |
2748 | ||
2749 | switch (from) | |
2750 | { | |
2751 | case FRAME_POINTER_REGNUM: | |
2752 | if (FRAME_GROWS_DOWNWARD) | |
2753 | offset = frame_size - (WINDOW_SIZE * UNITS_PER_WORD) | |
2754 | - cfun->machine->callee_save_size; | |
2755 | else | |
2756 | offset = 0; | |
2757 | break; | |
2758 | case ARG_POINTER_REGNUM: | |
2759 | offset = frame_size; | |
2760 | break; | |
2761 | default: | |
2762 | gcc_unreachable (); | |
2763 | } | |
2764 | ||
2765 | return offset; | |
2766 | } | |
2767 | ||
2768 | /* minimum frame = reg save area (4 words) plus static chain (1 word) | |
2769 | and the total number of words must be a multiple of 128 bits. */ | |
2770 | #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) | |
2771 | ||
2772 | void | |
2773 | xtensa_expand_prologue (void) | |
2774 | { | |
2775 | HOST_WIDE_INT total_size; | |
2776 | rtx_insn *insn = NULL; | |
2777 | rtx note_rtx; | |
2778 | ||
2779 | ||
2780 | total_size = compute_frame_size (get_frame_size ()); | |
2781 | ||
2782 | if (flag_stack_usage_info) | |
2783 | current_function_static_stack_size = total_size; | |
2784 | ||
2785 | if (TARGET_WINDOWED_ABI) | |
2786 | { | |
2787 | if (total_size < (1 << (12+3))) | |
2788 | insn = emit_insn (gen_entry (GEN_INT (total_size))); | |
2789 | else | |
2790 | { | |
2791 | /* Use a8 as a temporary since a0-a7 may be live. */ | |
2792 | rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG); | |
2793 | emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE))); | |
2794 | emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE)); | |
2795 | emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg)); | |
2796 | insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg)); | |
2797 | } | |
2798 | } | |
2799 | else | |
2800 | { | |
2801 | int regno; | |
2802 | HOST_WIDE_INT offset = 0; | |
2803 | int callee_save_size = cfun->machine->callee_save_size; | |
2804 | ||
2805 | /* -128 is a limit of single addi instruction. */ | |
2806 | if (total_size > 0 && total_size <= 128) | |
2807 | { | |
2808 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
2809 | GEN_INT (-total_size))); | |
2810 | RTX_FRAME_RELATED_P (insn) = 1; | |
2811 | note_rtx = gen_rtx_SET (stack_pointer_rtx, | |
2812 | plus_constant (Pmode, stack_pointer_rtx, | |
2813 | -total_size)); | |
2814 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2815 | offset = total_size - UNITS_PER_WORD; | |
2816 | } | |
2817 | else if (callee_save_size) | |
2818 | { | |
2819 | /* 1020 is maximal s32i offset, if the frame is bigger than that | |
2820 | * we move sp to the end of callee-saved save area, save and then | |
2821 | * move it to its final location. */ | |
2822 | if (total_size > 1024) | |
2823 | { | |
2824 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
2825 | GEN_INT (-callee_save_size))); | |
2826 | RTX_FRAME_RELATED_P (insn) = 1; | |
2827 | note_rtx = gen_rtx_SET (stack_pointer_rtx, | |
2828 | plus_constant (Pmode, stack_pointer_rtx, | |
2829 | -callee_save_size)); | |
2830 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2831 | offset = callee_save_size - UNITS_PER_WORD; | |
2832 | } | |
2833 | else | |
2834 | { | |
2835 | rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); | |
2836 | emit_move_insn (tmp_reg, GEN_INT (total_size)); | |
2837 | insn = emit_insn (gen_subsi3 (stack_pointer_rtx, | |
2838 | stack_pointer_rtx, tmp_reg)); | |
2839 | RTX_FRAME_RELATED_P (insn) = 1; | |
2840 | note_rtx = gen_rtx_SET (stack_pointer_rtx, | |
2841 | plus_constant (Pmode, stack_pointer_rtx, | |
2842 | -total_size)); | |
2843 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2844 | offset = total_size - UNITS_PER_WORD; | |
2845 | } | |
2846 | } | |
2847 | ||
2848 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) | |
2849 | { | |
2850 | if (xtensa_call_save_reg(regno)) | |
2851 | { | |
2852 | rtx x = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); | |
2853 | rtx mem = gen_frame_mem (SImode, x); | |
2854 | rtx reg = gen_rtx_REG (SImode, regno); | |
2855 | ||
2856 | offset -= UNITS_PER_WORD; | |
2857 | insn = emit_move_insn (mem, reg); | |
2858 | RTX_FRAME_RELATED_P (insn) = 1; | |
2859 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
2860 | gen_rtx_SET (mem, reg)); | |
2861 | } | |
2862 | } | |
2863 | if (total_size > 1024) | |
2864 | { | |
2865 | rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); | |
2866 | emit_move_insn (tmp_reg, GEN_INT (total_size - | |
2867 | callee_save_size)); | |
2868 | insn = emit_insn (gen_subsi3 (stack_pointer_rtx, | |
2869 | stack_pointer_rtx, tmp_reg)); | |
2870 | RTX_FRAME_RELATED_P (insn) = 1; | |
2871 | note_rtx = gen_rtx_SET (stack_pointer_rtx, | |
2872 | plus_constant (Pmode, stack_pointer_rtx, | |
2873 | callee_save_size - | |
2874 | total_size)); | |
2875 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2876 | } | |
2877 | } | |
2878 | ||
2879 | if (frame_pointer_needed) | |
2880 | { | |
2881 | if (cfun->machine->set_frame_ptr_insn) | |
2882 | { | |
2883 | rtx_insn *first; | |
2884 | ||
2885 | push_topmost_sequence (); | |
2886 | first = get_insns (); | |
2887 | pop_topmost_sequence (); | |
2888 | ||
2889 | /* For all instructions prior to set_frame_ptr_insn, replace | |
2890 | hard_frame_pointer references with stack_pointer. */ | |
2891 | for (insn = first; | |
2892 | insn != cfun->machine->set_frame_ptr_insn; | |
2893 | insn = NEXT_INSN (insn)) | |
2894 | { | |
2895 | if (INSN_P (insn)) | |
2896 | { | |
2897 | PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)), | |
2898 | hard_frame_pointer_rtx, | |
2899 | stack_pointer_rtx); | |
2900 | df_insn_rescan (insn); | |
2901 | } | |
2902 | } | |
2903 | } | |
2904 | else | |
2905 | { | |
2906 | insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, | |
2907 | stack_pointer_rtx)); | |
2908 | if (!TARGET_WINDOWED_ABI) | |
2909 | { | |
2910 | note_rtx = gen_rtx_SET (hard_frame_pointer_rtx, | |
2911 | stack_pointer_rtx); | |
2912 | RTX_FRAME_RELATED_P (insn) = 1; | |
2913 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2914 | } | |
2915 | } | |
2916 | } | |
2917 | ||
2918 | if (TARGET_WINDOWED_ABI) | |
2919 | { | |
2920 | /* Create a note to describe the CFA. Because this is only used to set | |
2921 | DW_AT_frame_base for debug info, don't bother tracking changes through | |
2922 | each instruction in the prologue. It just takes up space. */ | |
2923 | note_rtx = gen_rtx_SET ((frame_pointer_needed | |
2924 | ? hard_frame_pointer_rtx | |
2925 | : stack_pointer_rtx), | |
2926 | plus_constant (Pmode, stack_pointer_rtx, | |
2927 | -total_size)); | |
2928 | RTX_FRAME_RELATED_P (insn) = 1; | |
2929 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); | |
2930 | } | |
2931 | } | |
2932 | ||
2933 | void | |
2934 | xtensa_expand_epilogue (void) | |
2935 | { | |
2936 | if (!TARGET_WINDOWED_ABI) | |
2937 | { | |
2938 | int regno; | |
2939 | HOST_WIDE_INT offset; | |
2940 | ||
2941 | if (cfun->machine->current_frame_size > (frame_pointer_needed ? 127 : 1024)) | |
2942 | { | |
2943 | rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); | |
2944 | emit_move_insn (tmp_reg, GEN_INT (cfun->machine->current_frame_size - | |
2945 | cfun->machine->callee_save_size)); | |
2946 | emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_needed ? | |
2947 | hard_frame_pointer_rtx : stack_pointer_rtx, | |
2948 | tmp_reg)); | |
2949 | offset = cfun->machine->callee_save_size - UNITS_PER_WORD; | |
2950 | } | |
2951 | else | |
2952 | { | |
2953 | if (frame_pointer_needed) | |
2954 | emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
2955 | offset = cfun->machine->current_frame_size - UNITS_PER_WORD; | |
2956 | } | |
2957 | ||
2958 | /* Prevent reordering of saved a0 update and loading it back from | |
2959 | the save area. */ | |
2960 | if (crtl->calls_eh_return) | |
2961 | emit_insn (gen_blockage ()); | |
2962 | ||
2963 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) | |
2964 | { | |
2965 | if (xtensa_call_save_reg(regno)) | |
2966 | { | |
2967 | rtx x = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); | |
2968 | ||
2969 | offset -= UNITS_PER_WORD; | |
2970 | emit_move_insn (gen_rtx_REG (SImode, regno), | |
2971 | gen_frame_mem (SImode, x)); | |
2972 | } | |
2973 | } | |
2974 | ||
2975 | if (cfun->machine->current_frame_size > 0) | |
2976 | { | |
2977 | if (frame_pointer_needed || /* always reachable with addi */ | |
2978 | cfun->machine->current_frame_size > 1024 || | |
2979 | cfun->machine->current_frame_size <= 127) | |
2980 | { | |
2981 | if (cfun->machine->current_frame_size <= 127) | |
2982 | offset = cfun->machine->current_frame_size; | |
2983 | else | |
2984 | offset = cfun->machine->callee_save_size; | |
2985 | ||
2986 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
2987 | stack_pointer_rtx, | |
2988 | GEN_INT (offset))); | |
2989 | } | |
2990 | else | |
2991 | { | |
2992 | rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); | |
2993 | emit_move_insn (tmp_reg, | |
2994 | GEN_INT (cfun->machine->current_frame_size)); | |
2995 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
2996 | tmp_reg)); | |
2997 | } | |
2998 | } | |
2999 | ||
3000 | if (crtl->calls_eh_return) | |
3001 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
3002 | stack_pointer_rtx, | |
3003 | EH_RETURN_STACKADJ_RTX)); | |
3004 | } | |
3005 | cfun->machine->epilogue_done = true; | |
3006 | emit_jump_insn (gen_return ()); | |
3007 | } | |
3008 | ||
3009 | bool | |
3010 | xtensa_use_return_instruction_p (void) | |
3011 | { | |
3012 | if (!reload_completed) | |
3013 | return false; | |
3014 | if (TARGET_WINDOWED_ABI) | |
3015 | return true; | |
3016 | if (compute_frame_size (get_frame_size ()) == 0) | |
3017 | return true; | |
3018 | return cfun->machine->epilogue_done; | |
3019 | } | |
3020 | ||
3021 | void | |
3022 | xtensa_set_return_address (rtx address, rtx scratch) | |
3023 | { | |
3024 | HOST_WIDE_INT total_size = compute_frame_size (get_frame_size ()); | |
3025 | rtx frame = frame_pointer_needed ? | |
3026 | hard_frame_pointer_rtx : stack_pointer_rtx; | |
3027 | rtx a0_addr = plus_constant (Pmode, frame, | |
3028 | total_size - UNITS_PER_WORD); | |
3029 | rtx note = gen_rtx_SET (gen_frame_mem (SImode, a0_addr), | |
3030 | gen_rtx_REG (SImode, A0_REG)); | |
3031 | rtx insn; | |
3032 | ||
3033 | if (total_size > 1024) { | |
3034 | emit_move_insn (scratch, GEN_INT (total_size - UNITS_PER_WORD)); | |
3035 | emit_insn (gen_addsi3 (scratch, frame, scratch)); | |
3036 | a0_addr = scratch; | |
3037 | } | |
3038 | ||
3039 | insn = emit_move_insn (gen_frame_mem (SImode, a0_addr), address); | |
3040 | RTX_FRAME_RELATED_P (insn) = 1; | |
3041 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); | |
3042 | } | |
3043 | ||
3044 | rtx | |
3045 | xtensa_return_addr (int count, rtx frame) | |
3046 | { | |
3047 | rtx result, retaddr, curaddr, label; | |
3048 | ||
3049 | if (!TARGET_WINDOWED_ABI) | |
3050 | { | |
3051 | if (count != 0) | |
3052 | return const0_rtx; | |
3053 | ||
3054 | return get_hard_reg_initial_val (Pmode, A0_REG); | |
3055 | } | |
3056 | ||
3057 | if (count == -1) | |
3058 | retaddr = gen_rtx_REG (Pmode, A0_REG); | |
3059 | else | |
3060 | { | |
3061 | rtx addr = plus_constant (Pmode, frame, -4 * UNITS_PER_WORD); | |
3062 | addr = memory_address (Pmode, addr); | |
3063 | retaddr = gen_reg_rtx (Pmode); | |
3064 | emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr)); | |
3065 | } | |
3066 | ||
3067 | /* The 2 most-significant bits of the return address on Xtensa hold | |
3068 | the register window size. To get the real return address, these | |
3069 | bits must be replaced with the high bits from some address in the | |
3070 | code. */ | |
3071 | ||
3072 | /* Get the 2 high bits of a local label in the code. */ | |
3073 | curaddr = gen_reg_rtx (Pmode); | |
3074 | label = gen_label_rtx (); | |
3075 | emit_label (label); | |
3076 | LABEL_PRESERVE_P (label) = 1; | |
3077 | emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label)); | |
3078 | emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30))); | |
3079 | emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30))); | |
3080 | ||
3081 | /* Clear the 2 high bits of the return address. */ | |
3082 | result = gen_reg_rtx (Pmode); | |
3083 | emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2))); | |
3084 | emit_insn (gen_lshrsi3 (result, result, GEN_INT (2))); | |
3085 | ||
3086 | /* Combine them to get the result. */ | |
3087 | emit_insn (gen_iorsi3 (result, result, curaddr)); | |
3088 | return result; | |
3089 | } | |
3090 | ||
3091 | /* Disable the use of word-sized or smaller complex modes for structures, | |
3092 | and for function arguments in particular, where they cause problems with | |
3093 | register a7. The xtensa_copy_incoming_a7 function assumes that there is | |
3094 | a single reference to an argument in a7, but with small complex modes the | |
3095 | real and imaginary components may be extracted separately, leading to two | |
3096 | uses of the register, only one of which would be replaced. */ | |
3097 | ||
3098 | static bool | |
3099 | xtensa_member_type_forces_blk (const_tree, machine_mode mode) | |
3100 | { | |
3101 | return mode == CQImode || mode == CHImode; | |
3102 | } | |
3103 | ||
3104 | /* Create the va_list data type. | |
3105 | ||
3106 | This structure is set up by __builtin_saveregs. The __va_reg field | |
3107 | points to a stack-allocated region holding the contents of the | |
3108 | incoming argument registers. The __va_ndx field is an index | |
3109 | initialized to the position of the first unnamed (variable) | |
3110 | argument. This same index is also used to address the arguments | |
3111 | passed in memory. Thus, the __va_stk field is initialized to point | |
3112 | to the position of the first argument in memory offset to account | |
3113 | for the arguments passed in registers and to account for the size | |
3114 | of the argument registers not being 16-byte aligned. E.G., there | |
3115 | are 6 argument registers of 4 bytes each, but we want the __va_ndx | |
3116 | for the first stack argument to have the maximal alignment of 16 | |
3117 | bytes, so we offset the __va_stk address by 32 bytes so that | |
3118 | __va_stk[32] references the first argument on the stack. */ | |
3119 | ||
3120 | static tree | |
3121 | xtensa_build_builtin_va_list (void) | |
3122 | { | |
3123 | tree f_stk, f_reg, f_ndx, record, type_decl; | |
3124 | ||
3125 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); | |
3126 | type_decl = build_decl (BUILTINS_LOCATION, | |
3127 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
3128 | ||
3129 | f_stk = build_decl (BUILTINS_LOCATION, | |
3130 | FIELD_DECL, get_identifier ("__va_stk"), | |
3131 | ptr_type_node); | |
3132 | f_reg = build_decl (BUILTINS_LOCATION, | |
3133 | FIELD_DECL, get_identifier ("__va_reg"), | |
3134 | ptr_type_node); | |
3135 | f_ndx = build_decl (BUILTINS_LOCATION, | |
3136 | FIELD_DECL, get_identifier ("__va_ndx"), | |
3137 | integer_type_node); | |
3138 | ||
3139 | DECL_FIELD_CONTEXT (f_stk) = record; | |
3140 | DECL_FIELD_CONTEXT (f_reg) = record; | |
3141 | DECL_FIELD_CONTEXT (f_ndx) = record; | |
3142 | ||
3143 | TYPE_STUB_DECL (record) = type_decl; | |
3144 | TYPE_NAME (record) = type_decl; | |
3145 | TYPE_FIELDS (record) = f_stk; | |
3146 | DECL_CHAIN (f_stk) = f_reg; | |
3147 | DECL_CHAIN (f_reg) = f_ndx; | |
3148 | ||
3149 | layout_type (record); | |
3150 | return record; | |
3151 | } | |
3152 | ||
3153 | ||
3154 | /* Save the incoming argument registers on the stack. Returns the | |
3155 | address of the saved registers. */ | |
3156 | ||
3157 | static rtx | |
3158 | xtensa_builtin_saveregs (void) | |
3159 | { | |
3160 | rtx gp_regs; | |
3161 | int arg_words = crtl->args.info.arg_words; | |
3162 | int gp_left = MAX_ARGS_IN_REGISTERS - arg_words; | |
3163 | ||
3164 | if (gp_left <= 0) | |
3165 | return const0_rtx; | |
3166 | ||
3167 | /* Allocate the general-purpose register space. */ | |
3168 | gp_regs = assign_stack_local | |
3169 | (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1); | |
3170 | set_mem_alias_set (gp_regs, get_varargs_alias_set ()); | |
3171 | ||
3172 | /* Now store the incoming registers. */ | |
3173 | cfun->machine->need_a7_copy = TARGET_WINDOWED_ABI; | |
3174 | cfun->machine->vararg_a7 = true; | |
3175 | move_block_from_reg (GP_ARG_FIRST + arg_words, | |
3176 | adjust_address (gp_regs, BLKmode, | |
3177 | arg_words * UNITS_PER_WORD), | |
3178 | gp_left); | |
3179 | if (cfun->machine->vararg_a7_copy != 0) | |
3180 | emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ()); | |
3181 | ||
3182 | return XEXP (gp_regs, 0); | |
3183 | } | |
3184 | ||
3185 | ||
3186 | /* Implement `va_start' for varargs and stdarg. We look at the | |
3187 | current function to fill in an initial va_list. */ | |
3188 | ||
3189 | static void | |
3190 | xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) | |
3191 | { | |
3192 | tree f_stk, stk; | |
3193 | tree f_reg, reg; | |
3194 | tree f_ndx, ndx; | |
3195 | tree t, u; | |
3196 | int arg_words; | |
3197 | ||
3198 | arg_words = crtl->args.info.arg_words; | |
3199 | ||
3200 | f_stk = TYPE_FIELDS (va_list_type_node); | |
3201 | f_reg = DECL_CHAIN (f_stk); | |
3202 | f_ndx = DECL_CHAIN (f_reg); | |
3203 | ||
3204 | stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE); | |
3205 | reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), | |
3206 | f_reg, NULL_TREE); | |
3207 | ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
3208 | f_ndx, NULL_TREE); | |
3209 | ||
3210 | /* Call __builtin_saveregs; save the result in __va_reg */ | |
3211 | u = make_tree (sizetype, expand_builtin_saveregs ()); | |
3212 | u = fold_convert (ptr_type_node, u); | |
3213 | t = build2 (MODIFY_EXPR, ptr_type_node, reg, u); | |
3214 | TREE_SIDE_EFFECTS (t) = 1; | |
3215 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3216 | ||
3217 | /* Set the __va_stk member to ($arg_ptr - 32). */ | |
3218 | u = make_tree (ptr_type_node, virtual_incoming_args_rtx); | |
3219 | u = fold_build_pointer_plus_hwi (u, -32); | |
3220 | t = build2 (MODIFY_EXPR, ptr_type_node, stk, u); | |
3221 | TREE_SIDE_EFFECTS (t) = 1; | |
3222 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3223 | ||
3224 | /* Set the __va_ndx member. If the first variable argument is on | |
3225 | the stack, adjust __va_ndx by 2 words to account for the extra | |
3226 | alignment offset for __va_stk. */ | |
3227 | if (arg_words >= MAX_ARGS_IN_REGISTERS) | |
3228 | arg_words += 2; | |
3229 | t = build2 (MODIFY_EXPR, integer_type_node, ndx, | |
3230 | build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD)); | |
3231 | TREE_SIDE_EFFECTS (t) = 1; | |
3232 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
3233 | } | |
3234 | ||
3235 | ||
3236 | /* Implement `va_arg'. */ | |
3237 | ||
3238 | static tree | |
3239 | xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, | |
3240 | gimple_seq *post_p ATTRIBUTE_UNUSED) | |
3241 | { | |
3242 | tree f_stk, stk; | |
3243 | tree f_reg, reg; | |
3244 | tree f_ndx, ndx; | |
3245 | tree type_size, array, orig_ndx, addr, size, va_size, t; | |
3246 | tree lab_false, lab_over, lab_false2; | |
3247 | bool indirect; | |
3248 | ||
3249 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); | |
3250 | if (indirect) | |
3251 | type = build_pointer_type (type); | |
3252 | ||
3253 | /* Handle complex values as separate real and imaginary parts. */ | |
3254 | if (TREE_CODE (type) == COMPLEX_TYPE) | |
3255 | { | |
3256 | tree real_part, imag_part; | |
3257 | ||
3258 | real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type), | |
3259 | pre_p, NULL); | |
3260 | real_part = get_initialized_tmp_var (real_part, pre_p, NULL); | |
3261 | ||
3262 | imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist), | |
3263 | TREE_TYPE (type), | |
3264 | pre_p, NULL); | |
3265 | imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL); | |
3266 | ||
3267 | return build2 (COMPLEX_EXPR, type, real_part, imag_part); | |
3268 | } | |
3269 | ||
3270 | f_stk = TYPE_FIELDS (va_list_type_node); | |
3271 | f_reg = DECL_CHAIN (f_stk); | |
3272 | f_ndx = DECL_CHAIN (f_reg); | |
3273 | ||
3274 | stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, | |
3275 | f_stk, NULL_TREE); | |
3276 | reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), | |
3277 | f_reg, NULL_TREE); | |
3278 | ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), | |
3279 | f_ndx, NULL_TREE); | |
3280 | ||
3281 | type_size = size_in_bytes (type); | |
3282 | va_size = round_up (type_size, UNITS_PER_WORD); | |
3283 | gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue); | |
3284 | ||
3285 | ||
3286 | /* First align __va_ndx if necessary for this arg: | |
3287 | ||
3288 | orig_ndx = (AP).__va_ndx; | |
3289 | if (__alignof__ (TYPE) > 4 ) | |
3290 | orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1) | |
3291 | & -__alignof__ (TYPE)); */ | |
3292 | ||
3293 | orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL); | |
3294 | ||
3295 | if (TYPE_ALIGN (type) > BITS_PER_WORD) | |
3296 | { | |
3297 | int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT; | |
3298 | ||
3299 | t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx), | |
3300 | build_int_cst (integer_type_node, align - 1)); | |
3301 | t = build2 (BIT_AND_EXPR, integer_type_node, t, | |
3302 | build_int_cst (integer_type_node, -align)); | |
3303 | gimplify_assign (unshare_expr (orig_ndx), t, pre_p); | |
3304 | } | |
3305 | ||
3306 | ||
3307 | /* Increment __va_ndx to point past the argument: | |
3308 | ||
3309 | (AP).__va_ndx = orig_ndx + __va_size (TYPE); */ | |
3310 | ||
3311 | t = fold_convert (integer_type_node, va_size); | |
3312 | t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t); | |
3313 | gimplify_assign (unshare_expr (ndx), t, pre_p); | |
3314 | ||
3315 | ||
3316 | /* Check if the argument is in registers: | |
3317 | ||
3318 | if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4 | |
3319 | && !must_pass_in_stack (type)) | |
3320 | __array = (AP).__va_reg; */ | |
3321 | ||
3322 | array = create_tmp_var (ptr_type_node); | |
3323 | ||
3324 | lab_over = NULL; | |
3325 | if (!targetm.calls.must_pass_in_stack (TYPE_MODE (type), type)) | |
3326 | { | |
3327 | lab_false = create_artificial_label (UNKNOWN_LOCATION); | |
3328 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
3329 | ||
3330 | t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx), | |
3331 | build_int_cst (integer_type_node, | |
3332 | MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
3333 | t = build3 (COND_EXPR, void_type_node, t, | |
3334 | build1 (GOTO_EXPR, void_type_node, lab_false), | |
3335 | NULL_TREE); | |
3336 | gimplify_and_add (t, pre_p); | |
3337 | ||
3338 | gimplify_assign (unshare_expr (array), reg, pre_p); | |
3339 | ||
3340 | t = build1 (GOTO_EXPR, void_type_node, lab_over); | |
3341 | gimplify_and_add (t, pre_p); | |
3342 | ||
3343 | t = build1 (LABEL_EXPR, void_type_node, lab_false); | |
3344 | gimplify_and_add (t, pre_p); | |
3345 | } | |
3346 | ||
3347 | ||
3348 | /* ...otherwise, the argument is on the stack (never split between | |
3349 | registers and the stack -- change __va_ndx if necessary): | |
3350 | ||
3351 | else | |
3352 | { | |
3353 | if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4) | |
3354 | (AP).__va_ndx = 32 + __va_size (TYPE); | |
3355 | __array = (AP).__va_stk; | |
3356 | } */ | |
3357 | ||
3358 | lab_false2 = create_artificial_label (UNKNOWN_LOCATION); | |
3359 | ||
3360 | t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx), | |
3361 | build_int_cst (integer_type_node, | |
3362 | MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); | |
3363 | t = build3 (COND_EXPR, void_type_node, t, | |
3364 | build1 (GOTO_EXPR, void_type_node, lab_false2), | |
3365 | NULL_TREE); | |
3366 | gimplify_and_add (t, pre_p); | |
3367 | ||
3368 | t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32)); | |
3369 | t = fold_convert (integer_type_node, t); | |
3370 | gimplify_assign (unshare_expr (ndx), t, pre_p); | |
3371 | ||
3372 | t = build1 (LABEL_EXPR, void_type_node, lab_false2); | |
3373 | gimplify_and_add (t, pre_p); | |
3374 | ||
3375 | gimplify_assign (array, stk, pre_p); | |
3376 | ||
3377 | if (lab_over) | |
3378 | { | |
3379 | t = build1 (LABEL_EXPR, void_type_node, lab_over); | |
3380 | gimplify_and_add (t, pre_p); | |
3381 | } | |
3382 | ||
3383 | ||
3384 | /* Given the base array pointer (__array) and index to the subsequent | |
3385 | argument (__va_ndx), find the address: | |
3386 | ||
3387 | __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4 | |
3388 | ? sizeof (TYPE) | |
3389 | : __va_size (TYPE)) | |
3390 | ||
3391 | The results are endian-dependent because values smaller than one word | |
3392 | are aligned differently. */ | |
3393 | ||
3394 | ||
3395 | if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST) | |
3396 | { | |
3397 | t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size), | |
3398 | size_int (PARM_BOUNDARY / BITS_PER_UNIT)); | |
3399 | t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size), | |
3400 | unshare_expr (type_size)); | |
3401 | size = t; | |
3402 | } | |
3403 | else | |
3404 | size = unshare_expr (va_size); | |
3405 | ||
3406 | t = fold_convert (sizetype, unshare_expr (ndx)); | |
3407 | t = build2 (MINUS_EXPR, sizetype, t, size); | |
3408 | addr = fold_build_pointer_plus (unshare_expr (array), t); | |
3409 | ||
3410 | addr = fold_convert (build_pointer_type (type), addr); | |
3411 | if (indirect) | |
3412 | addr = build_va_arg_indirect_ref (addr); | |
3413 | return build_va_arg_indirect_ref (addr); | |
3414 | } | |
3415 | ||
3416 | ||
3417 | /* Builtins. */ | |
3418 | ||
3419 | enum xtensa_builtin | |
3420 | { | |
3421 | XTENSA_BUILTIN_UMULSIDI3, | |
3422 | XTENSA_BUILTIN_max | |
3423 | }; | |
3424 | ||
3425 | ||
3426 | static void | |
3427 | xtensa_init_builtins (void) | |
3428 | { | |
3429 | tree ftype, decl; | |
3430 | ||
3431 | ftype = build_function_type_list (unsigned_intDI_type_node, | |
3432 | unsigned_intSI_type_node, | |
3433 | unsigned_intSI_type_node, NULL_TREE); | |
3434 | ||
3435 | decl = add_builtin_function ("__builtin_umulsidi3", ftype, | |
3436 | XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD, | |
3437 | "__umulsidi3", NULL_TREE); | |
3438 | TREE_NOTHROW (decl) = 1; | |
3439 | TREE_READONLY (decl) = 1; | |
3440 | } | |
3441 | ||
3442 | ||
3443 | static tree | |
3444 | xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, | |
3445 | bool ignore ATTRIBUTE_UNUSED) | |
3446 | { | |
3447 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
3448 | tree arg0, arg1; | |
3449 | ||
3450 | switch (fcode) | |
3451 | { | |
3452 | case XTENSA_BUILTIN_UMULSIDI3: | |
3453 | arg0 = args[0]; | |
3454 | arg1 = args[1]; | |
3455 | if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) | |
3456 | || TARGET_MUL32_HIGH) | |
3457 | return fold_build2 (MULT_EXPR, unsigned_intDI_type_node, | |
3458 | fold_convert (unsigned_intDI_type_node, arg0), | |
3459 | fold_convert (unsigned_intDI_type_node, arg1)); | |
3460 | break; | |
3461 | ||
3462 | default: | |
3463 | internal_error ("bad builtin code"); | |
3464 | break; | |
3465 | } | |
3466 | ||
3467 | return NULL; | |
3468 | } | |
3469 | ||
3470 | ||
3471 | static rtx | |
3472 | xtensa_expand_builtin (tree exp, rtx target, | |
3473 | rtx subtarget ATTRIBUTE_UNUSED, | |
3474 | machine_mode mode ATTRIBUTE_UNUSED, | |
3475 | int ignore) | |
3476 | { | |
3477 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
3478 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
3479 | ||
3480 | switch (fcode) | |
3481 | { | |
3482 | case XTENSA_BUILTIN_UMULSIDI3: | |
3483 | /* The umulsidi3 builtin is just a mechanism to avoid calling the real | |
3484 | __umulsidi3 function when the Xtensa configuration can directly | |
3485 | implement it. If not, just call the function. */ | |
3486 | return expand_call (exp, target, ignore); | |
3487 | ||
3488 | default: | |
3489 | internal_error ("bad builtin code"); | |
3490 | } | |
3491 | return NULL_RTX; | |
3492 | } | |
3493 | ||
3494 | /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */ | |
3495 | ||
3496 | static reg_class_t | |
3497 | xtensa_preferred_reload_class (rtx x, reg_class_t rclass) | |
3498 | { | |
3499 | if (CONSTANT_P (x) && CONST_DOUBLE_P (x)) | |
3500 | return NO_REGS; | |
3501 | ||
3502 | /* Don't use the stack pointer or hard frame pointer for reloads! | |
3503 | The hard frame pointer would normally be OK except that it may | |
3504 | briefly hold an incoming argument in the prologue, and reload | |
3505 | won't know that it is live because the hard frame pointer is | |
3506 | treated specially. */ | |
3507 | ||
3508 | if (rclass == AR_REGS || rclass == GR_REGS) | |
3509 | return RL_REGS; | |
3510 | ||
3511 | return rclass; | |
3512 | } | |
3513 | ||
3514 | /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
3515 | ||
3516 | static reg_class_t | |
3517 | xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED, | |
3518 | reg_class_t rclass) | |
3519 | { | |
3520 | /* Don't use the stack pointer or hard frame pointer for reloads! | |
3521 | The hard frame pointer would normally be OK except that it may | |
3522 | briefly hold an incoming argument in the prologue, and reload | |
3523 | won't know that it is live because the hard frame pointer is | |
3524 | treated specially. */ | |
3525 | ||
3526 | if (rclass == AR_REGS || rclass == GR_REGS) | |
3527 | return RL_REGS; | |
3528 | ||
3529 | return rclass; | |
3530 | } | |
3531 | ||
3532 | /* Worker function for TARGET_SECONDARY_RELOAD. */ | |
3533 | ||
3534 | static reg_class_t | |
3535 | xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass, | |
3536 | machine_mode mode, secondary_reload_info *sri) | |
3537 | { | |
3538 | int regno; | |
3539 | ||
3540 | if (in_p && constantpool_mem_p (x)) | |
3541 | { | |
3542 | if (rclass == FP_REGS) | |
3543 | return RL_REGS; | |
3544 | ||
3545 | if (mode == QImode) | |
3546 | sri->icode = CODE_FOR_reloadqi_literal; | |
3547 | else if (mode == HImode) | |
3548 | sri->icode = CODE_FOR_reloadhi_literal; | |
3549 | } | |
3550 | ||
3551 | regno = xt_true_regnum (x); | |
3552 | if (ACC_REG_P (regno)) | |
3553 | return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS); | |
3554 | if (rclass == ACC_REG) | |
3555 | return (GP_REG_P (regno) ? NO_REGS : RL_REGS); | |
3556 | ||
3557 | return NO_REGS; | |
3558 | } | |
3559 | ||
3560 | ||
3561 | void | |
3562 | order_regs_for_local_alloc (void) | |
3563 | { | |
3564 | if (!leaf_function_p ()) | |
3565 | { | |
3566 | static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] = | |
3567 | REG_ALLOC_ORDER; | |
3568 | static const int reg_nonleaf_alloc_order_call0[FIRST_PSEUDO_REGISTER] = | |
3569 | { | |
3570 | 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 12, 13, 14, 15, | |
3571 | 18, | |
3572 | 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, | |
3573 | 0, 1, 16, 17, | |
3574 | 35, | |
3575 | }; | |
3576 | ||
3577 | memcpy (reg_alloc_order, TARGET_WINDOWED_ABI ? | |
3578 | reg_nonleaf_alloc_order : reg_nonleaf_alloc_order_call0, | |
3579 | FIRST_PSEUDO_REGISTER * sizeof (int)); | |
3580 | } | |
3581 | else | |
3582 | { | |
3583 | int i, num_arg_regs; | |
3584 | int nxt = 0; | |
3585 | ||
3586 | /* Use the AR registers in increasing order (skipping a0 and a1) | |
3587 | but save the incoming argument registers for a last resort. */ | |
3588 | num_arg_regs = crtl->args.info.arg_words; | |
3589 | if (num_arg_regs > MAX_ARGS_IN_REGISTERS) | |
3590 | num_arg_regs = MAX_ARGS_IN_REGISTERS; | |
3591 | for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++) | |
3592 | reg_alloc_order[nxt++] = i + num_arg_regs; | |
3593 | for (i = 0; i < num_arg_regs; i++) | |
3594 | reg_alloc_order[nxt++] = GP_ARG_FIRST + i; | |
3595 | ||
3596 | /* List the coprocessor registers in order. */ | |
3597 | for (i = 0; i < BR_REG_NUM; i++) | |
3598 | reg_alloc_order[nxt++] = BR_REG_FIRST + i; | |
3599 | ||
3600 | /* List the FP registers in order for now. */ | |
3601 | for (i = 0; i < 16; i++) | |
3602 | reg_alloc_order[nxt++] = FP_REG_FIRST + i; | |
3603 | ||
3604 | /* GCC requires that we list *all* the registers.... */ | |
3605 | reg_alloc_order[nxt++] = 0; /* a0 = return address */ | |
3606 | reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */ | |
3607 | reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */ | |
3608 | reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */ | |
3609 | ||
3610 | reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */ | |
3611 | } | |
3612 | } | |
3613 | ||
3614 | ||
3615 | /* Some Xtensa targets support multiple bss sections. If the section | |
3616 | name ends with ".bss", add SECTION_BSS to the flags. */ | |
3617 | ||
3618 | static unsigned int | |
3619 | xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc) | |
3620 | { | |
3621 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
3622 | const char *suffix; | |
3623 | ||
3624 | suffix = strrchr (name, '.'); | |
3625 | if (suffix && strcmp (suffix, ".bss") == 0) | |
3626 | { | |
3627 | if (!decl || (TREE_CODE (decl) == VAR_DECL | |
3628 | && DECL_INITIAL (decl) == NULL_TREE)) | |
3629 | flags |= SECTION_BSS; /* @nobits */ | |
3630 | else | |
3631 | warning (0, "only uninitialized variables can be placed in a " | |
3632 | ".bss section"); | |
3633 | } | |
3634 | ||
3635 | return flags; | |
3636 | } | |
3637 | ||
3638 | ||
3639 | /* The literal pool stays with the function. */ | |
3640 | ||
3641 | static section * | |
3642 | xtensa_select_rtx_section (machine_mode mode ATTRIBUTE_UNUSED, | |
3643 | rtx x ATTRIBUTE_UNUSED, | |
3644 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
3645 | { | |
3646 | return function_section (current_function_decl); | |
3647 | } | |
3648 | ||
3649 | /* Worker function for TARGET_REGISTER_MOVE_COST. */ | |
3650 | ||
3651 | static int | |
3652 | xtensa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, | |
3653 | reg_class_t from, reg_class_t to) | |
3654 | { | |
3655 | if (from == to && from != BR_REGS && to != BR_REGS) | |
3656 | return 2; | |
3657 | else if (reg_class_subset_p (from, AR_REGS) | |
3658 | && reg_class_subset_p (to, AR_REGS)) | |
3659 | return 2; | |
3660 | else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG) | |
3661 | return 3; | |
3662 | else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS)) | |
3663 | return 3; | |
3664 | else | |
3665 | return 10; | |
3666 | } | |
3667 | ||
3668 | /* Worker function for TARGET_MEMORY_MOVE_COST. */ | |
3669 | ||
3670 | static int | |
3671 | xtensa_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, | |
3672 | reg_class_t rclass ATTRIBUTE_UNUSED, | |
3673 | bool in ATTRIBUTE_UNUSED) | |
3674 | { | |
3675 | return 4; | |
3676 | } | |
3677 | ||
3678 | /* Compute a (partial) cost for rtx X. Return true if the complete | |
3679 | cost has been computed, and false if subexpressions should be | |
3680 | scanned. In either case, *TOTAL contains the cost result. */ | |
3681 | ||
3682 | static bool | |
3683 | xtensa_rtx_costs (rtx x, machine_mode mode, int outer_code, | |
3684 | int opno ATTRIBUTE_UNUSED, | |
3685 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3686 | { | |
3687 | int code = GET_CODE (x); | |
3688 | ||
3689 | switch (code) | |
3690 | { | |
3691 | case CONST_INT: | |
3692 | switch (outer_code) | |
3693 | { | |
3694 | case SET: | |
3695 | if (xtensa_simm12b (INTVAL (x))) | |
3696 | { | |
3697 | *total = 4; | |
3698 | return true; | |
3699 | } | |
3700 | break; | |
3701 | case PLUS: | |
3702 | if (xtensa_simm8 (INTVAL (x)) | |
3703 | || xtensa_simm8x256 (INTVAL (x))) | |
3704 | { | |
3705 | *total = 0; | |
3706 | return true; | |
3707 | } | |
3708 | break; | |
3709 | case AND: | |
3710 | if (xtensa_mask_immediate (INTVAL (x))) | |
3711 | { | |
3712 | *total = 0; | |
3713 | return true; | |
3714 | } | |
3715 | break; | |
3716 | case COMPARE: | |
3717 | if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x))) | |
3718 | { | |
3719 | *total = 0; | |
3720 | return true; | |
3721 | } | |
3722 | break; | |
3723 | case ASHIFT: | |
3724 | case ASHIFTRT: | |
3725 | case LSHIFTRT: | |
3726 | case ROTATE: | |
3727 | case ROTATERT: | |
3728 | /* No way to tell if X is the 2nd operand so be conservative. */ | |
3729 | default: break; | |
3730 | } | |
3731 | if (xtensa_simm12b (INTVAL (x))) | |
3732 | *total = 5; | |
3733 | else if (TARGET_CONST16) | |
3734 | *total = COSTS_N_INSNS (2); | |
3735 | else | |
3736 | *total = 6; | |
3737 | return true; | |
3738 | ||
3739 | case CONST: | |
3740 | case LABEL_REF: | |
3741 | case SYMBOL_REF: | |
3742 | if (TARGET_CONST16) | |
3743 | *total = COSTS_N_INSNS (2); | |
3744 | else | |
3745 | *total = 5; | |
3746 | return true; | |
3747 | ||
3748 | case CONST_DOUBLE: | |
3749 | if (TARGET_CONST16) | |
3750 | *total = COSTS_N_INSNS (4); | |
3751 | else | |
3752 | *total = 7; | |
3753 | return true; | |
3754 | ||
3755 | case MEM: | |
3756 | { | |
3757 | int num_words = | |
3758 | (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ? 2 : 1; | |
3759 | ||
3760 | if (memory_address_p (mode, XEXP ((x), 0))) | |
3761 | *total = COSTS_N_INSNS (num_words); | |
3762 | else | |
3763 | *total = COSTS_N_INSNS (2*num_words); | |
3764 | return true; | |
3765 | } | |
3766 | ||
3767 | case FFS: | |
3768 | case CTZ: | |
3769 | *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50); | |
3770 | return true; | |
3771 | ||
3772 | case CLZ: | |
3773 | *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50); | |
3774 | return true; | |
3775 | ||
3776 | case NOT: | |
3777 | *total = COSTS_N_INSNS (mode == DImode ? 3 : 2); | |
3778 | return true; | |
3779 | ||
3780 | case AND: | |
3781 | case IOR: | |
3782 | case XOR: | |
3783 | if (mode == DImode) | |
3784 | *total = COSTS_N_INSNS (2); | |
3785 | else | |
3786 | *total = COSTS_N_INSNS (1); | |
3787 | return true; | |
3788 | ||
3789 | case ASHIFT: | |
3790 | case ASHIFTRT: | |
3791 | case LSHIFTRT: | |
3792 | if (mode == DImode) | |
3793 | *total = COSTS_N_INSNS (50); | |
3794 | else | |
3795 | *total = COSTS_N_INSNS (1); | |
3796 | return true; | |
3797 | ||
3798 | case ABS: | |
3799 | { | |
3800 | if (mode == SFmode) | |
3801 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
3802 | else if (mode == DFmode) | |
3803 | *total = COSTS_N_INSNS (50); | |
3804 | else | |
3805 | *total = COSTS_N_INSNS (4); | |
3806 | return true; | |
3807 | } | |
3808 | ||
3809 | case PLUS: | |
3810 | case MINUS: | |
3811 | { | |
3812 | if (mode == SFmode) | |
3813 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); | |
3814 | else if (mode == DFmode || mode == DImode) | |
3815 | *total = COSTS_N_INSNS (50); | |
3816 | else | |
3817 | *total = COSTS_N_INSNS (1); | |
3818 | return true; | |
3819 | } | |
3820 | ||
3821 | case NEG: | |
3822 | *total = COSTS_N_INSNS (mode == DImode ? 4 : 2); | |
3823 | return true; | |
3824 | ||
3825 | case MULT: | |
3826 | { | |
3827 | if (mode == SFmode) | |
3828 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); | |
3829 | else if (mode == DFmode) | |
3830 | *total = COSTS_N_INSNS (50); | |
3831 | else if (mode == DImode) | |
3832 | *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50); | |
3833 | else if (TARGET_MUL32) | |
3834 | *total = COSTS_N_INSNS (4); | |
3835 | else if (TARGET_MAC16) | |
3836 | *total = COSTS_N_INSNS (16); | |
3837 | else if (TARGET_MUL16) | |
3838 | *total = COSTS_N_INSNS (12); | |
3839 | else | |
3840 | *total = COSTS_N_INSNS (50); | |
3841 | return true; | |
3842 | } | |
3843 | ||
3844 | case DIV: | |
3845 | case MOD: | |
3846 | { | |
3847 | if (mode == SFmode) | |
3848 | { | |
3849 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); | |
3850 | return true; | |
3851 | } | |
3852 | else if (mode == DFmode) | |
3853 | { | |
3854 | *total = COSTS_N_INSNS (50); | |
3855 | return true; | |
3856 | } | |
3857 | } | |
3858 | /* Fall through. */ | |
3859 | ||
3860 | case UDIV: | |
3861 | case UMOD: | |
3862 | { | |
3863 | if (mode == DImode) | |
3864 | *total = COSTS_N_INSNS (50); | |
3865 | else if (TARGET_DIV32) | |
3866 | *total = COSTS_N_INSNS (32); | |
3867 | else | |
3868 | *total = COSTS_N_INSNS (50); | |
3869 | return true; | |
3870 | } | |
3871 | ||
3872 | case SQRT: | |
3873 | if (mode == SFmode) | |
3874 | *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); | |
3875 | else | |
3876 | *total = COSTS_N_INSNS (50); | |
3877 | return true; | |
3878 | ||
3879 | case SMIN: | |
3880 | case UMIN: | |
3881 | case SMAX: | |
3882 | case UMAX: | |
3883 | *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); | |
3884 | return true; | |
3885 | ||
3886 | case SIGN_EXTRACT: | |
3887 | case SIGN_EXTEND: | |
3888 | *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); | |
3889 | return true; | |
3890 | ||
3891 | case ZERO_EXTRACT: | |
3892 | case ZERO_EXTEND: | |
3893 | *total = COSTS_N_INSNS (1); | |
3894 | return true; | |
3895 | ||
3896 | default: | |
3897 | return false; | |
3898 | } | |
3899 | } | |
3900 | ||
3901 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
3902 | ||
3903 | static bool | |
3904 | xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) | |
3905 | { | |
3906 | return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) | |
3907 | > 4 * UNITS_PER_WORD); | |
3908 | } | |
3909 | ||
3910 | /* Worker function for TARGET_FUNCTION_VALUE. */ | |
3911 | ||
3912 | rtx | |
3913 | xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED, | |
3914 | bool outgoing) | |
3915 | { | |
3916 | return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype) | |
3917 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
3918 | ? SImode : TYPE_MODE (valtype), | |
3919 | outgoing ? GP_OUTGOING_RETURN : GP_RETURN); | |
3920 | } | |
3921 | ||
3922 | /* Worker function for TARGET_LIBCALL_VALUE. */ | |
3923 | ||
3924 | static rtx | |
3925 | xtensa_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) | |
3926 | { | |
3927 | return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT | |
3928 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
3929 | ? SImode : mode, GP_RETURN); | |
3930 | } | |
3931 | ||
3932 | /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */ | |
3933 | ||
3934 | static bool | |
3935 | xtensa_function_value_regno_p (const unsigned int regno) | |
3936 | { | |
3937 | return (regno == GP_RETURN); | |
3938 | } | |
3939 | ||
3940 | /* The static chain is passed in memory. Provide rtx giving 'mem' | |
3941 | expressions that denote where they are stored. */ | |
3942 | ||
3943 | static rtx | |
3944 | xtensa_static_chain (const_tree ARG_UNUSED (fndecl_or_type), bool incoming_p) | |
3945 | { | |
3946 | if (TARGET_WINDOWED_ABI) | |
3947 | { | |
3948 | rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx; | |
3949 | return gen_frame_mem (Pmode, plus_constant (Pmode, base, | |
3950 | -5 * UNITS_PER_WORD)); | |
3951 | } | |
3952 | else | |
3953 | return gen_rtx_REG (Pmode, A8_REG); | |
3954 | } | |
3955 | ||
3956 | ||
3957 | /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY | |
3958 | instruction with a minimal stack frame in order to get some free | |
3959 | registers. Once the actual call target is known, the proper stack frame | |
3960 | size is extracted from the ENTRY instruction at the target and the | |
3961 | current frame is adjusted to match. The trampoline then transfers | |
3962 | control to the instruction following the ENTRY at the target. Note: | |
3963 | this assumes that the target begins with an ENTRY instruction. */ | |
3964 | ||
3965 | static void | |
3966 | xtensa_asm_trampoline_template (FILE *stream) | |
3967 | { | |
3968 | bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); | |
3969 | ||
3970 | fprintf (stream, "\t.begin no-transform\n"); | |
3971 | ||
3972 | if (TARGET_WINDOWED_ABI) | |
3973 | { | |
3974 | fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); | |
3975 | ||
3976 | if (use_call0) | |
3977 | { | |
3978 | /* Save the return address. */ | |
3979 | fprintf (stream, "\tmov\ta10, a0\n"); | |
3980 | ||
3981 | /* Use a CALL0 instruction to skip past the constants and in the | |
3982 | process get the PC into A0. This allows PC-relative access to | |
3983 | the constants without relying on L32R. */ | |
3984 | fprintf (stream, "\tcall0\t.Lskipconsts\n"); | |
3985 | } | |
3986 | else | |
3987 | fprintf (stream, "\tj\t.Lskipconsts\n"); | |
3988 | ||
3989 | fprintf (stream, "\t.align\t4\n"); | |
3990 | fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); | |
3991 | fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); | |
3992 | fprintf (stream, ".Lskipconsts:\n"); | |
3993 | ||
3994 | /* Load the static chain and function address from the trampoline. */ | |
3995 | if (use_call0) | |
3996 | { | |
3997 | fprintf (stream, "\taddi\ta0, a0, 3\n"); | |
3998 | fprintf (stream, "\tl32i\ta9, a0, 0\n"); | |
3999 | fprintf (stream, "\tl32i\ta8, a0, 4\n"); | |
4000 | } | |
4001 | else | |
4002 | { | |
4003 | fprintf (stream, "\tl32r\ta9, .Lchainval\n"); | |
4004 | fprintf (stream, "\tl32r\ta8, .Lfnaddr\n"); | |
4005 | } | |
4006 | ||
4007 | /* Store the static chain. */ | |
4008 | fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20); | |
4009 | ||
4010 | /* Set the proper stack pointer value. */ | |
4011 | fprintf (stream, "\tl32i\ta9, a8, 0\n"); | |
4012 | fprintf (stream, "\textui\ta9, a9, %d, 12\n", | |
4013 | TARGET_BIG_ENDIAN ? 8 : 12); | |
4014 | fprintf (stream, "\tslli\ta9, a9, 3\n"); | |
4015 | fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); | |
4016 | fprintf (stream, "\tsub\ta9, sp, a9\n"); | |
4017 | fprintf (stream, "\tmovsp\tsp, a9\n"); | |
4018 | ||
4019 | if (use_call0) | |
4020 | /* Restore the return address. */ | |
4021 | fprintf (stream, "\tmov\ta0, a10\n"); | |
4022 | ||
4023 | /* Jump to the instruction following the ENTRY. */ | |
4024 | fprintf (stream, "\taddi\ta8, a8, 3\n"); | |
4025 | fprintf (stream, "\tjx\ta8\n"); | |
4026 | ||
4027 | /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ | |
4028 | if (use_call0) | |
4029 | fprintf (stream, "\t.byte\t0\n"); | |
4030 | else | |
4031 | fprintf (stream, "\tnop\n"); | |
4032 | } | |
4033 | else | |
4034 | { | |
4035 | if (use_call0) | |
4036 | { | |
4037 | /* Save the return address. */ | |
4038 | fprintf (stream, "\tmov\ta10, a0\n"); | |
4039 | ||
4040 | /* Use a CALL0 instruction to skip past the constants and in the | |
4041 | process get the PC into A0. This allows PC-relative access to | |
4042 | the constants without relying on L32R. */ | |
4043 | fprintf (stream, "\tcall0\t.Lskipconsts\n"); | |
4044 | } | |
4045 | else | |
4046 | fprintf (stream, "\tj\t.Lskipconsts\n"); | |
4047 | ||
4048 | fprintf (stream, "\t.align\t4\n"); | |
4049 | fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); | |
4050 | fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); | |
4051 | fprintf (stream, ".Lskipconsts:\n"); | |
4052 | ||
4053 | /* Load the static chain and function address from the trampoline. */ | |
4054 | if (use_call0) | |
4055 | { | |
4056 | fprintf (stream, "\taddi\ta0, a0, 3\n"); | |
4057 | fprintf (stream, "\tl32i\ta8, a0, 0\n"); | |
4058 | fprintf (stream, "\tl32i\ta9, a0, 4\n"); | |
4059 | fprintf (stream, "\tmov\ta0, a10\n"); | |
4060 | } | |
4061 | else | |
4062 | { | |
4063 | fprintf (stream, "\tl32r\ta8, .Lchainval\n"); | |
4064 | fprintf (stream, "\tl32r\ta9, .Lfnaddr\n"); | |
4065 | } | |
4066 | fprintf (stream, "\tjx\ta9\n"); | |
4067 | ||
4068 | /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ | |
4069 | if (use_call0) | |
4070 | fprintf (stream, "\t.byte\t0\n"); | |
4071 | else | |
4072 | fprintf (stream, "\tnop\n"); | |
4073 | } | |
4074 | fprintf (stream, "\t.end no-transform\n"); | |
4075 | } | |
4076 | ||
4077 | static void | |
4078 | xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain) | |
4079 | { | |
4080 | rtx func = XEXP (DECL_RTL (fndecl), 0); | |
4081 | bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); | |
4082 | int chain_off; | |
4083 | int func_off; | |
4084 | ||
4085 | if (TARGET_WINDOWED_ABI) | |
4086 | { | |
4087 | chain_off = use_call0 ? 12 : 8; | |
4088 | func_off = use_call0 ? 16 : 12; | |
4089 | } | |
4090 | else | |
4091 | { | |
4092 | chain_off = use_call0 ? 8 : 4; | |
4093 | func_off = use_call0 ? 12 : 8; | |
4094 | } | |
4095 | ||
4096 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
4097 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
4098 | ||
4099 | emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain); | |
4100 | emit_move_insn (adjust_address (m_tramp, SImode, func_off), func); | |
4101 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), | |
4102 | LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode); | |
4103 | } | |
4104 | ||
4105 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ | |
4106 | ||
4107 | static bool | |
4108 | xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
4109 | { | |
4110 | return !xtensa_tls_referenced_p (x); | |
4111 | } | |
4112 | ||
4113 | /* Implement TARGET_CAN_USE_DOLOOP_P. */ | |
4114 | ||
4115 | static bool | |
4116 | xtensa_can_use_doloop_p (const widest_int &, const widest_int &, | |
4117 | unsigned int loop_depth, bool entered_at_top) | |
4118 | { | |
4119 | /* Considering limitations in the hardware, only use doloop | |
4120 | for innermost loops which must be entered from the top. */ | |
4121 | if (loop_depth > 1 || !entered_at_top) | |
4122 | return false; | |
4123 | ||
4124 | return true; | |
4125 | } | |
4126 | ||
4127 | /* NULL if INSN insn is valid within a low-overhead loop. | |
4128 | Otherwise return why doloop cannot be applied. */ | |
4129 | ||
4130 | static const char * | |
4131 | xtensa_invalid_within_doloop (const rtx_insn *insn) | |
4132 | { | |
4133 | if (CALL_P (insn)) | |
4134 | return "Function call in the loop."; | |
4135 | ||
4136 | if (JUMP_P (insn) && INSN_CODE (insn) == CODE_FOR_return) | |
4137 | return "Return from a call instruction in the loop."; | |
4138 | ||
4139 | return NULL; | |
4140 | } | |
4141 | ||
4142 | /* Optimize LOOP. */ | |
4143 | ||
4144 | static bool | |
4145 | hwloop_optimize (hwloop_info loop) | |
4146 | { | |
4147 | int i; | |
4148 | edge entry_edge; | |
4149 | basic_block entry_bb; | |
4150 | rtx iter_reg; | |
4151 | rtx_insn *insn, *seq, *entry_after; | |
4152 | ||
4153 | if (loop->depth > 1) | |
4154 | { | |
4155 | if (dump_file) | |
4156 | fprintf (dump_file, ";; loop %d is not innermost\n", | |
4157 | loop->loop_no); | |
4158 | return false; | |
4159 | } | |
4160 | ||
4161 | if (!loop->incoming_dest) | |
4162 | { | |
4163 | if (dump_file) | |
4164 | fprintf (dump_file, ";; loop %d has more than one entry\n", | |
4165 | loop->loop_no); | |
4166 | return false; | |
4167 | } | |
4168 | ||
4169 | if (loop->incoming_dest != loop->head) | |
4170 | { | |
4171 | if (dump_file) | |
4172 | fprintf (dump_file, ";; loop %d is not entered from head\n", | |
4173 | loop->loop_no); | |
4174 | return false; | |
4175 | } | |
4176 | ||
4177 | if (loop->has_call || loop->has_asm) | |
4178 | { | |
4179 | if (dump_file) | |
4180 | fprintf (dump_file, ";; loop %d has invalid insn\n", | |
4181 | loop->loop_no); | |
4182 | return false; | |
4183 | } | |
4184 | ||
4185 | /* Scan all the blocks to make sure they don't use iter_reg. */ | |
4186 | if (loop->iter_reg_used || loop->iter_reg_used_outside) | |
4187 | { | |
4188 | if (dump_file) | |
4189 | fprintf (dump_file, ";; loop %d uses iterator\n", | |
4190 | loop->loop_no); | |
4191 | return false; | |
4192 | } | |
4193 | ||
4194 | /* Check if start_label appears before doloop_end. */ | |
4195 | insn = loop->start_label; | |
4196 | while (insn && insn != loop->loop_end) | |
4197 | insn = NEXT_INSN (insn); | |
4198 | ||
4199 | if (!insn) | |
4200 | { | |
4201 | if (dump_file) | |
4202 | fprintf (dump_file, ";; loop %d start_label not before loop_end\n", | |
4203 | loop->loop_no); | |
4204 | return false; | |
4205 | } | |
4206 | ||
4207 | /* Get the loop iteration register. */ | |
4208 | iter_reg = loop->iter_reg; | |
4209 | ||
4210 | gcc_assert (REG_P (iter_reg)); | |
4211 | ||
4212 | entry_edge = NULL; | |
4213 | ||
4214 | FOR_EACH_VEC_SAFE_ELT (loop->incoming, i, entry_edge) | |
4215 | if (entry_edge->flags & EDGE_FALLTHRU) | |
4216 | break; | |
4217 | ||
4218 | if (entry_edge == NULL) | |
4219 | return false; | |
4220 | ||
4221 | /* Place the zero_cost_loop_start instruction before the loop. */ | |
4222 | entry_bb = entry_edge->src; | |
4223 | ||
4224 | start_sequence (); | |
4225 | ||
4226 | insn = emit_insn (gen_zero_cost_loop_start (loop->iter_reg, | |
4227 | loop->start_label, | |
4228 | loop->iter_reg)); | |
4229 | ||
4230 | seq = get_insns (); | |
4231 | ||
4232 | if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1) | |
4233 | { | |
4234 | basic_block new_bb; | |
4235 | edge e; | |
4236 | edge_iterator ei; | |
4237 | ||
4238 | emit_insn_before (seq, BB_HEAD (loop->head)); | |
4239 | seq = emit_label_before (gen_label_rtx (), seq); | |
4240 | new_bb = create_basic_block (seq, insn, entry_bb); | |
4241 | FOR_EACH_EDGE (e, ei, loop->incoming) | |
4242 | { | |
4243 | if (!(e->flags & EDGE_FALLTHRU)) | |
4244 | redirect_edge_and_branch_force (e, new_bb); | |
4245 | else | |
4246 | redirect_edge_succ (e, new_bb); | |
4247 | } | |
4248 | ||
4249 | make_edge (new_bb, loop->head, 0); | |
4250 | } | |
4251 | else | |
4252 | { | |
4253 | entry_after = BB_END (entry_bb); | |
4254 | while (DEBUG_INSN_P (entry_after) | |
4255 | || (NOTE_P (entry_after) | |
4256 | && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK | |
4257 | /* Make sure we don't split a call and its corresponding | |
4258 | CALL_ARG_LOCATION note. */ | |
4259 | && NOTE_KIND (entry_after) != NOTE_INSN_CALL_ARG_LOCATION)) | |
4260 | entry_after = PREV_INSN (entry_after); | |
4261 | ||
4262 | emit_insn_after (seq, entry_after); | |
4263 | } | |
4264 | ||
4265 | end_sequence (); | |
4266 | ||
4267 | return true; | |
4268 | } | |
4269 | ||
4270 | /* A callback for the hw-doloop pass. Called when a loop we have discovered | |
4271 | turns out not to be optimizable; we have to split the loop_end pattern into | |
4272 | a subtract and a test. */ | |
4273 | ||
4274 | static void | |
4275 | hwloop_fail (hwloop_info loop) | |
4276 | { | |
4277 | rtx test; | |
4278 | rtx_insn *insn = loop->loop_end; | |
4279 | ||
4280 | emit_insn_before (gen_addsi3 (loop->iter_reg, | |
4281 | loop->iter_reg, | |
4282 | constm1_rtx), | |
4283 | loop->loop_end); | |
4284 | ||
4285 | test = gen_rtx_NE (VOIDmode, loop->iter_reg, const0_rtx); | |
4286 | insn = emit_jump_insn_before (gen_cbranchsi4 (test, | |
4287 | loop->iter_reg, const0_rtx, | |
4288 | loop->start_label), | |
4289 | loop->loop_end); | |
4290 | ||
4291 | JUMP_LABEL (insn) = loop->start_label; | |
4292 | LABEL_NUSES (loop->start_label)++; | |
4293 | delete_insn (loop->loop_end); | |
4294 | } | |
4295 | ||
4296 | /* A callback for the hw-doloop pass. This function examines INSN; if | |
4297 | it is a doloop_end pattern we recognize, return the reg rtx for the | |
4298 | loop counter. Otherwise, return NULL_RTX. */ | |
4299 | ||
4300 | static rtx | |
4301 | hwloop_pattern_reg (rtx_insn *insn) | |
4302 | { | |
4303 | rtx reg; | |
4304 | ||
4305 | if (!JUMP_P (insn) || recog_memoized (insn) != CODE_FOR_loop_end) | |
4306 | return NULL_RTX; | |
4307 | ||
4308 | reg = SET_DEST (XVECEXP (PATTERN (insn), 0, 1)); | |
4309 | if (!REG_P (reg)) | |
4310 | return NULL_RTX; | |
4311 | ||
4312 | return reg; | |
4313 | } | |
4314 | ||
4315 | ||
4316 | static struct hw_doloop_hooks xtensa_doloop_hooks = | |
4317 | { | |
4318 | hwloop_pattern_reg, | |
4319 | hwloop_optimize, | |
4320 | hwloop_fail | |
4321 | }; | |
4322 | ||
4323 | /* Run from machine_dependent_reorg, this pass looks for doloop_end insns | |
4324 | and tries to rewrite the RTL of these loops so that proper Xtensa | |
4325 | hardware loops are generated. */ | |
4326 | ||
4327 | static void | |
4328 | xtensa_reorg_loops (void) | |
4329 | { | |
4330 | if (TARGET_LOOPS) | |
4331 | reorg_loops (false, &xtensa_doloop_hooks); | |
4332 | } | |
4333 | ||
4334 | /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. */ | |
4335 | ||
4336 | static void | |
4337 | xtensa_reorg (void) | |
4338 | { | |
4339 | /* We are freeing block_for_insn in the toplev to keep compatibility | |
4340 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
4341 | compute_bb_for_insn (); | |
4342 | ||
4343 | df_analyze (); | |
4344 | ||
4345 | /* Doloop optimization. */ | |
4346 | xtensa_reorg_loops (); | |
4347 | } | |
4348 | ||
4349 | /* Update register usage after having seen the compiler flags. */ | |
4350 | ||
4351 | static void | |
4352 | xtensa_conditional_register_usage (void) | |
4353 | { | |
4354 | unsigned i, c_mask; | |
4355 | ||
4356 | c_mask = TARGET_WINDOWED_ABI ? (1 << 1) : (1 << 2); | |
4357 | ||
4358 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
4359 | { | |
4360 | /* Set/reset conditionally defined registers from | |
4361 | CALL_USED_REGISTERS initializer. */ | |
4362 | if (call_used_regs[i] > 1) | |
4363 | call_used_regs[i] = !!(call_used_regs[i] & c_mask); | |
4364 | } | |
4365 | ||
4366 | /* Remove hard FP register from the preferred reload registers set. */ | |
4367 | CLEAR_HARD_REG_BIT (reg_class_contents[(int)RL_REGS], | |
4368 | HARD_FRAME_POINTER_REGNUM); | |
4369 | } | |
4370 | ||
4371 | /* Map hard register number to register class */ | |
4372 | ||
4373 | enum reg_class xtensa_regno_to_class (int regno) | |
4374 | { | |
4375 | static const enum reg_class regno_to_class[FIRST_PSEUDO_REGISTER] = | |
4376 | { | |
4377 | RL_REGS, SP_REG, RL_REGS, RL_REGS, | |
4378 | RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
4379 | RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
4380 | RL_REGS, RL_REGS, RL_REGS, RL_REGS, | |
4381 | AR_REGS, AR_REGS, BR_REGS, | |
4382 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
4383 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
4384 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
4385 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
4386 | ACC_REG, | |
4387 | }; | |
4388 | ||
4389 | if (regno == HARD_FRAME_POINTER_REGNUM) | |
4390 | return GR_REGS; | |
4391 | else | |
4392 | return regno_to_class[regno]; | |
4393 | } | |
4394 | ||
4395 | /* Implement TARGET_CONSTANT_ALIGNMENT. Align string constants and | |
4396 | constructors to at least a word boundary. The typical use of this | |
4397 | macro is to increase alignment for string constants to be word | |
4398 | aligned so that 'strcpy' calls that copy constants can be done | |
4399 | inline. */ | |
4400 | ||
4401 | static HOST_WIDE_INT | |
4402 | xtensa_constant_alignment (const_tree exp, HOST_WIDE_INT align) | |
4403 | { | |
4404 | if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) | |
4405 | && !optimize_size) | |
4406 | return MAX (align, BITS_PER_WORD); | |
4407 | return align; | |
4408 | } | |
4409 | ||
4410 | /* Implement TARGET_STARTING_FRAME_OFFSET. */ | |
4411 | ||
4412 | static HOST_WIDE_INT | |
4413 | xtensa_starting_frame_offset (void) | |
4414 | { | |
4415 | if (FRAME_GROWS_DOWNWARD) | |
4416 | return 0; | |
4417 | return crtl->outgoing_args_size; | |
4418 | } | |
4419 | ||
4420 | /* Implement TARGET_ASAN_SHADOW_OFFSET. */ | |
4421 | ||
4422 | static unsigned HOST_WIDE_INT | |
4423 | xtensa_asan_shadow_offset (void) | |
4424 | { | |
4425 | return HOST_WIDE_INT_UC (0x10000000); | |
4426 | } | |
4427 | ||
4428 | #include "gt-xtensa.h" |