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1 | /* Functions specific to running gdb native on IA-64 running | |
2 | GNU/Linux. | |
3 | ||
4 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
5 | Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
22 | Boston, MA 02110-1301, USA. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "gdb_string.h" | |
26 | #include "inferior.h" | |
27 | #include "target.h" | |
28 | #include "gdbcore.h" | |
29 | #include "regcache.h" | |
30 | #include "ia64-tdep.h" | |
31 | #include "linux-nat.h" | |
32 | ||
33 | #include <signal.h> | |
34 | #include <sys/ptrace.h> | |
35 | #include "gdb_wait.h" | |
36 | #ifdef HAVE_SYS_REG_H | |
37 | #include <sys/reg.h> | |
38 | #endif | |
39 | #include <sys/syscall.h> | |
40 | #include <sys/user.h> | |
41 | ||
42 | #include <asm/ptrace_offsets.h> | |
43 | #include <sys/procfs.h> | |
44 | ||
45 | /* Prototypes for supply_gregset etc. */ | |
46 | #include "gregset.h" | |
47 | ||
48 | /* These must match the order of the register names. | |
49 | ||
50 | Some sort of lookup table is needed because the offsets associated | |
51 | with the registers are all over the board. */ | |
52 | ||
53 | static int u_offsets[] = | |
54 | { | |
55 | /* general registers */ | |
56 | -1, /* gr0 not available; i.e, it's always zero */ | |
57 | PT_R1, | |
58 | PT_R2, | |
59 | PT_R3, | |
60 | PT_R4, | |
61 | PT_R5, | |
62 | PT_R6, | |
63 | PT_R7, | |
64 | PT_R8, | |
65 | PT_R9, | |
66 | PT_R10, | |
67 | PT_R11, | |
68 | PT_R12, | |
69 | PT_R13, | |
70 | PT_R14, | |
71 | PT_R15, | |
72 | PT_R16, | |
73 | PT_R17, | |
74 | PT_R18, | |
75 | PT_R19, | |
76 | PT_R20, | |
77 | PT_R21, | |
78 | PT_R22, | |
79 | PT_R23, | |
80 | PT_R24, | |
81 | PT_R25, | |
82 | PT_R26, | |
83 | PT_R27, | |
84 | PT_R28, | |
85 | PT_R29, | |
86 | PT_R30, | |
87 | PT_R31, | |
88 | /* gr32 through gr127 not directly available via the ptrace interface */ | |
89 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
90 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
91 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
92 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
93 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
94 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
95 | /* Floating point registers */ | |
96 | -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */ | |
97 | PT_F2, | |
98 | PT_F3, | |
99 | PT_F4, | |
100 | PT_F5, | |
101 | PT_F6, | |
102 | PT_F7, | |
103 | PT_F8, | |
104 | PT_F9, | |
105 | PT_F10, | |
106 | PT_F11, | |
107 | PT_F12, | |
108 | PT_F13, | |
109 | PT_F14, | |
110 | PT_F15, | |
111 | PT_F16, | |
112 | PT_F17, | |
113 | PT_F18, | |
114 | PT_F19, | |
115 | PT_F20, | |
116 | PT_F21, | |
117 | PT_F22, | |
118 | PT_F23, | |
119 | PT_F24, | |
120 | PT_F25, | |
121 | PT_F26, | |
122 | PT_F27, | |
123 | PT_F28, | |
124 | PT_F29, | |
125 | PT_F30, | |
126 | PT_F31, | |
127 | PT_F32, | |
128 | PT_F33, | |
129 | PT_F34, | |
130 | PT_F35, | |
131 | PT_F36, | |
132 | PT_F37, | |
133 | PT_F38, | |
134 | PT_F39, | |
135 | PT_F40, | |
136 | PT_F41, | |
137 | PT_F42, | |
138 | PT_F43, | |
139 | PT_F44, | |
140 | PT_F45, | |
141 | PT_F46, | |
142 | PT_F47, | |
143 | PT_F48, | |
144 | PT_F49, | |
145 | PT_F50, | |
146 | PT_F51, | |
147 | PT_F52, | |
148 | PT_F53, | |
149 | PT_F54, | |
150 | PT_F55, | |
151 | PT_F56, | |
152 | PT_F57, | |
153 | PT_F58, | |
154 | PT_F59, | |
155 | PT_F60, | |
156 | PT_F61, | |
157 | PT_F62, | |
158 | PT_F63, | |
159 | PT_F64, | |
160 | PT_F65, | |
161 | PT_F66, | |
162 | PT_F67, | |
163 | PT_F68, | |
164 | PT_F69, | |
165 | PT_F70, | |
166 | PT_F71, | |
167 | PT_F72, | |
168 | PT_F73, | |
169 | PT_F74, | |
170 | PT_F75, | |
171 | PT_F76, | |
172 | PT_F77, | |
173 | PT_F78, | |
174 | PT_F79, | |
175 | PT_F80, | |
176 | PT_F81, | |
177 | PT_F82, | |
178 | PT_F83, | |
179 | PT_F84, | |
180 | PT_F85, | |
181 | PT_F86, | |
182 | PT_F87, | |
183 | PT_F88, | |
184 | PT_F89, | |
185 | PT_F90, | |
186 | PT_F91, | |
187 | PT_F92, | |
188 | PT_F93, | |
189 | PT_F94, | |
190 | PT_F95, | |
191 | PT_F96, | |
192 | PT_F97, | |
193 | PT_F98, | |
194 | PT_F99, | |
195 | PT_F100, | |
196 | PT_F101, | |
197 | PT_F102, | |
198 | PT_F103, | |
199 | PT_F104, | |
200 | PT_F105, | |
201 | PT_F106, | |
202 | PT_F107, | |
203 | PT_F108, | |
204 | PT_F109, | |
205 | PT_F110, | |
206 | PT_F111, | |
207 | PT_F112, | |
208 | PT_F113, | |
209 | PT_F114, | |
210 | PT_F115, | |
211 | PT_F116, | |
212 | PT_F117, | |
213 | PT_F118, | |
214 | PT_F119, | |
215 | PT_F120, | |
216 | PT_F121, | |
217 | PT_F122, | |
218 | PT_F123, | |
219 | PT_F124, | |
220 | PT_F125, | |
221 | PT_F126, | |
222 | PT_F127, | |
223 | /* predicate registers - we don't fetch these individually */ | |
224 | -1, -1, -1, -1, -1, -1, -1, -1, | |
225 | -1, -1, -1, -1, -1, -1, -1, -1, | |
226 | -1, -1, -1, -1, -1, -1, -1, -1, | |
227 | -1, -1, -1, -1, -1, -1, -1, -1, | |
228 | -1, -1, -1, -1, -1, -1, -1, -1, | |
229 | -1, -1, -1, -1, -1, -1, -1, -1, | |
230 | -1, -1, -1, -1, -1, -1, -1, -1, | |
231 | -1, -1, -1, -1, -1, -1, -1, -1, | |
232 | /* branch registers */ | |
233 | PT_B0, | |
234 | PT_B1, | |
235 | PT_B2, | |
236 | PT_B3, | |
237 | PT_B4, | |
238 | PT_B5, | |
239 | PT_B6, | |
240 | PT_B7, | |
241 | /* virtual frame pointer and virtual return address pointer */ | |
242 | -1, -1, | |
243 | /* other registers */ | |
244 | PT_PR, | |
245 | PT_CR_IIP, /* ip */ | |
246 | PT_CR_IPSR, /* psr */ | |
247 | PT_CFM, /* cfm */ | |
248 | /* kernel registers not visible via ptrace interface (?) */ | |
249 | -1, -1, -1, -1, -1, -1, -1, -1, | |
250 | /* hole */ | |
251 | -1, -1, -1, -1, -1, -1, -1, -1, | |
252 | PT_AR_RSC, | |
253 | PT_AR_BSP, | |
254 | PT_AR_BSPSTORE, | |
255 | PT_AR_RNAT, | |
256 | -1, | |
257 | -1, /* Not available: FCR, IA32 floating control register */ | |
258 | -1, -1, | |
259 | -1, /* Not available: EFLAG */ | |
260 | -1, /* Not available: CSD */ | |
261 | -1, /* Not available: SSD */ | |
262 | -1, /* Not available: CFLG */ | |
263 | -1, /* Not available: FSR */ | |
264 | -1, /* Not available: FIR */ | |
265 | -1, /* Not available: FDR */ | |
266 | -1, | |
267 | PT_AR_CCV, | |
268 | -1, -1, -1, | |
269 | PT_AR_UNAT, | |
270 | -1, -1, -1, | |
271 | PT_AR_FPSR, | |
272 | -1, -1, -1, | |
273 | -1, /* Not available: ITC */ | |
274 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
275 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
276 | PT_AR_PFS, | |
277 | PT_AR_LC, | |
278 | -1, /* Not available: EC, the Epilog Count register */ | |
279 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
280 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
281 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
282 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
283 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
284 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
285 | -1, | |
286 | /* nat bits - not fetched directly; instead we obtain these bits from | |
287 | either rnat or unat or from memory. */ | |
288 | -1, -1, -1, -1, -1, -1, -1, -1, | |
289 | -1, -1, -1, -1, -1, -1, -1, -1, | |
290 | -1, -1, -1, -1, -1, -1, -1, -1, | |
291 | -1, -1, -1, -1, -1, -1, -1, -1, | |
292 | -1, -1, -1, -1, -1, -1, -1, -1, | |
293 | -1, -1, -1, -1, -1, -1, -1, -1, | |
294 | -1, -1, -1, -1, -1, -1, -1, -1, | |
295 | -1, -1, -1, -1, -1, -1, -1, -1, | |
296 | -1, -1, -1, -1, -1, -1, -1, -1, | |
297 | -1, -1, -1, -1, -1, -1, -1, -1, | |
298 | -1, -1, -1, -1, -1, -1, -1, -1, | |
299 | -1, -1, -1, -1, -1, -1, -1, -1, | |
300 | -1, -1, -1, -1, -1, -1, -1, -1, | |
301 | -1, -1, -1, -1, -1, -1, -1, -1, | |
302 | -1, -1, -1, -1, -1, -1, -1, -1, | |
303 | -1, -1, -1, -1, -1, -1, -1, -1, | |
304 | }; | |
305 | ||
306 | static CORE_ADDR | |
307 | ia64_register_addr (int regno) | |
308 | { | |
309 | CORE_ADDR addr; | |
310 | ||
311 | if (regno < 0 || regno >= NUM_REGS) | |
312 | error (_("Invalid register number %d."), regno); | |
313 | ||
314 | if (u_offsets[regno] == -1) | |
315 | addr = 0; | |
316 | else | |
317 | addr = (CORE_ADDR) u_offsets[regno]; | |
318 | ||
319 | return addr; | |
320 | } | |
321 | ||
322 | static int | |
323 | ia64_cannot_fetch_register (int regno) | |
324 | { | |
325 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1; | |
326 | } | |
327 | ||
328 | static int | |
329 | ia64_cannot_store_register (int regno) | |
330 | { | |
331 | /* Rationale behind not permitting stores to bspstore... | |
332 | ||
333 | The IA-64 architecture provides bspstore and bsp which refer | |
334 | memory locations in the RSE's backing store. bspstore is the | |
335 | next location which will be written when the RSE needs to write | |
336 | to memory. bsp is the address at which r32 in the current frame | |
337 | would be found if it were written to the backing store. | |
338 | ||
339 | The IA-64 architecture provides read-only access to bsp and | |
340 | read/write access to bspstore (but only when the RSE is in | |
341 | the enforced lazy mode). It should be noted that stores | |
342 | to bspstore also affect the value of bsp. Changing bspstore | |
343 | does not affect the number of dirty entries between bspstore | |
344 | and bsp, so changing bspstore by N words will also cause bsp | |
345 | to be changed by (roughly) N as well. (It could be N-1 or N+1 | |
346 | depending upon where the NaT collection bits fall.) | |
347 | ||
348 | OTOH, the Linux kernel provides read/write access to bsp (and | |
349 | currently read/write access to bspstore as well). But it | |
350 | is definitely the case that if you change one, the other | |
351 | will change at the same time. It is more useful to gdb to | |
352 | be able to change bsp. So in order to prevent strange and | |
353 | undesirable things from happening when a dummy stack frame | |
354 | is popped (after calling an inferior function), we allow | |
355 | bspstore to be read, but not written. (Note that popping | |
356 | a (generic) dummy stack frame causes all registers that | |
357 | were previously read from the inferior process to be written | |
358 | back.) */ | |
359 | ||
360 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1 | |
361 | || regno == IA64_BSPSTORE_REGNUM; | |
362 | } | |
363 | ||
364 | void | |
365 | supply_gregset (struct regcache *regcache, const gregset_t *gregsetp) | |
366 | { | |
367 | int regi; | |
368 | const greg_t *regp = (const greg_t *) gregsetp; | |
369 | ||
370 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
371 | { | |
372 | regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM)); | |
373 | } | |
374 | ||
375 | /* FIXME: NAT collection bits are at index 32; gotta deal with these | |
376 | somehow... */ | |
377 | ||
378 | regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33); | |
379 | ||
380 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
381 | { | |
382 | regcache_raw_supply (regcache, regi, | |
383 | regp + 34 + (regi - IA64_BR0_REGNUM)); | |
384 | } | |
385 | ||
386 | regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42); | |
387 | regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43); | |
388 | regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44); | |
389 | regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45); | |
390 | regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46); | |
391 | regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47); | |
392 | regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48); | |
393 | regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49); | |
394 | regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50); | |
395 | regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51); | |
396 | regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52); | |
397 | regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53); | |
398 | regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54); | |
399 | } | |
400 | ||
401 | void | |
402 | fill_gregset (const struct regcache *regcache, gregset_t *gregsetp, int regno) | |
403 | { | |
404 | int regi; | |
405 | greg_t *regp = (greg_t *) gregsetp; | |
406 | ||
407 | #define COPY_REG(_idx_,_regi_) \ | |
408 | if ((regno == -1) || regno == _regi_) \ | |
409 | regcache_raw_collect (regcache, _regi_, regp + _idx_) | |
410 | ||
411 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) | |
412 | { | |
413 | COPY_REG (regi - IA64_GR0_REGNUM, regi); | |
414 | } | |
415 | ||
416 | /* FIXME: NAT collection bits at index 32? */ | |
417 | ||
418 | COPY_REG (33, IA64_PR_REGNUM); | |
419 | ||
420 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) | |
421 | { | |
422 | COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); | |
423 | } | |
424 | ||
425 | COPY_REG (42, IA64_IP_REGNUM); | |
426 | COPY_REG (43, IA64_CFM_REGNUM); | |
427 | COPY_REG (44, IA64_PSR_REGNUM); | |
428 | COPY_REG (45, IA64_RSC_REGNUM); | |
429 | COPY_REG (46, IA64_BSP_REGNUM); | |
430 | COPY_REG (47, IA64_BSPSTORE_REGNUM); | |
431 | COPY_REG (48, IA64_RNAT_REGNUM); | |
432 | COPY_REG (49, IA64_CCV_REGNUM); | |
433 | COPY_REG (50, IA64_UNAT_REGNUM); | |
434 | COPY_REG (51, IA64_FPSR_REGNUM); | |
435 | COPY_REG (52, IA64_PFS_REGNUM); | |
436 | COPY_REG (53, IA64_LC_REGNUM); | |
437 | COPY_REG (54, IA64_EC_REGNUM); | |
438 | } | |
439 | ||
440 | /* Given a pointer to a floating point register set in /proc format | |
441 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
442 | idea of the current floating point register values. */ | |
443 | ||
444 | void | |
445 | supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp) | |
446 | { | |
447 | int regi; | |
448 | const char *from; | |
449 | ||
450 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
451 | { | |
452 | from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); | |
453 | regcache_raw_supply (regcache, regi, from); | |
454 | } | |
455 | } | |
456 | ||
457 | /* Given a pointer to a floating point register set in /proc format | |
458 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
459 | of the current floating point register set. If REGNO is -1, update | |
460 | them all. */ | |
461 | ||
462 | void | |
463 | fill_fpregset (const struct regcache *regcache, | |
464 | fpregset_t *fpregsetp, int regno) | |
465 | { | |
466 | int regi; | |
467 | ||
468 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) | |
469 | { | |
470 | if ((regno == -1) || (regno == regi)) | |
471 | regcache_raw_collect (regcache, regi, | |
472 | &((*fpregsetp)[regi - IA64_FR0_REGNUM])); | |
473 | } | |
474 | } | |
475 | ||
476 | #define IA64_PSR_DB (1UL << 24) | |
477 | #define IA64_PSR_DD (1UL << 39) | |
478 | ||
479 | static void | |
480 | enable_watchpoints_in_psr (ptid_t ptid) | |
481 | { | |
482 | CORE_ADDR psr; | |
483 | ||
484 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); | |
485 | if (!(psr & IA64_PSR_DB)) | |
486 | { | |
487 | psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware | |
488 | watchpoints and breakpoints. */ | |
489 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); | |
490 | } | |
491 | } | |
492 | ||
493 | static long | |
494 | fetch_debug_register (ptid_t ptid, int idx) | |
495 | { | |
496 | long val; | |
497 | int tid; | |
498 | ||
499 | tid = TIDGET (ptid); | |
500 | if (tid == 0) | |
501 | tid = PIDGET (ptid); | |
502 | ||
503 | val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0); | |
504 | ||
505 | return val; | |
506 | } | |
507 | ||
508 | static void | |
509 | store_debug_register (ptid_t ptid, int idx, long val) | |
510 | { | |
511 | int tid; | |
512 | ||
513 | tid = TIDGET (ptid); | |
514 | if (tid == 0) | |
515 | tid = PIDGET (ptid); | |
516 | ||
517 | (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val); | |
518 | } | |
519 | ||
520 | static void | |
521 | fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) | |
522 | { | |
523 | if (dbr_addr) | |
524 | *dbr_addr = fetch_debug_register (ptid, 2 * idx); | |
525 | if (dbr_mask) | |
526 | *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1); | |
527 | } | |
528 | ||
529 | static void | |
530 | store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) | |
531 | { | |
532 | if (dbr_addr) | |
533 | store_debug_register (ptid, 2 * idx, *dbr_addr); | |
534 | if (dbr_mask) | |
535 | store_debug_register (ptid, 2 * idx + 1, *dbr_mask); | |
536 | } | |
537 | ||
538 | static int | |
539 | is_power_of_2 (int val) | |
540 | { | |
541 | int i, onecount; | |
542 | ||
543 | onecount = 0; | |
544 | for (i = 0; i < 8 * sizeof (val); i++) | |
545 | if (val & (1 << i)) | |
546 | onecount++; | |
547 | ||
548 | return onecount <= 1; | |
549 | } | |
550 | ||
551 | static int | |
552 | ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw) | |
553 | { | |
554 | ptid_t ptid = inferior_ptid; | |
555 | int idx; | |
556 | long dbr_addr, dbr_mask; | |
557 | int max_watchpoints = 4; | |
558 | ||
559 | if (len <= 0 || !is_power_of_2 (len)) | |
560 | return -1; | |
561 | ||
562 | for (idx = 0; idx < max_watchpoints; idx++) | |
563 | { | |
564 | fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask); | |
565 | if ((dbr_mask & (0x3UL << 62)) == 0) | |
566 | { | |
567 | /* Exit loop if both r and w bits clear */ | |
568 | break; | |
569 | } | |
570 | } | |
571 | ||
572 | if (idx == max_watchpoints) | |
573 | return -1; | |
574 | ||
575 | dbr_addr = (long) addr; | |
576 | dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ | |
577 | dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ | |
578 | switch (rw) | |
579 | { | |
580 | case hw_write: | |
581 | dbr_mask |= (1L << 62); /* Set w bit */ | |
582 | break; | |
583 | case hw_read: | |
584 | dbr_mask |= (1L << 63); /* Set r bit */ | |
585 | break; | |
586 | case hw_access: | |
587 | dbr_mask |= (3L << 62); /* Set both r and w bits */ | |
588 | break; | |
589 | default: | |
590 | return -1; | |
591 | } | |
592 | ||
593 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); | |
594 | enable_watchpoints_in_psr (ptid); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | static int | |
600 | ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type) | |
601 | { | |
602 | ptid_t ptid = inferior_ptid; | |
603 | int idx; | |
604 | long dbr_addr, dbr_mask; | |
605 | int max_watchpoints = 4; | |
606 | ||
607 | if (len <= 0 || !is_power_of_2 (len)) | |
608 | return -1; | |
609 | ||
610 | for (idx = 0; idx < max_watchpoints; idx++) | |
611 | { | |
612 | fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); | |
613 | if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) | |
614 | { | |
615 | dbr_addr = 0; | |
616 | dbr_mask = 0; | |
617 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); | |
618 | return 0; | |
619 | } | |
620 | } | |
621 | return -1; | |
622 | } | |
623 | ||
624 | static int | |
625 | ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) | |
626 | { | |
627 | CORE_ADDR psr; | |
628 | int tid; | |
629 | struct siginfo siginfo; | |
630 | ptid_t ptid = inferior_ptid; | |
631 | ||
632 | tid = TIDGET(ptid); | |
633 | if (tid == 0) | |
634 | tid = PIDGET (ptid); | |
635 | ||
636 | errno = 0; | |
637 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo); | |
638 | ||
639 | if (errno != 0 || siginfo.si_signo != SIGTRAP || | |
640 | (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
641 | return 0; | |
642 | ||
643 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); | |
644 | psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint | |
645 | for the next instruction */ | |
646 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); | |
647 | ||
648 | *addr_p = (CORE_ADDR)siginfo.si_addr; | |
649 | return 1; | |
650 | } | |
651 | ||
652 | static int | |
653 | ia64_linux_stopped_by_watchpoint (void) | |
654 | { | |
655 | CORE_ADDR addr; | |
656 | return ia64_linux_stopped_data_address (¤t_target, &addr); | |
657 | } | |
658 | ||
659 | static int | |
660 | ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
661 | { | |
662 | return 1; | |
663 | } | |
664 | ||
665 | ||
666 | /* Fetch register REGNUM from the inferior. */ | |
667 | ||
668 | static void | |
669 | ia64_linux_fetch_register (struct regcache *regcache, int regnum) | |
670 | { | |
671 | CORE_ADDR addr; | |
672 | size_t size; | |
673 | PTRACE_TYPE_RET *buf; | |
674 | int pid, i; | |
675 | ||
676 | if (ia64_cannot_fetch_register (regnum)) | |
677 | { | |
678 | regcache_raw_supply (regcache, regnum, NULL); | |
679 | return; | |
680 | } | |
681 | ||
682 | /* Cater for systems like GNU/Linux, that implement threads as | |
683 | separate processes. */ | |
684 | pid = ptid_get_lwp (inferior_ptid); | |
685 | if (pid == 0) | |
686 | pid = ptid_get_pid (inferior_ptid); | |
687 | ||
688 | /* This isn't really an address, but ptrace thinks of it as one. */ | |
689 | addr = ia64_register_addr (regnum); | |
690 | size = register_size (current_gdbarch, regnum); | |
691 | ||
692 | gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); | |
693 | buf = alloca (size); | |
694 | ||
695 | /* Read the register contents from the inferior a chunk at a time. */ | |
696 | for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) | |
697 | { | |
698 | errno = 0; | |
699 | buf[i] = ptrace (PT_READ_U, pid, (PTRACE_TYPE_ARG3)addr, 0); | |
700 | if (errno != 0) | |
701 | error (_("Couldn't read register %s (#%d): %s."), | |
702 | REGISTER_NAME (regnum), regnum, safe_strerror (errno)); | |
703 | ||
704 | addr += sizeof (PTRACE_TYPE_RET); | |
705 | } | |
706 | regcache_raw_supply (regcache, regnum, buf); | |
707 | } | |
708 | ||
709 | /* Fetch register REGNUM from the inferior. If REGNUM is -1, do this | |
710 | for all registers. */ | |
711 | ||
712 | static void | |
713 | ia64_linux_fetch_registers (struct regcache *regcache, int regnum) | |
714 | { | |
715 | if (regnum == -1) | |
716 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
717 | ia64_linux_fetch_register (regcache, regnum); | |
718 | else | |
719 | ia64_linux_fetch_register (regcache, regnum); | |
720 | } | |
721 | ||
722 | /* Store register REGNUM into the inferior. */ | |
723 | ||
724 | static void | |
725 | ia64_linux_store_register (const struct regcache *regcache, int regnum) | |
726 | { | |
727 | CORE_ADDR addr; | |
728 | size_t size; | |
729 | PTRACE_TYPE_RET *buf; | |
730 | int pid, i; | |
731 | ||
732 | if (ia64_cannot_store_register (regnum)) | |
733 | return; | |
734 | ||
735 | /* Cater for systems like GNU/Linux, that implement threads as | |
736 | separate processes. */ | |
737 | pid = ptid_get_lwp (inferior_ptid); | |
738 | if (pid == 0) | |
739 | pid = ptid_get_pid (inferior_ptid); | |
740 | ||
741 | /* This isn't really an address, but ptrace thinks of it as one. */ | |
742 | addr = ia64_register_addr (regnum); | |
743 | size = register_size (current_gdbarch, regnum); | |
744 | ||
745 | gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0); | |
746 | buf = alloca (size); | |
747 | ||
748 | /* Write the register contents into the inferior a chunk at a time. */ | |
749 | regcache_raw_collect (regcache, regnum, buf); | |
750 | for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++) | |
751 | { | |
752 | errno = 0; | |
753 | ptrace (PT_WRITE_U, pid, (PTRACE_TYPE_ARG3)addr, buf[i]); | |
754 | if (errno != 0) | |
755 | error (_("Couldn't write register %s (#%d): %s."), | |
756 | REGISTER_NAME (regnum), regnum, safe_strerror (errno)); | |
757 | ||
758 | addr += sizeof (PTRACE_TYPE_RET); | |
759 | } | |
760 | } | |
761 | ||
762 | /* Store register REGNUM back into the inferior. If REGNUM is -1, do | |
763 | this for all registers. */ | |
764 | ||
765 | static void | |
766 | ia64_linux_store_registers (struct regcache *regcache, int regnum) | |
767 | { | |
768 | if (regnum == -1) | |
769 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
770 | ia64_linux_store_register (regcache, regnum); | |
771 | else | |
772 | ia64_linux_store_register (regcache, regnum); | |
773 | } | |
774 | ||
775 | ||
776 | static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object, | |
777 | const char *, gdb_byte *, const gdb_byte *, | |
778 | ULONGEST, LONGEST); | |
779 | ||
780 | static LONGEST | |
781 | ia64_linux_xfer_partial (struct target_ops *ops, | |
782 | enum target_object object, | |
783 | const char *annex, | |
784 | gdb_byte *readbuf, const gdb_byte *writebuf, | |
785 | ULONGEST offset, LONGEST len) | |
786 | { | |
787 | if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0) | |
788 | return syscall (__NR_getunwind, readbuf, len); | |
789 | ||
790 | return super_xfer_partial (ops, object, annex, readbuf, writebuf, | |
791 | offset, len); | |
792 | } | |
793 | ||
794 | void _initialize_ia64_linux_nat (void); | |
795 | ||
796 | void | |
797 | _initialize_ia64_linux_nat (void) | |
798 | { | |
799 | struct target_ops *t = linux_target (); | |
800 | ||
801 | /* Fill in the generic GNU/Linux methods. */ | |
802 | t = linux_target (); | |
803 | ||
804 | /* Override the default fetch/store register routines. */ | |
805 | t->to_fetch_registers = ia64_linux_fetch_registers; | |
806 | t->to_store_registers = ia64_linux_store_registers; | |
807 | ||
808 | /* Override the default to_xfer_partial. */ | |
809 | super_xfer_partial = t->to_xfer_partial; | |
810 | t->to_xfer_partial = ia64_linux_xfer_partial; | |
811 | ||
812 | /* Override watchpoint routines. */ | |
813 | ||
814 | /* The IA-64 architecture can step over a watch point (without triggering | |
815 | it again) if the "dd" (data debug fault disable) bit in the processor | |
816 | status word is set. | |
817 | ||
818 | This PSR bit is set in ia64_linux_stopped_by_watchpoint when the | |
819 | code there has determined that a hardware watchpoint has indeed | |
820 | been hit. The CPU will then be able to execute one instruction | |
821 | without triggering a watchpoint. */ | |
822 | ||
823 | t->to_have_steppable_watchpoint = 1; | |
824 | t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint; | |
825 | t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint; | |
826 | t->to_stopped_data_address = ia64_linux_stopped_data_address; | |
827 | t->to_insert_watchpoint = ia64_linux_insert_watchpoint; | |
828 | t->to_remove_watchpoint = ia64_linux_remove_watchpoint; | |
829 | ||
830 | /* Register the target. */ | |
831 | linux_nat_add_target (t); | |
832 | } |