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1 | /* | |
2 | * Configuation settings for the Freescale MCF54451 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M54451EVB_H | |
15 | #define _M54451EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
21 | #define CONFIG_M54451EVB /* M54451EVB board */ | |
22 | ||
23 | #define CONFIG_DISPLAY_BOARDINFO | |
24 | ||
25 | #define CONFIG_MCFUART | |
26 | #define CONFIG_SYS_UART_PORT (0) | |
27 | #define CONFIG_BAUDRATE 115200 | |
28 | ||
29 | #undef CONFIG_WATCHDOG | |
30 | ||
31 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
32 | ||
33 | /* | |
34 | * BOOTP options | |
35 | */ | |
36 | #define CONFIG_BOOTP_BOOTFILESIZE | |
37 | #define CONFIG_BOOTP_BOOTPATH | |
38 | #define CONFIG_BOOTP_GATEWAY | |
39 | #define CONFIG_BOOTP_HOSTNAME | |
40 | ||
41 | /* Command line configuration */ | |
42 | #define CONFIG_CMD_CACHE | |
43 | #define CONFIG_CMD_DATE | |
44 | #define CONFIG_CMD_DHCP | |
45 | #define CONFIG_CMD_ELF | |
46 | #define CONFIG_CMD_I2C | |
47 | #undef CONFIG_CMD_JFFS2 | |
48 | #define CONFIG_CMD_MII | |
49 | #define CONFIG_CMD_PING | |
50 | #define CONFIG_CMD_REGINFO | |
51 | #define CONFIG_CMD_SPI | |
52 | #define CONFIG_CMD_SF | |
53 | ||
54 | ||
55 | /* Network configuration */ | |
56 | #define CONFIG_MCFFEC | |
57 | #ifdef CONFIG_MCFFEC | |
58 | # define CONFIG_MII 1 | |
59 | # define CONFIG_MII_INIT 1 | |
60 | # define CONFIG_SYS_DISCOVER_PHY | |
61 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
62 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
63 | ||
64 | # define CONFIG_SYS_FEC0_PINMUX 0 | |
65 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
66 | # define MCFFEC_TOUT_LOOP 50000 | |
67 | ||
68 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
69 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)" | |
70 | # define CONFIG_ETHPRIME "FEC0" | |
71 | # define CONFIG_IPADDR 192.162.1.2 | |
72 | # define CONFIG_NETMASK 255.255.255.0 | |
73 | # define CONFIG_SERVERIP 192.162.1.1 | |
74 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
75 | ||
76 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ | |
77 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
78 | # define FECDUPLEX FULL | |
79 | # define FECSPEED _100BASET | |
80 | # else | |
81 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
82 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
83 | # endif | |
84 | # endif /* CONFIG_SYS_DISCOVER_PHY */ | |
85 | #endif | |
86 | ||
87 | #define CONFIG_HOSTNAME M54451EVB | |
88 | #ifdef CONFIG_SYS_STMICRO_BOOT | |
89 | /* ST Micro serial flash */ | |
90 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
91 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
92 | "netdev=eth0\0" \ | |
93 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
94 | "loadaddr=0x40010000\0" \ | |
95 | "sbfhdr=sbfhdr.bin\0" \ | |
96 | "uboot=u-boot.bin\0" \ | |
97 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
98 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ | |
99 | "upd=run load; run prog\0" \ | |
100 | "prog=sf probe 0:1 1000000 3;" \ | |
101 | "sf erase 0 30000;" \ | |
102 | "sf write ${loadaddr} 0 30000;" \ | |
103 | "save\0" \ | |
104 | "" | |
105 | #else | |
106 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
107 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
108 | "netdev=eth0\0" \ | |
109 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
110 | "loadaddr=40010000\0" \ | |
111 | "u-boot=u-boot.bin\0" \ | |
112 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
113 | "upd=run load; run prog\0" \ | |
114 | "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ | |
115 | "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ | |
116 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
117 | "save\0" \ | |
118 | "" | |
119 | #endif | |
120 | ||
121 | /* Realtime clock */ | |
122 | #define CONFIG_MCFRTC | |
123 | #undef RTC_DEBUG | |
124 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) | |
125 | ||
126 | /* Timer */ | |
127 | #define CONFIG_MCFTMR | |
128 | #undef CONFIG_MCFPIT | |
129 | ||
130 | /* I2c */ | |
131 | #define CONFIG_SYS_I2C | |
132 | #define CONFIG_SYS_I2C_FSL | |
133 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
134 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
135 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
136 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
137 | ||
138 | /* DSPI and Serial Flash */ | |
139 | #define CONFIG_CF_SPI | |
140 | #define CONFIG_CF_DSPI | |
141 | #define CONFIG_SERIAL_FLASH | |
142 | #define CONFIG_HARD_SPI | |
143 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 | |
144 | #ifdef CONFIG_CMD_SPI | |
145 | # define CONFIG_SPI_FLASH_STMICRO | |
146 | ||
147 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ | |
148 | DSPI_CTAR_PCSSCK_1CLK | \ | |
149 | DSPI_CTAR_PASC(0) | \ | |
150 | DSPI_CTAR_PDT(0) | \ | |
151 | DSPI_CTAR_CSSCK(0) | \ | |
152 | DSPI_CTAR_ASC(0) | \ | |
153 | DSPI_CTAR_DT(1)) | |
154 | # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) | |
155 | # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) | |
156 | #endif | |
157 | ||
158 | /* Input, PCI, Flexbus, and VCO */ | |
159 | #define CONFIG_EXTRA_CLOCK | |
160 | ||
161 | #define CONFIG_PRAM 2048 /* 2048 KB */ | |
162 | ||
163 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
164 | ||
165 | #if defined(CONFIG_CMD_KGDB) | |
166 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
167 | #else | |
168 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
169 | #endif | |
170 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
171 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
172 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
173 | ||
174 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) | |
175 | ||
176 | #define CONFIG_SYS_MBAR 0xFC000000 | |
177 | ||
178 | /* | |
179 | * Low Level Configuration Settings | |
180 | * (address mappings, register initial values, etc.) | |
181 | * You should know what you are doing if you make changes here. | |
182 | */ | |
183 | ||
184 | /*----------------------------------------------------------------------- | |
185 | * Definitions for initial stack pointer and data area (in DPRAM) | |
186 | */ | |
187 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
188 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ | |
189 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 | |
190 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) | |
191 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
192 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) | |
193 | ||
194 | /*----------------------------------------------------------------------- | |
195 | * Start addresses for the final memory configuration | |
196 | * (Set up by the startup code) | |
197 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
198 | */ | |
199 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
200 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ | |
201 | #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 | |
202 | #define CONFIG_SYS_SDRAM_CFG2 0x57670000 | |
203 | #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 | |
204 | #define CONFIG_SYS_SDRAM_EMOD 0x80810000 | |
205 | #define CONFIG_SYS_SDRAM_MODE 0x008D0000 | |
206 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 | |
207 | ||
208 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
209 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
210 | ||
211 | #ifdef CONFIG_CF_SBF | |
212 | # define CONFIG_SERIAL_BOOT | |
213 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) | |
214 | #else | |
215 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
216 | #endif | |
217 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
218 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
219 | ||
220 | /* Reserve 256 kB for malloc() */ | |
221 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
222 | /* | |
223 | * For booting Linux, the board info and command line data | |
224 | * have to be in the first 8 MB of memory, since this is | |
225 | * the maximum mapped by the Linux kernel during initialization ?? | |
226 | */ | |
227 | /* Initial Memory map for Linux */ | |
228 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) | |
229 | ||
230 | /* Configuration for environment | |
231 | * Environment is not embedded in u-boot. First time runing may have env | |
232 | * crc error warning if there is no correct environment on the flash. | |
233 | */ | |
234 | #if defined(CONFIG_SYS_STMICRO_BOOT) | |
235 | # define CONFIG_ENV_IS_IN_SPI_FLASH 1 | |
236 | # define CONFIG_ENV_SPI_CS 1 | |
237 | # define CONFIG_ENV_OFFSET 0x20000 | |
238 | # define CONFIG_ENV_SIZE 0x2000 | |
239 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
240 | #else | |
241 | # define CONFIG_ENV_IS_IN_FLASH 1 | |
242 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) | |
243 | # define CONFIG_ENV_SIZE 0x2000 | |
244 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
245 | #endif | |
246 | #undef CONFIG_ENV_OVERWRITE | |
247 | ||
248 | /* FLASH organization */ | |
249 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
250 | ||
251 | #define CONFIG_SYS_FLASH_CFI | |
252 | #ifdef CONFIG_SYS_FLASH_CFI | |
253 | ||
254 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
255 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
256 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ | |
257 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
258 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
259 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
260 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
261 | # define CONFIG_SYS_FLASH_CHECKSUM | |
262 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } | |
263 | ||
264 | #endif | |
265 | ||
266 | /* | |
267 | * This is setting for JFFS2 support in u-boot. | |
268 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
269 | */ | |
270 | #ifdef CONFIG_CMD_JFFS2 | |
271 | # define CONFIG_JFFS2_DEV "nor0" | |
272 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
273 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) | |
274 | #endif | |
275 | ||
276 | /* Cache Configuration */ | |
277 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
278 | ||
279 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
280 | CONFIG_SYS_INIT_RAM_SIZE - 8) | |
281 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
282 | CONFIG_SYS_INIT_RAM_SIZE - 4) | |
283 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) | |
284 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
285 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
286 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
287 | CF_ACR_EN | CF_ACR_SM_ALL) | |
288 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
289 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
290 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
291 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
292 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * Memory bank definitions | |
296 | */ | |
297 | /* | |
298 | * CS0 - NOR Flash 16MB | |
299 | * CS1 - Available | |
300 | * CS2 - Available | |
301 | * CS3 - Available | |
302 | * CS4 - Available | |
303 | * CS5 - Available | |
304 | */ | |
305 | ||
306 | /* Flash */ | |
307 | #define CONFIG_SYS_CS0_BASE 0x00000000 | |
308 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 | |
309 | #define CONFIG_SYS_CS0_CTRL 0x00004D80 | |
310 | ||
311 | #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE | |
312 | ||
313 | #endif /* _M54451EVB_H */ |