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1 | /* | |
2 | * Copyright 2004, 2011 Freescale Semiconductor. | |
3 | * (C) Copyright 2002,2003 Motorola,Inc. | |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | /* | |
10 | * mpc8540ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
15 | * search for CONFIG_SERVERIP, etc in this file. | |
16 | */ | |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
21 | /* | |
22 | * default CCARBAR is at 0xff700000 | |
23 | * assume U-Boot is less than 0.5MB | |
24 | */ | |
25 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
26 | ||
27 | #ifndef CONFIG_HAS_FEC | |
28 | #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ | |
29 | #endif | |
30 | ||
31 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
32 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
33 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
34 | #define CONFIG_ENV_OVERWRITE | |
35 | ||
36 | /* | |
37 | * sysclk for MPC85xx | |
38 | * | |
39 | * Two valid values are: | |
40 | * 33000000 | |
41 | * 66000000 | |
42 | * | |
43 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
44 | * is likely the desired value here, so that is now the default. | |
45 | * The board, however, can run at 66MHz. In any event, this value | |
46 | * must match the settings of some switches. Details can be found | |
47 | * in the README.mpc85xxads. | |
48 | * | |
49 | * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to | |
50 | * 33MHz to accommodate, based on a PCI pin. | |
51 | * Note that PCI-X won't work at 33MHz. | |
52 | */ | |
53 | ||
54 | #ifndef CONFIG_SYS_CLK_FREQ | |
55 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
56 | #endif | |
57 | ||
58 | /* | |
59 | * These can be toggled for performance analysis, otherwise use default. | |
60 | */ | |
61 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
62 | #define CONFIG_BTB /* toggle branch predition */ | |
63 | ||
64 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
65 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
66 | ||
67 | #define CONFIG_SYS_CCSRBAR 0xe0000000 | |
68 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
69 | ||
70 | /* DDR Setup */ | |
71 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
72 | #define CONFIG_DDR_SPD | |
73 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
74 | ||
75 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
76 | ||
77 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
78 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
79 | ||
80 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
81 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
82 | ||
83 | /* I2C addresses of SPD EEPROMs */ | |
84 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
85 | ||
86 | /* These are used when DDR doesn't use SPD. */ | |
87 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ | |
88 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
89 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
90 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
91 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
92 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
93 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
94 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
95 | ||
96 | /* | |
97 | * SDRAM on the Local Bus | |
98 | */ | |
99 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
100 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
101 | ||
102 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ | |
103 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
104 | ||
105 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ | |
106 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
108 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
109 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
110 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
111 | ||
112 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
113 | ||
114 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
115 | #define CONFIG_SYS_RAMBOOT | |
116 | #else | |
117 | #undef CONFIG_SYS_RAMBOOT | |
118 | #endif | |
119 | ||
120 | #define CONFIG_FLASH_CFI_DRIVER | |
121 | #define CONFIG_SYS_FLASH_CFI | |
122 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
123 | ||
124 | #undef CONFIG_CLOCKS_IN_MHZ | |
125 | ||
126 | /* | |
127 | * Local Bus Definitions | |
128 | */ | |
129 | ||
130 | /* | |
131 | * Base Register 2 and Option Register 2 configure SDRAM. | |
132 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. | |
133 | * | |
134 | * For BR2, need: | |
135 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
136 | * port-size = 32-bits = BR2[19:20] = 11 | |
137 | * no parity checking = BR2[21:22] = 00 | |
138 | * SDRAM for MSEL = BR2[24:26] = 011 | |
139 | * Valid = BR[31] = 1 | |
140 | * | |
141 | * 0 4 8 12 16 20 24 28 | |
142 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
143 | * | |
144 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into | |
145 | * FIXME: the top 17 bits of BR2. | |
146 | */ | |
147 | ||
148 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 | |
149 | ||
150 | /* | |
151 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
152 | * | |
153 | * For OR2, need: | |
154 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
155 | * XAM, OR2[17:18] = 11 | |
156 | * 9 columns OR2[19-21] = 010 | |
157 | * 13 rows OR2[23-25] = 100 | |
158 | * EAD set for extra time OR[31] = 1 | |
159 | * | |
160 | * 0 4 8 12 16 20 24 28 | |
161 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
162 | */ | |
163 | ||
164 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
165 | ||
166 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
167 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
168 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
169 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
170 | ||
171 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ | |
172 | | LSDMR_RFCR5 \ | |
173 | | LSDMR_PRETOACT3 \ | |
174 | | LSDMR_ACTTORW3 \ | |
175 | | LSDMR_BL8 \ | |
176 | | LSDMR_WRC2 \ | |
177 | | LSDMR_CL3 \ | |
178 | | LSDMR_RFEN \ | |
179 | ) | |
180 | ||
181 | /* | |
182 | * SDRAM Controller configuration sequence. | |
183 | */ | |
184 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) | |
185 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
186 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
187 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
188 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
189 | ||
190 | /* | |
191 | * 32KB, 8-bit wide for ADS config reg | |
192 | */ | |
193 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 | |
194 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
195 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
196 | ||
197 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
198 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
199 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ | |
200 | ||
201 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
202 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
203 | ||
204 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
205 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
206 | ||
207 | /* Serial Port */ | |
208 | #define CONFIG_CONS_INDEX 1 | |
209 | #define CONFIG_SYS_NS16550_SERIAL | |
210 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
211 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
212 | ||
213 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
214 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
215 | ||
216 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
217 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
218 | ||
219 | /* | |
220 | * I2C | |
221 | */ | |
222 | #define CONFIG_SYS_I2C | |
223 | #define CONFIG_SYS_I2C_FSL | |
224 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
225 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
226 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
227 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
228 | ||
229 | /* RapidIO MMU */ | |
230 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ | |
231 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ | |
232 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 | |
233 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
234 | ||
235 | /* | |
236 | * General PCI | |
237 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
238 | */ | |
239 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 | |
240 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
241 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
242 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
243 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 | |
244 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
245 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
246 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
247 | ||
248 | #if defined(CONFIG_PCI) | |
249 | #undef CONFIG_EEPRO100 | |
250 | #undef CONFIG_TULIP | |
251 | ||
252 | #if !defined(CONFIG_PCI_PNP) | |
253 | #define PCI_ENET0_IOADDR 0xe0000000 | |
254 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
255 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
256 | #endif | |
257 | ||
258 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
259 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
260 | ||
261 | #endif /* CONFIG_PCI */ | |
262 | ||
263 | #if defined(CONFIG_TSEC_ENET) | |
264 | ||
265 | #define CONFIG_MII 1 /* MII PHY management */ | |
266 | #define CONFIG_TSEC1 1 | |
267 | #define CONFIG_TSEC1_NAME "TSEC0" | |
268 | #define CONFIG_TSEC2 1 | |
269 | #define CONFIG_TSEC2_NAME "TSEC1" | |
270 | #define TSEC1_PHY_ADDR 0 | |
271 | #define TSEC2_PHY_ADDR 1 | |
272 | #define TSEC1_PHYIDX 0 | |
273 | #define TSEC2_PHYIDX 0 | |
274 | #define TSEC1_FLAGS TSEC_GIGABIT | |
275 | #define TSEC2_FLAGS TSEC_GIGABIT | |
276 | ||
277 | #if CONFIG_HAS_FEC | |
278 | #define CONFIG_MPC85XX_FEC 1 | |
279 | #define CONFIG_MPC85XX_FEC_NAME "FEC" | |
280 | #define FEC_PHY_ADDR 3 | |
281 | #define FEC_PHYIDX 0 | |
282 | #define FEC_FLAGS 0 | |
283 | #endif | |
284 | ||
285 | /* Options are: TSEC[0-1], FEC */ | |
286 | #define CONFIG_ETHPRIME "TSEC0" | |
287 | ||
288 | #endif /* CONFIG_TSEC_ENET */ | |
289 | ||
290 | /* | |
291 | * Environment | |
292 | */ | |
293 | #ifndef CONFIG_SYS_RAMBOOT | |
294 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
295 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) | |
296 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
297 | #define CONFIG_ENV_SIZE 0x2000 | |
298 | #else | |
299 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
300 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
301 | #define CONFIG_ENV_SIZE 0x2000 | |
302 | #endif | |
303 | ||
304 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
305 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
306 | ||
307 | /* | |
308 | * BOOTP options | |
309 | */ | |
310 | #define CONFIG_BOOTP_BOOTFILESIZE | |
311 | #define CONFIG_BOOTP_BOOTPATH | |
312 | #define CONFIG_BOOTP_GATEWAY | |
313 | #define CONFIG_BOOTP_HOSTNAME | |
314 | ||
315 | /* | |
316 | * Command line configuration. | |
317 | */ | |
318 | ||
319 | #if defined(CONFIG_PCI) | |
320 | #define CONFIG_CMD_PCI | |
321 | #endif | |
322 | ||
323 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
324 | ||
325 | /* | |
326 | * Miscellaneous configurable options | |
327 | */ | |
328 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
329 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
330 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
331 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
332 | ||
333 | #if defined(CONFIG_CMD_KGDB) | |
334 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
335 | #else | |
336 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
337 | #endif | |
338 | ||
339 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
340 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
341 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
342 | ||
343 | /* | |
344 | * For booting Linux, the board info and command line data | |
345 | * have to be in the first 64 MB of memory, since this is | |
346 | * the maximum mapped by the Linux kernel during initialization. | |
347 | */ | |
348 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ | |
349 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
350 | ||
351 | #if defined(CONFIG_CMD_KGDB) | |
352 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
353 | #endif | |
354 | ||
355 | /* | |
356 | * Environment Configuration | |
357 | */ | |
358 | ||
359 | /* The mac addresses for all ethernet interface */ | |
360 | #if defined(CONFIG_TSEC_ENET) | |
361 | #define CONFIG_HAS_ETH0 | |
362 | #define CONFIG_HAS_ETH1 | |
363 | #define CONFIG_HAS_ETH2 | |
364 | #endif | |
365 | ||
366 | #define CONFIG_IPADDR 192.168.1.253 | |
367 | ||
368 | #define CONFIG_HOSTNAME unknown | |
369 | #define CONFIG_ROOTPATH "/nfsroot" | |
370 | #define CONFIG_BOOTFILE "your.uImage" | |
371 | ||
372 | #define CONFIG_SERVERIP 192.168.1.1 | |
373 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
374 | #define CONFIG_NETMASK 255.255.255.0 | |
375 | ||
376 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
377 | ||
378 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
379 | ||
380 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
381 | "netdev=eth0\0" \ | |
382 | "consoledev=ttyS0\0" \ | |
383 | "ramdiskaddr=1000000\0" \ | |
384 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
385 | "fdtaddr=400000\0" \ | |
386 | "fdtfile=your.fdt.dtb\0" | |
387 | ||
388 | #define CONFIG_NFSBOOTCOMMAND \ | |
389 | "setenv bootargs root=/dev/nfs rw " \ | |
390 | "nfsroot=$serverip:$rootpath " \ | |
391 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
392 | "console=$consoledev,$baudrate $othbootargs;" \ | |
393 | "tftp $loadaddr $bootfile;" \ | |
394 | "tftp $fdtaddr $fdtfile;" \ | |
395 | "bootm $loadaddr - $fdtaddr" | |
396 | ||
397 | #define CONFIG_RAMBOOTCOMMAND \ | |
398 | "setenv bootargs root=/dev/ram rw " \ | |
399 | "console=$consoledev,$baudrate $othbootargs;" \ | |
400 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
401 | "tftp $loadaddr $bootfile;" \ | |
402 | "tftp $fdtaddr $fdtfile;" \ | |
403 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
404 | ||
405 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
406 | ||
407 | #endif /* __CONFIG_H */ |