| | 1 | /* |
| | 2 | * Copyright 2010-2012 Freescale Semiconductor, Inc. |
| | 3 | * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
| | 4 | * Timur Tabi <timur@freescale.com> |
| | 5 | * |
| | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| | 7 | */ |
| | 8 | |
| | 9 | #ifndef __CONFIG_H |
| | 10 | #define __CONFIG_H |
| | 11 | |
| | 12 | #include "../board/freescale/common/ics307_clk.h" |
| | 13 | |
| | 14 | #ifdef CONFIG_SDCARD |
| | 15 | #define CONFIG_SPL_MMC_MINIMAL |
| | 16 | #define CONFIG_SPL_FLUSH_IMAGE |
| | 17 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| | 18 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
| | 19 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| | 20 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| | 21 | #define CONFIG_SPL_PAD_TO 0x20000 |
| | 22 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) |
| | 23 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| | 24 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) |
| | 25 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) |
| | 26 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) |
| | 27 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| | 28 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| | 29 | #define CONFIG_SPL_MMC_BOOT |
| | 30 | #ifdef CONFIG_SPL_BUILD |
| | 31 | #define CONFIG_SPL_COMMON_INIT_DDR |
| | 32 | #endif |
| | 33 | #endif |
| | 34 | |
| | 35 | #ifdef CONFIG_SPIFLASH |
| | 36 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
| | 37 | #define CONFIG_SPL_FLUSH_IMAGE |
| | 38 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| | 39 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
| | 40 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| | 41 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| | 42 | #define CONFIG_SPL_PAD_TO 0x20000 |
| | 43 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) |
| | 44 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) |
| | 45 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) |
| | 46 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) |
| | 47 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) |
| | 48 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| | 49 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" |
| | 50 | #define CONFIG_SPL_SPI_BOOT |
| | 51 | #ifdef CONFIG_SPL_BUILD |
| | 52 | #define CONFIG_SPL_COMMON_INIT_DDR |
| | 53 | #endif |
| | 54 | #endif |
| | 55 | |
| | 56 | #define CONFIG_NAND_FSL_ELBC |
| | 57 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 |
| | 58 | #define CONFIG_SYS_NAND_MAX_OOBFREE 5 |
| | 59 | |
| | 60 | #ifdef CONFIG_NAND |
| | 61 | #ifdef CONFIG_TPL_BUILD |
| | 62 | #define CONFIG_SPL_NAND_BOOT |
| | 63 | #define CONFIG_SPL_FLUSH_IMAGE |
| | 64 | #define CONFIG_SPL_NAND_INIT |
| | 65 | #define CONFIG_SPL_COMMON_INIT_DDR |
| | 66 | #define CONFIG_SPL_MAX_SIZE (128 << 10) |
| | 67 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 |
| | 68 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| | 69 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) |
| | 70 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) |
| | 71 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) |
| | 72 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) |
| | 73 | #elif defined(CONFIG_SPL_BUILD) |
| | 74 | #define CONFIG_SPL_INIT_MINIMAL |
| | 75 | #define CONFIG_SPL_FLUSH_IMAGE |
| | 76 | #define CONFIG_SPL_TEXT_BASE 0xff800000 |
| | 77 | #define CONFIG_SPL_MAX_SIZE 4096 |
| | 78 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
| | 79 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 |
| | 80 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 |
| | 81 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) |
| | 82 | #endif |
| | 83 | #define CONFIG_SPL_PAD_TO 0x20000 |
| | 84 | #define CONFIG_TPL_PAD_TO 0x20000 |
| | 85 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
| | 86 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
| | 87 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" |
| | 88 | #endif |
| | 89 | |
| | 90 | /* High Level Configuration Options */ |
| | 91 | #define CONFIG_BOOKE /* BOOKE */ |
| | 92 | #define CONFIG_E500 /* BOOKE e500 family */ |
| | 93 | #define CONFIG_P1022 |
| | 94 | #define CONFIG_P1022DS |
| | 95 | #define CONFIG_MP /* support multiple processors */ |
| | 96 | |
| | 97 | #ifndef CONFIG_SYS_TEXT_BASE |
| | 98 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| | 99 | #endif |
| | 100 | |
| | 101 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| | 102 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| | 103 | #endif |
| | 104 | |
| | 105 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ |
| | 106 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
| | 107 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
| | 108 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ |
| | 109 | #define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ |
| | 110 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| | 111 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
| | 112 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| | 113 | |
| | 114 | #define CONFIG_ENABLE_36BIT_PHYS |
| | 115 | |
| | 116 | #ifdef CONFIG_PHYS_64BIT |
| | 117 | #define CONFIG_ADDR_MAP |
| | 118 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| | 119 | #endif |
| | 120 | |
| | 121 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
| | 122 | |
| | 123 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| | 124 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() |
| | 125 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| | 126 | |
| | 127 | /* |
| | 128 | * These can be toggled for performance analysis, otherwise use default. |
| | 129 | */ |
| | 130 | #define CONFIG_L2_CACHE |
| | 131 | #define CONFIG_BTB |
| | 132 | |
| | 133 | #define CONFIG_SYS_MEMTEST_START 0x00000000 |
| | 134 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff |
| | 135 | |
| | 136 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| | 137 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| | 138 | |
| | 139 | /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k |
| | 140 | SPL code*/ |
| | 141 | #ifdef CONFIG_SPL_BUILD |
| | 142 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| | 143 | #endif |
| | 144 | |
| | 145 | /* DDR Setup */ |
| | 146 | #define CONFIG_DDR_SPD |
| | 147 | #define CONFIG_VERY_BIG_RAM |
| | 148 | #define CONFIG_SYS_FSL_DDR3 |
| | 149 | |
| | 150 | #ifdef CONFIG_DDR_ECC |
| | 151 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| | 152 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| | 153 | #endif |
| | 154 | |
| | 155 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| | 156 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| | 157 | |
| | 158 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| | 159 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| | 160 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| | 161 | |
| | 162 | /* I2C addresses of SPD EEPROMs */ |
| | 163 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| | 164 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| | 165 | |
| | 166 | /* These are used when DDR doesn't use SPD. */ |
| | 167 | #define CONFIG_SYS_SDRAM_SIZE 2048 |
| | 168 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G |
| | 169 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| | 170 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| | 171 | #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F |
| | 172 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 |
| | 173 | #define CONFIG_SYS_DDR_TIMING_3 0x00010000 |
| | 174 | #define CONFIG_SYS_DDR_TIMING_0 0x40110104 |
| | 175 | #define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 |
| | 176 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca |
| | 177 | #define CONFIG_SYS_DDR_MODE_1 0x00441221 |
| | 178 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| | 179 | #define CONFIG_SYS_DDR_INTERVAL 0x0a280100 |
| | 180 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| | 181 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 |
| | 182 | #define CONFIG_SYS_DDR_CONTROL 0xc7000008 |
| | 183 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401041 |
| | 184 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| | 185 | #define CONFIG_SYS_DDR_TIMING_5 0x02401400 |
| | 186 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
| | 187 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 |
| | 188 | |
| | 189 | /* |
| | 190 | * Memory map |
| | 191 | * |
| | 192 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| | 193 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable |
| | 194 | * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable |
| | 195 | * |
| | 196 | * Localbus cacheable (TBD) |
| | 197 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| | 198 | * |
| | 199 | * Localbus non-cacheable |
| | 200 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| | 201 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| | 202 | * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable |
| | 203 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| | 204 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| | 205 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| | 206 | */ |
| | 207 | |
| | 208 | /* |
| | 209 | * Local Bus Definitions |
| | 210 | */ |
| | 211 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ |
| | 212 | #ifdef CONFIG_PHYS_64BIT |
| | 213 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull |
| | 214 | #else |
| | 215 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| | 216 | #endif |
| | 217 | |
| | 218 | #define CONFIG_FLASH_BR_PRELIM \ |
| | 219 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| | 220 | #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) |
| | 221 | |
| | 222 | #ifdef CONFIG_NAND |
| | 223 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| | 224 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| | 225 | #else |
| | 226 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| | 227 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| | 228 | #endif |
| | 229 | |
| | 230 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| | 231 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| | 232 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| | 233 | |
| | 234 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| | 235 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| | 236 | |
| | 237 | #ifndef CONFIG_SYS_MONITOR_BASE |
| | 238 | #ifdef CONFIG_SPL_BUILD |
| | 239 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| | 240 | #else |
| | 241 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| | 242 | #endif |
| | 243 | #endif |
| | 244 | |
| | 245 | #define CONFIG_FLASH_CFI_DRIVER |
| | 246 | #define CONFIG_SYS_FLASH_CFI |
| | 247 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| | 248 | |
| | 249 | /* Nand Flash */ |
| | 250 | #if defined(CONFIG_NAND_FSL_ELBC) |
| | 251 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| | 252 | #ifdef CONFIG_PHYS_64BIT |
| | 253 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
| | 254 | #else |
| | 255 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| | 256 | #endif |
| | 257 | |
| | 258 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
| | 259 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| | 260 | #define CONFIG_CMD_NAND 1 |
| | 261 | #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) |
| | 262 | #define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE |
| | 263 | |
| | 264 | /* NAND flash config */ |
| | 265 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| | 266 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| | 267 | | BR_PS_8 /* Port Size = 8 bit */ \ |
| | 268 | | BR_MS_FCM /* MSEL = FCM */ \ |
| | 269 | | BR_V) /* valid */ |
| | 270 | #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ |
| | 271 | | OR_FCM_PGS /* Large Page*/ \ |
| | 272 | | OR_FCM_CSCT \ |
| | 273 | | OR_FCM_CST \ |
| | 274 | | OR_FCM_CHT \ |
| | 275 | | OR_FCM_SCY_1 \ |
| | 276 | | OR_FCM_TRLX \ |
| | 277 | | OR_FCM_EHTR) |
| | 278 | #ifdef CONFIG_NAND |
| | 279 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| | 280 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 281 | #else |
| | 282 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| | 283 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
| | 284 | #endif |
| | 285 | |
| | 286 | #endif /* CONFIG_NAND_FSL_ELBC */ |
| | 287 | |
| | 288 | #define CONFIG_BOARD_EARLY_INIT_F |
| | 289 | #define CONFIG_BOARD_EARLY_INIT_R |
| | 290 | #define CONFIG_MISC_INIT_R |
| | 291 | #define CONFIG_HWCONFIG |
| | 292 | |
| | 293 | #define CONFIG_FSL_NGPIXIS |
| | 294 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| | 295 | #ifdef CONFIG_PHYS_64BIT |
| | 296 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| | 297 | #else |
| | 298 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| | 299 | #endif |
| | 300 | |
| | 301 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| | 302 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) |
| | 303 | |
| | 304 | #define PIXIS_LBMAP_SWITCH 7 |
| | 305 | #define PIXIS_LBMAP_MASK 0xF0 |
| | 306 | #define PIXIS_LBMAP_ALTBANK 0x20 |
| | 307 | #define PIXIS_SPD 0x07 |
| | 308 | #define PIXIS_SPD_SYSCLK_MASK 0x07 |
| | 309 | #define PIXIS_ELBC_SPI_MASK 0xc0 |
| | 310 | #define PIXIS_SPI 0x80 |
| | 311 | |
| | 312 | #define CONFIG_SYS_INIT_RAM_LOCK |
| | 313 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
| | 314 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| | 315 | |
| | 316 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| | 317 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| | 318 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| | 319 | |
| | 320 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| | 321 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| | 322 | |
| | 323 | /* |
| | 324 | * Config the L2 Cache as L2 SRAM |
| | 325 | */ |
| | 326 | #if defined(CONFIG_SPL_BUILD) |
| | 327 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) |
| | 328 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| | 329 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| | 330 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| | 331 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| | 332 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
| | 333 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) |
| | 334 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) |
| | 335 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) |
| | 336 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) |
| | 337 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) |
| | 338 | #elif defined(CONFIG_NAND) |
| | 339 | #ifdef CONFIG_TPL_BUILD |
| | 340 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| | 341 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| | 342 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| | 343 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| | 344 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 |
| | 345 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) |
| | 346 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) |
| | 347 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) |
| | 348 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) |
| | 349 | #else |
| | 350 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| | 351 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| | 352 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| | 353 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| | 354 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) |
| | 355 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) |
| | 356 | #endif |
| | 357 | #endif |
| | 358 | #endif |
| | 359 | |
| | 360 | /* |
| | 361 | * Serial Port |
| | 362 | */ |
| | 363 | #define CONFIG_CONS_INDEX 1 |
| | 364 | #define CONFIG_SYS_NS16550_SERIAL |
| | 365 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| | 366 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| | 367 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| | 368 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| | 369 | #endif |
| | 370 | |
| | 371 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| | 372 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| | 373 | |
| | 374 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| | 375 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| | 376 | |
| | 377 | /* Video */ |
| | 378 | |
| | 379 | #ifdef CONFIG_FSL_DIU_FB |
| | 380 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) |
| | 381 | #define CONFIG_CMD_BMP |
| | 382 | #define CONFIG_CFB_CONSOLE |
| | 383 | #define CONFIG_VIDEO_SW_CURSOR |
| | 384 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| | 385 | #define CONFIG_VIDEO_LOGO |
| | 386 | #define CONFIG_VIDEO_BMP_LOGO |
| | 387 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
| | 388 | /* |
| | 389 | * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so |
| | 390 | * disable empty flash sector detection, which is I/O-intensive. |
| | 391 | */ |
| | 392 | #undef CONFIG_SYS_FLASH_EMPTY_INFO |
| | 393 | #endif |
| | 394 | |
| | 395 | #ifndef CONFIG_FSL_DIU_FB |
| | 396 | #endif |
| | 397 | |
| | 398 | #ifdef CONFIG_ATI |
| | 399 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| | 400 | #define CONFIG_BIOSEMU |
| | 401 | #define CONFIG_VIDEO_SW_CURSOR |
| | 402 | #define CONFIG_ATI_RADEON_FB |
| | 403 | #define CONFIG_VIDEO_LOGO |
| | 404 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| | 405 | #define CONFIG_CFB_CONSOLE |
| | 406 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| | 407 | #endif |
| | 408 | |
| | 409 | /* I2C */ |
| | 410 | #define CONFIG_SYS_I2C |
| | 411 | #define CONFIG_SYS_I2C_FSL |
| | 412 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| | 413 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| | 414 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| | 415 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| | 416 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| | 417 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
| | 418 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} |
| | 419 | |
| | 420 | /* |
| | 421 | * I2C2 EEPROM |
| | 422 | */ |
| | 423 | #define CONFIG_ID_EEPROM |
| | 424 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| | 425 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| | 426 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| | 427 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 |
| | 428 | |
| | 429 | /* |
| | 430 | * eSPI - Enhanced SPI |
| | 431 | */ |
| | 432 | |
| | 433 | #define CONFIG_HARD_SPI |
| | 434 | |
| | 435 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| | 436 | #define CONFIG_SF_DEFAULT_MODE 0 |
| | 437 | |
| | 438 | /* |
| | 439 | * General PCI |
| | 440 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| | 441 | */ |
| | 442 | |
| | 443 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ |
| | 444 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| | 445 | #ifdef CONFIG_PHYS_64BIT |
| | 446 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| | 447 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| | 448 | #else |
| | 449 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| | 450 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| | 451 | #endif |
| | 452 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| | 453 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| | 454 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| | 455 | #ifdef CONFIG_PHYS_64BIT |
| | 456 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| | 457 | #else |
| | 458 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| | 459 | #endif |
| | 460 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| | 461 | |
| | 462 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
| | 463 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| | 464 | #ifdef CONFIG_PHYS_64BIT |
| | 465 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| | 466 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| | 467 | #else |
| | 468 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| | 469 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| | 470 | #endif |
| | 471 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| | 472 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| | 473 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| | 474 | #ifdef CONFIG_PHYS_64BIT |
| | 475 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| | 476 | #else |
| | 477 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| | 478 | #endif |
| | 479 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| | 480 | |
| | 481 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ |
| | 482 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| | 483 | #ifdef CONFIG_PHYS_64BIT |
| | 484 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| | 485 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| | 486 | #else |
| | 487 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| | 488 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| | 489 | #endif |
| | 490 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| | 491 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| | 492 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| | 493 | #ifdef CONFIG_PHYS_64BIT |
| | 494 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| | 495 | #else |
| | 496 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| | 497 | #endif |
| | 498 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| | 499 | |
| | 500 | #ifdef CONFIG_PCI |
| | 501 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| | 502 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| | 503 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| | 504 | #endif |
| | 505 | |
| | 506 | /* SATA */ |
| | 507 | #define CONFIG_LIBATA |
| | 508 | #define CONFIG_FSL_SATA |
| | 509 | #define CONFIG_FSL_SATA_V2 |
| | 510 | |
| | 511 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| | 512 | #define CONFIG_SATA1 |
| | 513 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| | 514 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| | 515 | #define CONFIG_SATA2 |
| | 516 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| | 517 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
| | 518 | |
| | 519 | #ifdef CONFIG_FSL_SATA |
| | 520 | #define CONFIG_LBA48 |
| | 521 | #define CONFIG_CMD_SATA |
| | 522 | #define CONFIG_DOS_PARTITION |
| | 523 | #endif |
| | 524 | |
| | 525 | #define CONFIG_MMC |
| | 526 | #ifdef CONFIG_MMC |
| | 527 | #define CONFIG_FSL_ESDHC |
| | 528 | #define CONFIG_GENERIC_MMC |
| | 529 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| | 530 | #endif |
| | 531 | |
| | 532 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) |
| | 533 | #define CONFIG_DOS_PARTITION |
| | 534 | #endif |
| | 535 | |
| | 536 | #define CONFIG_TSEC_ENET |
| | 537 | #ifdef CONFIG_TSEC_ENET |
| | 538 | |
| | 539 | #define CONFIG_TSECV2 |
| | 540 | |
| | 541 | #define CONFIG_MII /* MII PHY management */ |
| | 542 | #define CONFIG_TSEC1 1 |
| | 543 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| | 544 | #define CONFIG_TSEC2 1 |
| | 545 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| | 546 | |
| | 547 | #define TSEC1_PHY_ADDR 1 |
| | 548 | #define TSEC2_PHY_ADDR 2 |
| | 549 | |
| | 550 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 551 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| | 552 | |
| | 553 | #define TSEC1_PHYIDX 0 |
| | 554 | #define TSEC2_PHYIDX 0 |
| | 555 | |
| | 556 | #define CONFIG_ETHPRIME "eTSEC1" |
| | 557 | |
| | 558 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| | 559 | #endif |
| | 560 | |
| | 561 | /* |
| | 562 | * Dynamic MTD Partition support with mtdparts |
| | 563 | */ |
| | 564 | #define CONFIG_MTD_DEVICE |
| | 565 | #define CONFIG_MTD_PARTITIONS |
| | 566 | #define CONFIG_CMD_MTDPARTS |
| | 567 | #define CONFIG_FLASH_CFI_MTD |
| | 568 | #ifdef CONFIG_PHYS_64BIT |
| | 569 | #define MTDIDS_DEFAULT "nor0=fe8000000.nor" |
| | 570 | #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \ |
| | 571 | "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ |
| | 572 | "512k(dtb),768k(u-boot)" |
| | 573 | #else |
| | 574 | #define MTDIDS_DEFAULT "nor0=e8000000.nor" |
| | 575 | #define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \ |
| | 576 | "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \ |
| | 577 | "512k(dtb),768k(u-boot)" |
| | 578 | #endif |
| | 579 | |
| | 580 | /* |
| | 581 | * Environment |
| | 582 | */ |
| | 583 | #ifdef CONFIG_SPIFLASH |
| | 584 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| | 585 | #define CONFIG_ENV_SPI_BUS 0 |
| | 586 | #define CONFIG_ENV_SPI_CS 0 |
| | 587 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| | 588 | #define CONFIG_ENV_SPI_MODE 0 |
| | 589 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| | 590 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| | 591 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| | 592 | #elif defined(CONFIG_SDCARD) |
| | 593 | #define CONFIG_ENV_IS_IN_MMC |
| | 594 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| | 595 | #define CONFIG_ENV_SIZE 0x2000 |
| | 596 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| | 597 | #elif defined(CONFIG_NAND) |
| | 598 | #ifdef CONFIG_TPL_BUILD |
| | 599 | #define CONFIG_ENV_SIZE 0x2000 |
| | 600 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
| | 601 | #else |
| | 602 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| | 603 | #endif |
| | 604 | #define CONFIG_ENV_IS_IN_NAND |
| | 605 | #define CONFIG_ENV_OFFSET (1024 * 1024) |
| | 606 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
| | 607 | #elif defined(CONFIG_SYS_RAMBOOT) |
| | 608 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
| | 609 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| | 610 | #define CONFIG_ENV_SIZE 0x2000 |
| | 611 | #else |
| | 612 | #define CONFIG_ENV_IS_IN_FLASH |
| | 613 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| | 614 | #define CONFIG_ENV_SIZE 0x2000 |
| | 615 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| | 616 | #endif |
| | 617 | |
| | 618 | #define CONFIG_LOADS_ECHO |
| | 619 | #define CONFIG_SYS_LOADS_BAUD_CHANGE |
| | 620 | |
| | 621 | /* |
| | 622 | * Command line configuration. |
| | 623 | */ |
| | 624 | #define CONFIG_CMD_ERRATA |
| | 625 | #define CONFIG_CMD_IRQ |
| | 626 | #define CONFIG_CMD_REGINFO |
| | 627 | |
| | 628 | #ifdef CONFIG_PCI |
| | 629 | #define CONFIG_CMD_PCI |
| | 630 | #endif |
| | 631 | |
| | 632 | /* |
| | 633 | * USB |
| | 634 | */ |
| | 635 | #define CONFIG_HAS_FSL_DR_USB |
| | 636 | #ifdef CONFIG_HAS_FSL_DR_USB |
| | 637 | #define CONFIG_USB_EHCI |
| | 638 | |
| | 639 | #ifdef CONFIG_USB_EHCI |
| | 640 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| | 641 | #define CONFIG_USB_EHCI_FSL |
| | 642 | #endif |
| | 643 | #endif |
| | 644 | |
| | 645 | /* |
| | 646 | * Miscellaneous configurable options |
| | 647 | */ |
| | 648 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| | 649 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| | 650 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| | 651 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| | 652 | #ifdef CONFIG_CMD_KGDB |
| | 653 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| | 654 | #else |
| | 655 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| | 656 | #endif |
| | 657 | /* Print Buffer Size */ |
| | 658 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| | 659 | #define CONFIG_SYS_MAXARGS 16 |
| | 660 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| | 661 | |
| | 662 | /* |
| | 663 | * For booting Linux, the board info and command line data |
| | 664 | * have to be in the first 64 MB of memory, since this is |
| | 665 | * the maximum mapped by the Linux kernel during initialization. |
| | 666 | */ |
| | 667 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| | 668 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| | 669 | |
| | 670 | #ifdef CONFIG_CMD_KGDB |
| | 671 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| | 672 | #endif |
| | 673 | |
| | 674 | /* |
| | 675 | * Environment Configuration |
| | 676 | */ |
| | 677 | |
| | 678 | #define CONFIG_HOSTNAME p1022ds |
| | 679 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| | 680 | #define CONFIG_BOOTFILE "uImage" |
| | 681 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| | 682 | |
| | 683 | #define CONFIG_LOADADDR 1000000 |
| | 684 | |
| | 685 | |
| | 686 | #define CONFIG_BAUDRATE 115200 |
| | 687 | |
| | 688 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| | 689 | "netdev=eth0\0" \ |
| | 690 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| | 691 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| | 692 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| | 693 | "protect off $ubootaddr +$filesize && " \ |
| | 694 | "erase $ubootaddr +$filesize && " \ |
| | 695 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| | 696 | "protect on $ubootaddr +$filesize && " \ |
| | 697 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| | 698 | "consoledev=ttyS0\0" \ |
| | 699 | "ramdiskaddr=2000000\0" \ |
| | 700 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ |
| | 701 | "fdtaddr=1e00000\0" \ |
| | 702 | "fdtfile=p1022ds.dtb\0" \ |
| | 703 | "bdev=sda3\0" \ |
| | 704 | "hwconfig=esdhc;audclk:12\0" |
| | 705 | |
| | 706 | #define CONFIG_HDBOOT \ |
| | 707 | "setenv bootargs root=/dev/$bdev rw " \ |
| | 708 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| | 709 | "tftp $loadaddr $bootfile;" \ |
| | 710 | "tftp $fdtaddr $fdtfile;" \ |
| | 711 | "bootm $loadaddr - $fdtaddr" |
| | 712 | |
| | 713 | #define CONFIG_NFSBOOTCOMMAND \ |
| | 714 | "setenv bootargs root=/dev/nfs rw " \ |
| | 715 | "nfsroot=$serverip:$rootpath " \ |
| | 716 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| | 717 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| | 718 | "tftp $loadaddr $bootfile;" \ |
| | 719 | "tftp $fdtaddr $fdtfile;" \ |
| | 720 | "bootm $loadaddr - $fdtaddr" |
| | 721 | |
| | 722 | #define CONFIG_RAMBOOTCOMMAND \ |
| | 723 | "setenv bootargs root=/dev/ram rw " \ |
| | 724 | "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ |
| | 725 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| | 726 | "tftp $loadaddr $bootfile;" \ |
| | 727 | "tftp $fdtaddr $fdtfile;" \ |
| | 728 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| | 729 | |
| | 730 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND |
| | 731 | |
| | 732 | #endif |
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