| | 1 | /* |
| | 2 | * Configuation settings for the esd TASREG board. |
| | 3 | * |
| | 4 | * (C) Copyright 2004 |
| | 5 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| | 6 | * |
| | 7 | * See file CREDITS for list of people who contributed to this |
| | 8 | * project. |
| | 9 | * |
| | 10 | * This program is free software; you can redistribute it and/or |
| | 11 | * modify it under the terms of the GNU General Public License as |
| | 12 | * published by the Free Software Foundation; either version 2 of |
| | 13 | * the License, or (at your option) any later version. |
| | 14 | * |
| | 15 | * This program is distributed in the hope that it will be useful, |
| | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 18 | * GNU General Public License for more details. |
| | 19 | * |
| | 20 | * You should have received a copy of the GNU General Public License |
| | 21 | * along with this program; if not, write to the Free Software |
| | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| | 23 | * MA 02111-1307 USA |
| | 24 | */ |
| | 25 | |
| | 26 | /* |
| | 27 | * board/config.h - configuration options, board specific |
| | 28 | */ |
| | 29 | |
| | 30 | #ifndef _TASREG_H |
| | 31 | #define _TASREG_H |
| | 32 | |
| | 33 | #ifndef __ASSEMBLY__ |
| | 34 | #include <asm/m5249.h> |
| | 35 | #endif |
| | 36 | |
| | 37 | /* |
| | 38 | * High Level Configuration Options |
| | 39 | * (easy to change) |
| | 40 | */ |
| | 41 | #define CONFIG_MCF52x2 /* define processor family */ |
| | 42 | #define CONFIG_M5249 /* define processor type */ |
| | 43 | |
| | 44 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
| | 45 | |
| | 46 | #define CONFIG_MCFTMR |
| | 47 | |
| | 48 | #define CONFIG_MCFUART |
| | 49 | #define CONFIG_SYS_UART_PORT (0) |
| | 50 | #define CONFIG_BAUDRATE 19200 |
| | 51 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
| | 52 | |
| | 53 | #undef CONFIG_WATCHDOG |
| | 54 | |
| | 55 | #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ |
| | 56 | |
| | 57 | |
| | 58 | /* |
| | 59 | * BOOTP options |
| | 60 | */ |
| | 61 | #define CONFIG_BOOTP_BOOTFILESIZE |
| | 62 | #define CONFIG_BOOTP_BOOTPATH |
| | 63 | #define CONFIG_BOOTP_GATEWAY |
| | 64 | #define CONFIG_BOOTP_HOSTNAME |
| | 65 | |
| | 66 | |
| | 67 | /* |
| | 68 | * Command line configuration. |
| | 69 | */ |
| | 70 | #include <config_cmd_default.h> |
| | 71 | |
| | 72 | #define CONFIG_CMD_BSP |
| | 73 | #define CONFIG_CMD_EEPROM |
| | 74 | #define CONFIG_CMD_I2C |
| | 75 | |
| | 76 | #undef CONFIG_CMD_NET |
| | 77 | |
| | 78 | |
| | 79 | #define CONFIG_BOOTDELAY 3 |
| | 80 | |
| | 81 | #define CONFIG_SYS_PROMPT "=> " |
| | 82 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| | 83 | |
| | 84 | #if defined(CONFIG_CMD_KGDB) |
| | 85 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| | 86 | #else |
| | 87 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| | 88 | #endif |
| | 89 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| | 90 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| | 91 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| | 92 | |
| | 93 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
| | 94 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
| | 95 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| | 96 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| | 97 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
| | 98 | |
| | 99 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
| | 100 | |
| | 101 | #define CONFIG_SYS_MEMTEST_START 0x400 |
| | 102 | #define CONFIG_SYS_MEMTEST_END 0x380000 |
| | 103 | |
| | 104 | #define CONFIG_SYS_HZ 1000 |
| | 105 | |
| | 106 | /* |
| | 107 | * Clock configuration: enable only one of the following options |
| | 108 | */ |
| | 109 | |
| | 110 | #if 0 /* this setting will run the cpu at 11MHz */ |
| | 111 | #define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */ |
| | 112 | #undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ |
| | 113 | #define CONFIG_SYS_CLK 11289600 /* PLL bypass */ |
| | 114 | #endif |
| | 115 | |
| | 116 | #if 0 /* this setting will run the cpu at 70MHz */ |
| | 117 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
| | 118 | #undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */ |
| | 119 | #define CONFIG_SYS_CLK 72185018 /* The next lower speed */ |
| | 120 | #endif |
| | 121 | |
| | 122 | #if 1 /* this setting will run the cpu at 140MHz */ |
| | 123 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
| | 124 | #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ |
| | 125 | #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ |
| | 126 | #endif |
| | 127 | |
| | 128 | /* |
| | 129 | * Low Level Configuration Settings |
| | 130 | * (address mappings, register initial values, etc.) |
| | 131 | * You should know what you are doing if you make changes here. |
| | 132 | */ |
| | 133 | |
| | 134 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
| | 135 | #define CONFIG_SYS_MBAR2 0x80000000 |
| | 136 | |
| | 137 | /*----------------------------------------------------------------------- |
| | 138 | * I2C |
| | 139 | */ |
| | 140 | #define CONFIG_SOFT_I2C |
| | 141 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
| | 142 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| | 143 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ |
| | 144 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
| | 145 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
| | 146 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 |
| | 147 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ |
| | 148 | /* 32 byte page write mode using*/ |
| | 149 | /* last 5 bits of the address */ |
| | 150 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
| | 151 | |
| | 152 | #if defined (CONFIG_SOFT_I2C) |
| | 153 | #if 0 /* push-pull */ |
| | 154 | #define SDA 0x00800000 |
| | 155 | #define SCL 0x00000008 |
| | 156 | #define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) |
| | 157 | #define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) |
| | 158 | #define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) |
| | 159 | #define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) |
| | 160 | #define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) |
| | 161 | #define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) |
| | 162 | #define I2C_INIT {OUT1|=SDA;OUT0|=SCL;} |
| | 163 | #define I2C_READ ((IN1&SDA)?1:0) |
| | 164 | #define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;} |
| | 165 | #define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;} |
| | 166 | #define I2C_DELAY {udelay(5);} |
| | 167 | #define I2C_ACTIVE {DIR1|=SDA;} |
| | 168 | #define I2C_TRISTATE {DIR1&=~SDA;} |
| | 169 | #else /* open-collector */ |
| | 170 | #define SDA 0x00800000 |
| | 171 | #define SCL 0x00000008 |
| | 172 | #define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN)) |
| | 173 | #define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN)) |
| | 174 | #define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT)) |
| | 175 | #define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT)) |
| | 176 | #define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ)) |
| | 177 | #define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ)) |
| | 178 | #define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;} |
| | 179 | #define I2C_READ ((IN1&SDA)?1:0) |
| | 180 | #define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;} |
| | 181 | #define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;} |
| | 182 | #define I2C_DELAY {udelay(5);} |
| | 183 | #define I2C_ACTIVE {DIR1|=SDA;} |
| | 184 | #define I2C_TRISTATE {DIR1&=~SDA;} |
| | 185 | #endif |
| | 186 | #endif |
| | 187 | |
| | 188 | /*----------------------------------------------------------------------- |
| | 189 | * Definitions for initial stack pointer and data area (in DPRAM) |
| | 190 | */ |
| | 191 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
| | 192 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ |
| | 193 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
| | 194 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| | 195 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| | 196 | |
| | 197 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| | 198 | #define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/ |
| | 199 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
| | 200 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ |
| | 201 | |
| | 202 | /*----------------------------------------------------------------------- |
| | 203 | * Start addresses for the final memory configuration |
| | 204 | * (Set up by the startup code) |
| | 205 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| | 206 | */ |
| | 207 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| | 208 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
| | 209 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 |
| | 210 | |
| | 211 | #if 0 /* test-only */ |
| | 212 | #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ |
| | 213 | #endif |
| | 214 | |
| | 215 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| | 216 | |
| | 217 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
| | 218 | #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ |
| | 219 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
| | 220 | |
| | 221 | /* |
| | 222 | * For booting Linux, the board info and command line data |
| | 223 | * have to be in the first 8 MB of memory, since this is |
| | 224 | * the maximum mapped by the Linux kernel during initialization ?? |
| | 225 | */ |
| | 226 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| | 227 | |
| | 228 | /*----------------------------------------------------------------------- |
| | 229 | * FLASH organization |
| | 230 | */ |
| | 231 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| | 232 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
| | 233 | |
| | 234 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| | 235 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| | 236 | |
| | 237 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| | 238 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| | 239 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
| | 240 | /* |
| | 241 | * The following defines are added for buggy IOP480 byte interface. |
| | 242 | * All other boards should use the standard values (CPCI405 etc.) |
| | 243 | */ |
| | 244 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
| | 245 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
| | 246 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
| | 247 | |
| | 248 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| | 249 | |
| | 250 | /*----------------------------------------------------------------------- |
| | 251 | * Cache Configuration |
| | 252 | */ |
| | 253 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
| | 254 | |
| | 255 | /*----------------------------------------------------------------------- |
| | 256 | * Memory bank definitions |
| | 257 | */ |
| | 258 | |
| | 259 | /* CS0 - AMD Flash, address 0xffc00000 */ |
| | 260 | #define CONFIG_SYS_CSAR0 0xffc0 |
| | 261 | #define CONFIG_SYS_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ |
| | 262 | /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
| | 263 | #define CONFIG_SYS_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
| | 264 | |
| | 265 | /* CS1 - FPGA, address 0xe0000000 */ |
| | 266 | #define CONFIG_SYS_CSAR1 0xe000 |
| | 267 | #define CONFIG_SYS_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ |
| | 268 | #define CONFIG_SYS_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ |
| | 269 | |
| | 270 | /*----------------------------------------------------------------------- |
| | 271 | * Port configuration |
| | 272 | */ |
| | 273 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
| | 274 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ |
| | 275 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ |
| | 276 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ |
| | 277 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ |
| | 278 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ |
| | 279 | |
| | 280 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ |
| | 281 | |
| | 282 | /*----------------------------------------------------------------------- |
| | 283 | * FPGA stuff |
| | 284 | */ |
| | 285 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
| | 286 | #define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/ |
| | 287 | |
| | 288 | /* FPGA program pin configuration */ |
| | 289 | #define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */ |
| | 290 | #define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */ |
| | 291 | #define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */ |
| | 292 | #define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */ |
| | 293 | #define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */ |
| | 294 | |
| | 295 | #endif /* _TASREG_H */ |
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