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1 | /* | |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ | |
37 | #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ | |
38 | ||
39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
40 | #undef CONFIG_8xx_CONS_SMC2 | |
41 | #undef CONFIG_8xx_CONS_NONE | |
42 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
43 | ||
44 | #define CONFIG_BOOTCOUNT_LIMIT | |
45 | ||
46 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
47 | ||
48 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
49 | ||
50 | #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" | |
51 | ||
52 | #undef CONFIG_BOOTARGS | |
53 | ||
54 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
55 | "netdev=eth0\0" \ | |
56 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
57 | "nfsroot=${serverip}:${rootpath}\0" \ | |
58 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
59 | "addip=setenv bootargs ${bootargs} " \ | |
60 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
61 | ":${hostname}:${netdev}:off panic=1\0" \ | |
62 | "flash_nfs=run nfsargs addip;" \ | |
63 | "bootm ${kernel_addr}\0" \ | |
64 | "flash_self=run ramargs addip;" \ | |
65 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
66 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
67 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
68 | "bootfile=/tftpboot/TQM850L/uImage\0" \ | |
69 | "fdt_addr=40040000\0" \ | |
70 | "kernel_addr=40060000\0" \ | |
71 | "ramdisk_addr=40200000\0" \ | |
72 | "" | |
73 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
74 | ||
75 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
76 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
77 | ||
78 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
79 | ||
80 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
81 | ||
82 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
83 | ||
84 | /* | |
85 | * BOOTP options | |
86 | */ | |
87 | #define CONFIG_BOOTP_SUBNETMASK | |
88 | #define CONFIG_BOOTP_GATEWAY | |
89 | #define CONFIG_BOOTP_HOSTNAME | |
90 | #define CONFIG_BOOTP_BOOTPATH | |
91 | #define CONFIG_BOOTP_BOOTFILESIZE | |
92 | ||
93 | ||
94 | #define CONFIG_MAC_PARTITION | |
95 | #define CONFIG_DOS_PARTITION | |
96 | ||
97 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
98 | ||
99 | /* | |
100 | * Command line configuration. | |
101 | */ | |
102 | #include <config_cmd_default.h> | |
103 | ||
104 | #define CONFIG_CMD_ASKENV | |
105 | #define CONFIG_CMD_DATE | |
106 | #define CONFIG_CMD_DHCP | |
107 | #define CONFIG_CMD_IDE | |
108 | #define CONFIG_CMD_NFS | |
109 | #define CONFIG_CMD_SNTP | |
110 | ||
111 | ||
112 | /* | |
113 | * Miscellaneous configurable options | |
114 | */ | |
115 | #define CFG_LONGHELP /* undef to save memory */ | |
116 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
117 | ||
118 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
119 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
120 | #ifdef CFG_HUSH_PARSER | |
121 | #define CFG_PROMPT_HUSH_PS2 "> " | |
122 | #endif | |
123 | ||
124 | #if defined(CONFIG_CMD_KGDB) | |
125 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
126 | #else | |
127 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
128 | #endif | |
129 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
130 | #define CFG_MAXARGS 16 /* max number of command args */ | |
131 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
132 | ||
133 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
134 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
135 | ||
136 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
137 | ||
138 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
139 | ||
140 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
141 | ||
142 | /* | |
143 | * Low Level Configuration Settings | |
144 | * (address mappings, register initial values, etc.) | |
145 | * You should know what you are doing if you make changes here. | |
146 | */ | |
147 | /*----------------------------------------------------------------------- | |
148 | * Internal Memory Mapped Register | |
149 | */ | |
150 | #define CFG_IMMR 0xFFF00000 | |
151 | ||
152 | /*----------------------------------------------------------------------- | |
153 | * Definitions for initial stack pointer and data area (in DPRAM) | |
154 | */ | |
155 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
156 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
157 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
158 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
159 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
160 | ||
161 | /*----------------------------------------------------------------------- | |
162 | * Start addresses for the final memory configuration | |
163 | * (Set up by the startup code) | |
164 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
165 | */ | |
166 | #define CFG_SDRAM_BASE 0x00000000 | |
167 | #define CFG_FLASH_BASE 0x40000000 | |
168 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
169 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
170 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
171 | ||
172 | /* | |
173 | * For booting Linux, the board info and command line data | |
174 | * have to be in the first 8 MB of memory, since this is | |
175 | * the maximum mapped by the Linux kernel during initialization. | |
176 | */ | |
177 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
178 | ||
179 | /*----------------------------------------------------------------------- | |
180 | * FLASH organization | |
181 | */ | |
182 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
183 | #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
184 | ||
185 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
186 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
187 | ||
188 | #define CFG_ENV_IS_IN_FLASH 1 | |
189 | #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ | |
190 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
191 | ||
192 | /* Address and size of Redundant Environment Sector */ | |
193 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) | |
194 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
195 | ||
196 | #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ | |
197 | ||
198 | /*----------------------------------------------------------------------- | |
199 | * Hardware Information Block | |
200 | */ | |
201 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
202 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
203 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * Cache Configuration | |
207 | */ | |
208 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
209 | #if defined(CONFIG_CMD_KGDB) | |
210 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
211 | #endif | |
212 | ||
213 | /*----------------------------------------------------------------------- | |
214 | * SYPCR - System Protection Control 11-9 | |
215 | * SYPCR can only be written once after reset! | |
216 | *----------------------------------------------------------------------- | |
217 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
218 | */ | |
219 | #if defined(CONFIG_WATCHDOG) | |
220 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
221 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
222 | #else | |
223 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
224 | #endif | |
225 | ||
226 | /*----------------------------------------------------------------------- | |
227 | * SIUMCR - SIU Module Configuration 11-6 | |
228 | *----------------------------------------------------------------------- | |
229 | * PCMCIA config., multi-function pin tri-state | |
230 | */ | |
231 | #ifndef CONFIG_CAN_DRIVER | |
232 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
233 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
234 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
235 | #endif /* CONFIG_CAN_DRIVER */ | |
236 | ||
237 | /*----------------------------------------------------------------------- | |
238 | * TBSCR - Time Base Status and Control 11-26 | |
239 | *----------------------------------------------------------------------- | |
240 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
241 | */ | |
242 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
246 | *----------------------------------------------------------------------- | |
247 | */ | |
248 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
249 | ||
250 | /*----------------------------------------------------------------------- | |
251 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
252 | *----------------------------------------------------------------------- | |
253 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
254 | */ | |
255 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
256 | ||
257 | /*----------------------------------------------------------------------- | |
258 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
259 | *----------------------------------------------------------------------- | |
260 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
261 | * interrupt status bit | |
262 | */ | |
263 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
264 | ||
265 | /*----------------------------------------------------------------------- | |
266 | * SCCR - System Clock and reset Control Register 15-27 | |
267 | *----------------------------------------------------------------------- | |
268 | * Set clock output, timebase and RTC source and divider, | |
269 | * power management and some other internal clocks | |
270 | */ | |
271 | #define SCCR_MASK SCCR_EBDF11 | |
272 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
273 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
274 | SCCR_DFALCD00) | |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * PCMCIA stuff | |
278 | *----------------------------------------------------------------------- | |
279 | * | |
280 | */ | |
281 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
282 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
283 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
284 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
285 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
286 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
287 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
288 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
289 | ||
290 | /*----------------------------------------------------------------------- | |
291 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
292 | *----------------------------------------------------------------------- | |
293 | */ | |
294 | ||
295 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
296 | ||
297 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
298 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
299 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
300 | ||
301 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
302 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
303 | ||
304 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
305 | ||
306 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
307 | ||
308 | /* Offset for data I/O */ | |
309 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
310 | ||
311 | /* Offset for normal register accesses */ | |
312 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
313 | ||
314 | /* Offset for alternate registers */ | |
315 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
316 | ||
317 | /*----------------------------------------------------------------------- | |
318 | * | |
319 | *----------------------------------------------------------------------- | |
320 | * | |
321 | */ | |
322 | #define CFG_DER 0 | |
323 | ||
324 | /* | |
325 | * Init Memory Controller: | |
326 | * | |
327 | * BR0/1 and OR0/1 (FLASH) | |
328 | */ | |
329 | ||
330 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
331 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
332 | ||
333 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
334 | * restrict access enough to keep SRAM working (if any) | |
335 | * but not too much to meddle with FLASH accesses | |
336 | */ | |
337 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
338 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
339 | ||
340 | /* | |
341 | * FLASH timing: | |
342 | */ | |
343 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
344 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
345 | ||
346 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
347 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
348 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
349 | ||
350 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
351 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
352 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
353 | ||
354 | /* | |
355 | * BR2/3 and OR2/3 (SDRAM) | |
356 | * | |
357 | */ | |
358 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
359 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
360 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
361 | ||
362 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
363 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
364 | ||
365 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
366 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
367 | ||
368 | #ifndef CONFIG_CAN_DRIVER | |
369 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
370 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
371 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
372 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
373 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
374 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
375 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
376 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
377 | #endif /* CONFIG_CAN_DRIVER */ | |
378 | ||
379 | /* | |
380 | * Memory Periodic Timer Prescaler | |
381 | * | |
382 | * The Divider for PTA (refresh timer) configuration is based on an | |
383 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
384 | * the number of chip selects (NCS) and the actually needed refresh | |
385 | * rate is done by setting MPTPR. | |
386 | * | |
387 | * PTA is calculated from | |
388 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
389 | * | |
390 | * gclk CPU clock (not bus clock!) | |
391 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
392 | * | |
393 | * 4096 Rows from SDRAM example configuration | |
394 | * 1000 factor s -> ms | |
395 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
396 | * 4 Number of refresh cycles per period | |
397 | * 64 Refresh cycle in ms per number of rows | |
398 | * -------------------------------------------- | |
399 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
400 | * | |
401 | * 50 MHz => 50.000.000 / Divider = 98 | |
402 | * 66 Mhz => 66.000.000 / Divider = 129 | |
403 | * 80 Mhz => 80.000.000 / Divider = 156 | |
404 | */ | |
405 | ||
406 | #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) | |
407 | #define CFG_MAMR_PTA 98 | |
408 | ||
409 | /* | |
410 | * For 16 MBit, refresh rates could be 31.3 us | |
411 | * (= 64 ms / 2K = 125 / quad bursts). | |
412 | * For a simpler initialization, 15.6 us is used instead. | |
413 | * | |
414 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
415 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
416 | */ | |
417 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
418 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
419 | ||
420 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
421 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
422 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
423 | ||
424 | /* | |
425 | * MAMR settings for SDRAM | |
426 | */ | |
427 | ||
428 | /* 8 column SDRAM */ | |
429 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
430 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
431 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
432 | /* 9 column SDRAM */ | |
433 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
434 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
435 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
436 | ||
437 | ||
438 | /* | |
439 | * Internal Definitions | |
440 | * | |
441 | * Boot Flags | |
442 | */ | |
443 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
444 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
445 | ||
446 | #endif /* __CONFIG_H */ |