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1 | /* | |
2 | * (C) Copyright 2000-2008 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ | |
37 | #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ | |
38 | ||
39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
40 | #undef CONFIG_8xx_CONS_SMC2 | |
41 | #undef CONFIG_8xx_CONS_NONE | |
42 | ||
43 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
44 | ||
45 | #define CONFIG_BOOTCOUNT_LIMIT | |
46 | ||
47 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
48 | ||
49 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
50 | ||
51 | #define CONFIG_PREBOOT "echo;" \ | |
52 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
53 | "echo" | |
54 | ||
55 | #undef CONFIG_BOOTARGS | |
56 | ||
57 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
58 | "netdev=eth0\0" \ | |
59 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
60 | "nfsroot=${serverip}:${rootpath}\0" \ | |
61 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
62 | "addip=setenv bootargs ${bootargs} " \ | |
63 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
64 | ":${hostname}:${netdev}:off panic=1\0" \ | |
65 | "flash_nfs=run nfsargs addip;" \ | |
66 | "bootm ${kernel_addr}\0" \ | |
67 | "flash_self=run ramargs addip;" \ | |
68 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
69 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
70 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
71 | "hostname=TQM855M\0" \ | |
72 | "bootfile=TQM855M/uImage\0" \ | |
73 | "fdt_addr=40080000\0" \ | |
74 | "kernel_addr=400A0000\0" \ | |
75 | "ramdisk_addr=40280000\0" \ | |
76 | "u-boot=TQM855M/u-image.bin\0" \ | |
77 | "load=tftp 200000 ${u-boot}\0" \ | |
78 | "update=prot off 40000000 +${filesize};" \ | |
79 | "era 40000000 +${filesize};" \ | |
80 | "cp.b 200000 40000000 ${filesize};" \ | |
81 | "sete filesize;save\0" \ | |
82 | "" | |
83 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
84 | ||
85 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
86 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
87 | ||
88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
89 | ||
90 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
91 | ||
92 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
93 | ||
94 | /* enable I2C and select the hardware/software driver */ | |
95 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
96 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
97 | ||
98 | #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ | |
99 | #define CFG_I2C_SLAVE 0xFE | |
100 | ||
101 | #ifdef CONFIG_SOFT_I2C | |
102 | /* | |
103 | * Software (bit-bang) I2C driver configuration | |
104 | */ | |
105 | #define PB_SCL 0x00000020 /* PB 26 */ | |
106 | #define PB_SDA 0x00000010 /* PB 27 */ | |
107 | ||
108 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
109 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
110 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
111 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
112 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
113 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
114 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
115 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
116 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
117 | #endif /* CONFIG_SOFT_I2C */ | |
118 | ||
119 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ | |
120 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
121 | #if 0 | |
122 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ | |
123 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
124 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 | |
125 | #endif | |
126 | ||
127 | /* | |
128 | * BOOTP options | |
129 | */ | |
130 | #define CONFIG_BOOTP_SUBNETMASK | |
131 | #define CONFIG_BOOTP_GATEWAY | |
132 | #define CONFIG_BOOTP_HOSTNAME | |
133 | #define CONFIG_BOOTP_BOOTPATH | |
134 | #define CONFIG_BOOTP_BOOTFILESIZE | |
135 | ||
136 | ||
137 | #define CONFIG_MAC_PARTITION | |
138 | #define CONFIG_DOS_PARTITION | |
139 | ||
140 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
141 | ||
142 | ||
143 | /* | |
144 | * Command line configuration. | |
145 | */ | |
146 | #include <config_cmd_default.h> | |
147 | ||
148 | #define CONFIG_CMD_ASKENV | |
149 | #define CONFIG_CMD_DATE | |
150 | #define CONFIG_CMD_DHCP | |
151 | #define CONFIG_CMD_ELF | |
152 | #define CONFIG_CMD_EEPROM | |
153 | #define CONFIG_CMD_IDE | |
154 | #define CONFIG_CMD_JFFS2 | |
155 | #define CONFIG_CMD_NFS | |
156 | #define CONFIG_CMD_SNTP | |
157 | ||
158 | ||
159 | #define CONFIG_NETCONSOLE | |
160 | ||
161 | ||
162 | /* | |
163 | * Miscellaneous configurable options | |
164 | */ | |
165 | #define CFG_LONGHELP /* undef to save memory */ | |
166 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
167 | ||
168 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
169 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
170 | #ifdef CFG_HUSH_PARSER | |
171 | #define CFG_PROMPT_HUSH_PS2 "> " | |
172 | #endif | |
173 | ||
174 | #if defined(CONFIG_CMD_KGDB) | |
175 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
176 | #else | |
177 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
178 | #endif | |
179 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
180 | #define CFG_MAXARGS 16 /* max number of command args */ | |
181 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
182 | ||
183 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
184 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
185 | ||
186 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
187 | ||
188 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
189 | ||
190 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
191 | ||
192 | /* | |
193 | * Low Level Configuration Settings | |
194 | * (address mappings, register initial values, etc.) | |
195 | * You should know what you are doing if you make changes here. | |
196 | */ | |
197 | /*----------------------------------------------------------------------- | |
198 | * Internal Memory Mapped Register | |
199 | */ | |
200 | #define CFG_IMMR 0xFFF00000 | |
201 | ||
202 | /*----------------------------------------------------------------------- | |
203 | * Definitions for initial stack pointer and data area (in DPRAM) | |
204 | */ | |
205 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
206 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
207 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
208 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
209 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * Start addresses for the final memory configuration | |
213 | * (Set up by the startup code) | |
214 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
215 | */ | |
216 | #define CFG_SDRAM_BASE 0x00000000 | |
217 | #define CFG_FLASH_BASE 0x40000000 | |
218 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
219 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
220 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
221 | ||
222 | /* | |
223 | * For booting Linux, the board info and command line data | |
224 | * have to be in the first 8 MB of memory, since this is | |
225 | * the maximum mapped by the Linux kernel during initialization. | |
226 | */ | |
227 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
228 | ||
229 | /*----------------------------------------------------------------------- | |
230 | * FLASH organization | |
231 | */ | |
232 | ||
233 | /* use CFI flash driver */ | |
234 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
235 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
236 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
237 | #define CFG_FLASH_EMPTY_INFO | |
238 | #define CFG_FLASH_USE_BUFFER_WRITE 1 | |
239 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
240 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
241 | ||
242 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
243 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
244 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
245 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ | |
246 | ||
247 | /* Address and size of Redundant Environment Sector */ | |
248 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) | |
249 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
250 | ||
251 | #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ | |
252 | ||
253 | /*----------------------------------------------------------------------- | |
254 | * Dynamic MTD partition support | |
255 | */ | |
256 | #define CONFIG_JFFS2_CMDLINE | |
257 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" | |
258 | ||
259 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
260 | "128k(dtb)," \ | |
261 | "1920k(kernel)," \ | |
262 | "5632(rootfs)," \ | |
263 | "4m(data)" | |
264 | ||
265 | /*----------------------------------------------------------------------- | |
266 | * Hardware Information Block | |
267 | */ | |
268 | #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
269 | #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
270 | #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
271 | ||
272 | /*----------------------------------------------------------------------- | |
273 | * Cache Configuration | |
274 | */ | |
275 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
276 | #if defined(CONFIG_CMD_KGDB) | |
277 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
278 | #endif | |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * SYPCR - System Protection Control 11-9 | |
282 | * SYPCR can only be written once after reset! | |
283 | *----------------------------------------------------------------------- | |
284 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
285 | */ | |
286 | #if defined(CONFIG_WATCHDOG) | |
287 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
288 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
289 | #else | |
290 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
291 | #endif | |
292 | ||
293 | /*----------------------------------------------------------------------- | |
294 | * SIUMCR - SIU Module Configuration 11-6 | |
295 | *----------------------------------------------------------------------- | |
296 | * PCMCIA config., multi-function pin tri-state | |
297 | */ | |
298 | #ifndef CONFIG_CAN_DRIVER | |
299 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
300 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
301 | #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
302 | #endif /* CONFIG_CAN_DRIVER */ | |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * TBSCR - Time Base Status and Control 11-26 | |
306 | *----------------------------------------------------------------------- | |
307 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
308 | */ | |
309 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
310 | ||
311 | /*----------------------------------------------------------------------- | |
312 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
313 | *----------------------------------------------------------------------- | |
314 | */ | |
315 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
316 | ||
317 | /*----------------------------------------------------------------------- | |
318 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
319 | *----------------------------------------------------------------------- | |
320 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
321 | */ | |
322 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
323 | ||
324 | /*----------------------------------------------------------------------- | |
325 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
326 | *----------------------------------------------------------------------- | |
327 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
328 | * interrupt status bit | |
329 | */ | |
330 | #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
331 | ||
332 | /*----------------------------------------------------------------------- | |
333 | * SCCR - System Clock and reset Control Register 15-27 | |
334 | *----------------------------------------------------------------------- | |
335 | * Set clock output, timebase and RTC source and divider, | |
336 | * power management and some other internal clocks | |
337 | */ | |
338 | #define SCCR_MASK SCCR_EBDF11 | |
339 | #define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
340 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
341 | SCCR_DFALCD00) | |
342 | ||
343 | /*----------------------------------------------------------------------- | |
344 | * PCMCIA stuff | |
345 | *----------------------------------------------------------------------- | |
346 | * | |
347 | */ | |
348 | #define CFG_PCMCIA_MEM_ADDR (0xE0000000) | |
349 | #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
350 | #define CFG_PCMCIA_DMA_ADDR (0xE4000000) | |
351 | #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
352 | #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) | |
353 | #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
354 | #define CFG_PCMCIA_IO_ADDR (0xEC000000) | |
355 | #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) | |
356 | ||
357 | /*----------------------------------------------------------------------- | |
358 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
359 | *----------------------------------------------------------------------- | |
360 | */ | |
361 | ||
362 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
363 | ||
364 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
365 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
366 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
367 | ||
368 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
369 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
370 | ||
371 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
372 | ||
373 | #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR | |
374 | ||
375 | /* Offset for data I/O */ | |
376 | #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) | |
377 | ||
378 | /* Offset for normal register accesses */ | |
379 | #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) | |
380 | ||
381 | /* Offset for alternate registers */ | |
382 | #define CFG_ATA_ALT_OFFSET 0x0100 | |
383 | ||
384 | /*----------------------------------------------------------------------- | |
385 | * | |
386 | *----------------------------------------------------------------------- | |
387 | * | |
388 | */ | |
389 | #define CFG_DER 0 | |
390 | ||
391 | /* | |
392 | * Init Memory Controller: | |
393 | * | |
394 | * BR0/1 and OR0/1 (FLASH) | |
395 | */ | |
396 | ||
397 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
398 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
399 | ||
400 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
401 | * restrict access enough to keep SRAM working (if any) | |
402 | * but not too much to meddle with FLASH accesses | |
403 | */ | |
404 | #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
405 | #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
406 | ||
407 | /* | |
408 | * FLASH timing: | |
409 | */ | |
410 | #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
411 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
412 | ||
413 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
414 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
415 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
416 | ||
417 | #define CFG_OR1_REMAP CFG_OR0_REMAP | |
418 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
419 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
420 | ||
421 | /* | |
422 | * BR2/3 and OR2/3 (SDRAM) | |
423 | * | |
424 | */ | |
425 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
426 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
427 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
428 | ||
429 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
430 | #define CFG_OR_TIMING_SDRAM 0x00000A00 | |
431 | ||
432 | #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) | |
433 | #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
434 | ||
435 | #ifndef CONFIG_CAN_DRIVER | |
436 | #define CFG_OR3_PRELIM CFG_OR2_PRELIM | |
437 | #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
438 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
439 | #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
440 | #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
441 | #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) | |
442 | #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ | |
443 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
444 | #endif /* CONFIG_CAN_DRIVER */ | |
445 | ||
446 | /* | |
447 | * Memory Periodic Timer Prescaler | |
448 | * | |
449 | * The Divider for PTA (refresh timer) configuration is based on an | |
450 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
451 | * the number of chip selects (NCS) and the actually needed refresh | |
452 | * rate is done by setting MPTPR. | |
453 | * | |
454 | * PTA is calculated from | |
455 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
456 | * | |
457 | * gclk CPU clock (not bus clock!) | |
458 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
459 | * | |
460 | * 4096 Rows from SDRAM example configuration | |
461 | * 1000 factor s -> ms | |
462 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
463 | * 4 Number of refresh cycles per period | |
464 | * 64 Refresh cycle in ms per number of rows | |
465 | * -------------------------------------------- | |
466 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
467 | * | |
468 | * 50 MHz => 50.000.000 / Divider = 98 | |
469 | * 66 Mhz => 66.000.000 / Divider = 129 | |
470 | * 80 Mhz => 80.000.000 / Divider = 156 | |
471 | */ | |
472 | ||
473 | #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) | |
474 | #define CFG_MAMR_PTA 98 | |
475 | ||
476 | /* | |
477 | * For 16 MBit, refresh rates could be 31.3 us | |
478 | * (= 64 ms / 2K = 125 / quad bursts). | |
479 | * For a simpler initialization, 15.6 us is used instead. | |
480 | * | |
481 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
482 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
483 | */ | |
484 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
485 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
486 | ||
487 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
488 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
489 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
490 | ||
491 | /* | |
492 | * MAMR settings for SDRAM | |
493 | */ | |
494 | ||
495 | /* 8 column SDRAM */ | |
496 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
497 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
498 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
499 | /* 9 column SDRAM */ | |
500 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
501 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
502 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
503 | ||
504 | ||
505 | /* | |
506 | * Internal Definitions | |
507 | * | |
508 | * Boot Flags | |
509 | */ | |
510 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
511 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
512 | ||
513 | #define CONFIG_SCC1_ENET | |
514 | #define CONFIG_FEC_ENET | |
515 | #define CONFIG_ETHPRIME "SCC ETHERNET" | |
516 | ||
517 | #endif /* __CONFIG_H */ |