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1 | /* | |
2 | * (C) Copyright 2000-2014 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
21 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
22 | ||
23 | #define CONFIG_SYS_TEXT_BASE 0x40000000 | |
24 | ||
25 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ | |
26 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ | |
27 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
28 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ | |
29 | /* (it will be used if there is no */ | |
30 | /* 'cpuclk' variable with valid value) */ | |
31 | ||
32 | #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ | |
33 | /* (function measure_gclk() */ | |
34 | /* will be called) */ | |
35 | #ifdef CONFIG_SYS_MEASURE_CPUCLK | |
36 | #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
37 | #endif | |
38 | ||
39 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
40 | #define CONFIG_SYS_SMC_RXBUFLEN 128 | |
41 | #define CONFIG_SYS_MAXIDLE 10 | |
42 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
43 | ||
44 | #define CONFIG_BOOTCOUNT_LIMIT | |
45 | ||
46 | ||
47 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
48 | ||
49 | #define CONFIG_PREBOOT "echo;" \ | |
50 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
51 | "echo" | |
52 | ||
53 | #undef CONFIG_BOOTARGS | |
54 | ||
55 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
56 | "netdev=eth0\0" \ | |
57 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
58 | "nfsroot=${serverip}:${rootpath}\0" \ | |
59 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
60 | "addip=setenv bootargs ${bootargs} " \ | |
61 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
62 | ":${hostname}:${netdev}:off panic=1\0" \ | |
63 | "flash_nfs=run nfsargs addip;" \ | |
64 | "bootm ${kernel_addr}\0" \ | |
65 | "flash_self=run ramargs addip;" \ | |
66 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
67 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
68 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
69 | "hostname=TQM866M\0" \ | |
70 | "bootfile=TQM866M/uImage\0" \ | |
71 | "fdt_addr=400C0000\0" \ | |
72 | "kernel_addr=40100000\0" \ | |
73 | "ramdisk_addr=40280000\0" \ | |
74 | "u-boot=TQM866M/u-image.bin\0" \ | |
75 | "load=tftp 200000 ${u-boot}\0" \ | |
76 | "update=prot off 40000000 +${filesize};" \ | |
77 | "era 40000000 +${filesize};" \ | |
78 | "cp.b 200000 40000000 ${filesize};" \ | |
79 | "sete filesize;save\0" \ | |
80 | "" | |
81 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
82 | ||
83 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
84 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
85 | ||
86 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
87 | ||
88 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
89 | ||
90 | /* enable I2C and select the hardware/software driver */ | |
91 | #define CONFIG_SYS_I2C | |
92 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
93 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
94 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
95 | ||
96 | /* | |
97 | * Software (bit-bang) I2C driver configuration | |
98 | */ | |
99 | #define PB_SCL 0x00000020 /* PB 26 */ | |
100 | #define PB_SDA 0x00000010 /* PB 27 */ | |
101 | ||
102 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
103 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
104 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
105 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
106 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
107 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
108 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
109 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
110 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
111 | ||
112 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ | |
113 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
114 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
115 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
116 | ||
117 | /* | |
118 | * BOOTP options | |
119 | */ | |
120 | #define CONFIG_BOOTP_SUBNETMASK | |
121 | #define CONFIG_BOOTP_GATEWAY | |
122 | #define CONFIG_BOOTP_HOSTNAME | |
123 | #define CONFIG_BOOTP_BOOTPATH | |
124 | #define CONFIG_BOOTP_BOOTFILESIZE | |
125 | ||
126 | #define CONFIG_DOS_PARTITION | |
127 | ||
128 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ | |
129 | ||
130 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
131 | ||
132 | /* | |
133 | * Command line configuration. | |
134 | */ | |
135 | #define CONFIG_CMD_EEPROM | |
136 | #define CONFIG_CMD_IDE | |
137 | #define CONFIG_CMD_JFFS2 | |
138 | ||
139 | #define CONFIG_NETCONSOLE | |
140 | ||
141 | /* | |
142 | * Miscellaneous configurable options | |
143 | */ | |
144 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
145 | ||
146 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
147 | ||
148 | #if defined(CONFIG_CMD_KGDB) | |
149 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
150 | #else | |
151 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
152 | #endif | |
153 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
154 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
155 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
156 | ||
157 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ | |
158 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
159 | ||
160 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
161 | ||
162 | /* | |
163 | * Low Level Configuration Settings | |
164 | * (address mappings, register initial values, etc.) | |
165 | * You should know what you are doing if you make changes here. | |
166 | */ | |
167 | /*----------------------------------------------------------------------- | |
168 | * Internal Memory Mapped Register | |
169 | */ | |
170 | #define CONFIG_SYS_IMMR 0xFFF00000 | |
171 | ||
172 | /*----------------------------------------------------------------------- | |
173 | * Definitions for initial stack pointer and data area (in DPRAM) | |
174 | */ | |
175 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
176 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ | |
177 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
178 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
179 | ||
180 | /*----------------------------------------------------------------------- | |
181 | * Start addresses for the final memory configuration | |
182 | * (Set up by the startup code) | |
183 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
184 | */ | |
185 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
186 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
187 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
188 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
189 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
190 | ||
191 | /* | |
192 | * For booting Linux, the board info and command line data | |
193 | * have to be in the first 8 MB of memory, since this is | |
194 | * the maximum mapped by the Linux kernel during initialization. | |
195 | */ | |
196 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
197 | ||
198 | /*----------------------------------------------------------------------- | |
199 | * FLASH organization | |
200 | */ | |
201 | /* use CFI flash driver */ | |
202 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
203 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
204 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
205 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
206 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
207 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
209 | ||
210 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
211 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
212 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
213 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
214 | ||
215 | /* Address and size of Redundant Environment Sector */ | |
216 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) | |
217 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
218 | ||
219 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ | |
220 | ||
221 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ | |
222 | ||
223 | /*----------------------------------------------------------------------- | |
224 | * Dynamic MTD partition support | |
225 | */ | |
226 | #define CONFIG_CMD_MTDPARTS | |
227 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
228 | #define CONFIG_FLASH_CFI_MTD | |
229 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" | |
230 | ||
231 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
232 | "128k(dtb)," \ | |
233 | "1920k(kernel)," \ | |
234 | "5632(rootfs)," \ | |
235 | "4m(data)" | |
236 | ||
237 | /*----------------------------------------------------------------------- | |
238 | * Hardware Information Block | |
239 | */ | |
240 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
241 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
242 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * Cache Configuration | |
246 | */ | |
247 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
248 | #if defined(CONFIG_CMD_KGDB) | |
249 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
250 | #endif | |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * SYPCR - System Protection Control 11-9 | |
254 | * SYPCR can only be written once after reset! | |
255 | *----------------------------------------------------------------------- | |
256 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
257 | */ | |
258 | #if defined(CONFIG_WATCHDOG) | |
259 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
260 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
261 | #else | |
262 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
263 | #endif | |
264 | ||
265 | /*----------------------------------------------------------------------- | |
266 | * SIUMCR - SIU Module Configuration 11-6 | |
267 | *----------------------------------------------------------------------- | |
268 | * PCMCIA config., multi-function pin tri-state | |
269 | */ | |
270 | #ifndef CONFIG_CAN_DRIVER | |
271 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
272 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
273 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
274 | #endif /* CONFIG_CAN_DRIVER */ | |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * TBSCR - Time Base Status and Control 11-26 | |
278 | *----------------------------------------------------------------------- | |
279 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
280 | */ | |
281 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
282 | ||
283 | /*----------------------------------------------------------------------- | |
284 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
285 | *----------------------------------------------------------------------- | |
286 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
287 | */ | |
288 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) | |
289 | ||
290 | /*----------------------------------------------------------------------- | |
291 | * SCCR - System Clock and reset Control Register 15-27 | |
292 | *----------------------------------------------------------------------- | |
293 | * Set clock output, timebase and RTC source and divider, | |
294 | * power management and some other internal clocks | |
295 | */ | |
296 | #define SCCR_MASK SCCR_EBDF11 | |
297 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
298 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
299 | SCCR_DFALCD00) | |
300 | ||
301 | /*----------------------------------------------------------------------- | |
302 | * PCMCIA stuff | |
303 | *----------------------------------------------------------------------- | |
304 | * | |
305 | */ | |
306 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) | |
307 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
308 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
309 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
310 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
311 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
312 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
313 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
314 | ||
315 | /*----------------------------------------------------------------------- | |
316 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
317 | *----------------------------------------------------------------------- | |
318 | */ | |
319 | ||
320 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ | |
321 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
322 | ||
323 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
324 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
325 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
326 | ||
327 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
328 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
329 | ||
330 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
331 | ||
332 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
333 | ||
334 | /* Offset for data I/O */ | |
335 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
336 | ||
337 | /* Offset for normal register accesses */ | |
338 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
339 | ||
340 | /* Offset for alternate registers */ | |
341 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 | |
342 | ||
343 | /*----------------------------------------------------------------------- | |
344 | * | |
345 | *----------------------------------------------------------------------- | |
346 | * | |
347 | */ | |
348 | #define CONFIG_SYS_DER 0 | |
349 | ||
350 | /* | |
351 | * Init Memory Controller: | |
352 | * | |
353 | * BR0/1 and OR0/1 (FLASH) | |
354 | */ | |
355 | ||
356 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
357 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
358 | ||
359 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
360 | * restrict access enough to keep SRAM working (if any) | |
361 | * but not too much to meddle with FLASH accesses | |
362 | */ | |
363 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
364 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
365 | ||
366 | /* | |
367 | * FLASH timing: Default value of OR0 after reset | |
368 | */ | |
369 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ | |
370 | OR_SCY_15_CLK | OR_TRLX) | |
371 | ||
372 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
373 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
374 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
375 | ||
376 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP | |
377 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
378 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
379 | ||
380 | /* | |
381 | * BR2/3 and OR2/3 (SDRAM) | |
382 | * | |
383 | */ | |
384 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
385 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
386 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ | |
387 | ||
388 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
389 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 | |
390 | ||
391 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
392 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
393 | ||
394 | #ifndef CONFIG_CAN_DRIVER | |
395 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
396 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
397 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
398 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
399 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
400 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
401 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
402 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
403 | #endif /* CONFIG_CAN_DRIVER */ | |
404 | ||
405 | /* | |
406 | * 4096 Rows from SDRAM example configuration | |
407 | * 1000 factor s -> ms | |
408 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
409 | * 4 Number of refresh cycles per period | |
410 | * 64 Refresh cycle in ms per number of rows | |
411 | */ | |
412 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) | |
413 | ||
414 | /* | |
415 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) | |
416 | * | |
417 | * CPUclock(MHz) * 31.2 | |
418 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 | |
419 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 | |
420 | * | |
421 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us | |
422 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
423 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
424 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
425 | * | |
426 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
427 | * be met also in the default configuration, i.e. if environment variable | |
428 | * 'cpuclk' is not set. | |
429 | */ | |
430 | #define CONFIG_SYS_MAMR_PTA 97 | |
431 | ||
432 | /* | |
433 | * Memory Periodic Timer Prescaler Register (MPTPR) values. | |
434 | */ | |
435 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ | |
436 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 | |
437 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ | |
438 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 | |
439 | ||
440 | /* | |
441 | * MAMR settings for SDRAM | |
442 | */ | |
443 | ||
444 | /* 8 column SDRAM */ | |
445 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
446 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
447 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
448 | /* 9 column SDRAM */ | |
449 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
450 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
451 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
452 | /* 10 column SDRAM */ | |
453 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
454 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ | |
455 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
456 | ||
457 | #define CONFIG_SCC1_ENET | |
458 | #define CONFIG_FEC_ENET | |
459 | #define CONFIG_ETHPRIME "SCC" | |
460 | ||
461 | #define CONFIG_HWCONFIG 1 | |
462 | ||
463 | #endif /* __CONFIG_H */ |