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1 | /* | |
2 | * (C) Copyright 2000-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | /* | |
12 | * board/config.h - configuration options, board specific | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
18 | /* | |
19 | * High Level Configuration Options | |
20 | * (easy to change) | |
21 | */ | |
22 | ||
23 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
24 | #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ | |
25 | ||
26 | #define CONFIG_SYS_TEXT_BASE 0x40000000 | |
27 | ||
28 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ | |
29 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ | |
30 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
31 | #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ | |
32 | /* (it will be used if there is no */ | |
33 | /* 'cpuclk' variable with valid value) */ | |
34 | ||
35 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
36 | #define CONFIG_SYS_SMC_RXBUFLEN 128 | |
37 | #define CONFIG_SYS_MAXIDLE 10 | |
38 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
39 | ||
40 | #define CONFIG_BOOTCOUNT_LIMIT | |
41 | ||
42 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
43 | ||
44 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
45 | ||
46 | #define CONFIG_PREBOOT "echo;" \ | |
47 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
48 | "echo" | |
49 | ||
50 | #undef CONFIG_BOOTARGS | |
51 | ||
52 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53 | "netdev=eth0\0" \ | |
54 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
55 | "nfsroot=${serverip}:${rootpath}\0" \ | |
56 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
57 | "addip=setenv bootargs ${bootargs} " \ | |
58 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
59 | ":${hostname}:${netdev}:off panic=1\0" \ | |
60 | "flash_nfs=run nfsargs addip;" \ | |
61 | "bootm ${kernel_addr}\0" \ | |
62 | "flash_self=run ramargs addip;" \ | |
63 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
64 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
65 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
66 | "bootfile=/tftpboot/TQM885D/uImage\0" \ | |
67 | "fdt_addr=400C0000\0" \ | |
68 | "kernel_addr=40100000\0" \ | |
69 | "ramdisk_addr=40280000\0" \ | |
70 | "load=tftp 200000 ${u-boot}\0" \ | |
71 | "update=protect off 40000000 +${filesize};" \ | |
72 | "erase 40000000 +${filesize};" \ | |
73 | "cp.b 200000 40000000 ${filesize};" \ | |
74 | "protect on 40000000 +${filesize}\0" \ | |
75 | "" | |
76 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
77 | ||
78 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
79 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
80 | ||
81 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
82 | ||
83 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
84 | ||
85 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
86 | ||
87 | /* enable I2C and select the hardware/software driver */ | |
88 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
89 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
90 | ||
91 | #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ | |
92 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
93 | ||
94 | #ifdef CONFIG_SOFT_I2C | |
95 | /* | |
96 | * Software (bit-bang) I2C driver configuration | |
97 | */ | |
98 | #define PB_SCL 0x00000020 /* PB 26 */ | |
99 | #define PB_SDA 0x00000010 /* PB 27 */ | |
100 | ||
101 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
102 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
103 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
104 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
105 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
106 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
107 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
108 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
109 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ | |
110 | #endif /* CONFIG_SOFT_I2C */ | |
111 | ||
112 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ | |
113 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
114 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
115 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
116 | ||
117 | # define CONFIG_RTC_DS1337 1 | |
118 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
119 | ||
120 | /* | |
121 | * BOOTP options | |
122 | */ | |
123 | #define CONFIG_BOOTP_SUBNETMASK | |
124 | #define CONFIG_BOOTP_GATEWAY | |
125 | #define CONFIG_BOOTP_HOSTNAME | |
126 | #define CONFIG_BOOTP_BOOTPATH | |
127 | #define CONFIG_BOOTP_BOOTFILESIZE | |
128 | ||
129 | ||
130 | #define CONFIG_MAC_PARTITION | |
131 | #define CONFIG_DOS_PARTITION | |
132 | ||
133 | #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ | |
134 | ||
135 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
136 | ||
137 | ||
138 | /* | |
139 | * Command line configuration. | |
140 | */ | |
141 | #include <config_cmd_default.h> | |
142 | ||
143 | #define CONFIG_CMD_ASKENV | |
144 | #define CONFIG_CMD_DATE | |
145 | #define CONFIG_CMD_DHCP | |
146 | #define CONFIG_CMD_EEPROM | |
147 | #define CONFIG_CMD_EXT2 | |
148 | #define CONFIG_CMD_I2C | |
149 | #define CONFIG_CMD_IDE | |
150 | #define CONFIG_CMD_MII | |
151 | #define CONFIG_CMD_NFS | |
152 | #define CONFIG_CMD_PING | |
153 | ||
154 | ||
155 | /* | |
156 | * Miscellaneous configurable options | |
157 | */ | |
158 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
159 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
160 | ||
161 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
162 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ | |
163 | ||
164 | #if defined(CONFIG_CMD_KGDB) | |
165 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
166 | #else | |
167 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
168 | #endif | |
169 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
170 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
171 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
172 | ||
173 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ | |
174 | #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ | |
175 | #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive | |
176 | memory test.*/ | |
177 | ||
178 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
179 | ||
180 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
181 | ||
182 | /* | |
183 | * Enable loopw command. | |
184 | */ | |
185 | #define CONFIG_LOOPW | |
186 | ||
187 | /* | |
188 | * Low Level Configuration Settings | |
189 | * (address mappings, register initial values, etc.) | |
190 | * You should know what you are doing if you make changes here. | |
191 | */ | |
192 | /*----------------------------------------------------------------------- | |
193 | * Internal Memory Mapped Register | |
194 | */ | |
195 | #define CONFIG_SYS_IMMR 0xFFF00000 | |
196 | ||
197 | /*----------------------------------------------------------------------- | |
198 | * Definitions for initial stack pointer and data area (in DPRAM) | |
199 | */ | |
200 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
201 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ | |
202 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
203 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * Start addresses for the final memory configuration | |
207 | * (Set up by the startup code) | |
208 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
209 | */ | |
210 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
211 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
212 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
213 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
214 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ | |
215 | ||
216 | /* | |
217 | * For booting Linux, the board info and command line data | |
218 | * have to be in the first 8 MB of memory, since this is | |
219 | * the maximum mapped by the Linux kernel during initialization. | |
220 | */ | |
221 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
222 | ||
223 | /*----------------------------------------------------------------------- | |
224 | * FLASH organization | |
225 | */ | |
226 | ||
227 | /* use CFI flash driver */ | |
228 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
229 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
230 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
231 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
232 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
233 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
234 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
235 | ||
236 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
237 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ | |
238 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ | |
239 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
240 | ||
241 | /* Address and size of Redundant Environment Sector */ | |
242 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) | |
243 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
244 | ||
245 | /*----------------------------------------------------------------------- | |
246 | * Hardware Information Block | |
247 | */ | |
248 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
249 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
250 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * Cache Configuration | |
254 | */ | |
255 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
256 | #if defined(CONFIG_CMD_KGDB) | |
257 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
258 | #endif | |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * SYPCR - System Protection Control 11-9 | |
262 | * SYPCR can only be written once after reset! | |
263 | *----------------------------------------------------------------------- | |
264 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
265 | */ | |
266 | #if defined(CONFIG_WATCHDOG) | |
267 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
268 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
269 | #else | |
270 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
271 | #endif | |
272 | ||
273 | /*----------------------------------------------------------------------- | |
274 | * SIUMCR - SIU Module Configuration 11-6 | |
275 | *----------------------------------------------------------------------- | |
276 | * PCMCIA config., multi-function pin tri-state | |
277 | */ | |
278 | #ifndef CONFIG_CAN_DRIVER | |
279 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
280 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
281 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
282 | #endif /* CONFIG_CAN_DRIVER */ | |
283 | ||
284 | /*----------------------------------------------------------------------- | |
285 | * TBSCR - Time Base Status and Control 11-26 | |
286 | *----------------------------------------------------------------------- | |
287 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
288 | */ | |
289 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
290 | ||
291 | /*----------------------------------------------------------------------- | |
292 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
293 | *----------------------------------------------------------------------- | |
294 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
295 | */ | |
296 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) | |
297 | ||
298 | /*----------------------------------------------------------------------- | |
299 | * SCCR - System Clock and reset Control Register 15-27 | |
300 | *----------------------------------------------------------------------- | |
301 | * Set clock output, timebase and RTC source and divider, | |
302 | * power management and some other internal clocks | |
303 | */ | |
304 | #define SCCR_MASK SCCR_EBDF11 | |
305 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
306 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
307 | SCCR_DFALCD00) | |
308 | ||
309 | /*----------------------------------------------------------------------- | |
310 | * PCMCIA stuff | |
311 | *----------------------------------------------------------------------- | |
312 | * | |
313 | */ | |
314 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) | |
315 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
316 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
317 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
318 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
319 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
320 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
321 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
322 | ||
323 | /*----------------------------------------------------------------------- | |
324 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
325 | *----------------------------------------------------------------------- | |
326 | */ | |
327 | ||
328 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ | |
329 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
330 | ||
331 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
332 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
333 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
334 | ||
335 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
336 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
337 | ||
338 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
339 | ||
340 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
341 | ||
342 | /* Offset for data I/O */ | |
343 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
344 | ||
345 | /* Offset for normal register accesses */ | |
346 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
347 | ||
348 | /* Offset for alternate registers */ | |
349 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 | |
350 | ||
351 | /*----------------------------------------------------------------------- | |
352 | * | |
353 | *----------------------------------------------------------------------- | |
354 | * | |
355 | */ | |
356 | #define CONFIG_SYS_DER 0 | |
357 | ||
358 | /* | |
359 | * Init Memory Controller: | |
360 | * | |
361 | * BR0/1 and OR0/1 (FLASH) | |
362 | */ | |
363 | ||
364 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
365 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
366 | ||
367 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
368 | * restrict access enough to keep SRAM working (if any) | |
369 | * but not too much to meddle with FLASH accesses | |
370 | */ | |
371 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
372 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
373 | ||
374 | /* | |
375 | * FLASH timing: Default value of OR0 after reset | |
376 | */ | |
377 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ | |
378 | OR_SCY_6_CLK | OR_TRLX) | |
379 | ||
380 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
381 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
382 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
383 | ||
384 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP | |
385 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
386 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
387 | ||
388 | /* | |
389 | * BR2/3 and OR2/3 (SDRAM) | |
390 | * | |
391 | */ | |
392 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
393 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
394 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ | |
395 | ||
396 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
397 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 | |
398 | ||
399 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
400 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
401 | ||
402 | #ifndef CONFIG_CAN_DRIVER | |
403 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
404 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
405 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
406 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
407 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
408 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
409 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
410 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
411 | #endif /* CONFIG_CAN_DRIVER */ | |
412 | ||
413 | /* | |
414 | * 4096 Rows from SDRAM example configuration | |
415 | * 1000 factor s -> ms | |
416 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
417 | * 4 Number of refresh cycles per period | |
418 | * 64 Refresh cycle in ms per number of rows | |
419 | */ | |
420 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) | |
421 | ||
422 | /* | |
423 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) | |
424 | * | |
425 | * CPUclock(MHz) * 31.2 | |
426 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 | |
427 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 | |
428 | * | |
429 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us | |
430 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
431 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
432 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
433 | * | |
434 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
435 | * be met also in the default configuration, i.e. if environment variable | |
436 | * 'cpuclk' is not set. | |
437 | */ | |
438 | #define CONFIG_SYS_MAMR_PTA 128 | |
439 | ||
440 | /* | |
441 | * Memory Periodic Timer Prescaler Register (MPTPR) values. | |
442 | */ | |
443 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ | |
444 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 | |
445 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ | |
446 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 | |
447 | ||
448 | /* | |
449 | * MAMR settings for SDRAM | |
450 | */ | |
451 | ||
452 | /* 8 column SDRAM */ | |
453 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
454 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
455 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
456 | /* 9 column SDRAM */ | |
457 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
458 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
459 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
460 | /* 10 column SDRAM */ | |
461 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
462 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ | |
463 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
464 | ||
465 | /* | |
466 | * Network configuration | |
467 | */ | |
468 | #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ | |
469 | #define CONFIG_FEC_ENET /* enable ethernet on FEC */ | |
470 | #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ | |
471 | #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ | |
472 | ||
473 | #if defined(CONFIG_CMD_MII) | |
474 | #define CONFIG_SYS_DISCOVER_PHY | |
475 | #define CONFIG_MII_INIT 1 | |
476 | #endif | |
477 | ||
478 | #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before | |
479 | switching to another netwok (if the | |
480 | tried network is unreachable) */ | |
481 | ||
482 | #define CONFIG_ETHPRIME "SCC" | |
483 | ||
484 | /* pass open firmware flat tree */ | |
485 | #define CONFIG_OF_LIBFDT 1 | |
486 | #define CONFIG_OF_BOARD_SETUP 1 | |
487 | #define CONFIG_HWCONFIG 1 | |
488 | ||
489 | #endif /* __CONFIG_H */ |