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1 | /* | |
2 | * Copyright 2009 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * xpedite5170 board configuration file | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | */ | |
33 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
34 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
35 | #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ | |
36 | #define CONFIG_SYS_BOARD_NAME "XPedite5170" | |
37 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
38 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ | |
39 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ | |
40 | #define CONFIG_ALTIVEC 1 | |
41 | ||
42 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
43 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
44 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
45 | #define CONFIG_PCIE1 1 /* PCIE controler 1 */ | |
46 | #define CONFIG_PCIE2 1 /* PCIE controler 2 */ | |
47 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
48 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
49 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
50 | ||
51 | /* | |
52 | * DDR config | |
53 | */ | |
54 | #define CONFIG_FSL_DDR2 | |
55 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
56 | #define CONFIG_DDR_SPD | |
57 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
58 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
59 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
60 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
61 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
62 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
63 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
64 | #define CONFIG_DDR_ECC | |
65 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
66 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
67 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
68 | #define CONFIG_VERY_BIG_RAM | |
69 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ | |
70 | ||
71 | /* | |
72 | * virtual address to be used for temporary mappings. There | |
73 | * should be 128k free at this VA. | |
74 | */ | |
75 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
76 | ||
77 | #ifndef __ASSEMBLY__ | |
78 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
79 | #endif | |
80 | ||
81 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ | |
82 | ||
83 | /* | |
84 | * L2CR setup | |
85 | */ | |
86 | #define CONFIG_SYS_L2 | |
87 | #define L2_INIT 0 | |
88 | #define L2_ENABLE (L2CR_L2E) | |
89 | ||
90 | /* | |
91 | * Base addresses -- Note these are effective addresses where the | |
92 | * actual resources get mapped (not physical addresses) | |
93 | */ | |
94 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
95 | #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ | |
96 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR | |
97 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
98 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
99 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR | |
100 | ||
101 | /* | |
102 | * Diagnostics | |
103 | */ | |
104 | #define CONFIG_SYS_ALT_MEMTEST | |
105 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
106 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
107 | ||
108 | /* | |
109 | * Memory map | |
110 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
111 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
112 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
113 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
114 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
115 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
116 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable | |
117 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
118 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
119 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
120 | */ | |
121 | ||
122 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) | |
123 | ||
124 | /* | |
125 | * NAND flash configuration | |
126 | */ | |
127 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
128 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
129 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} | |
130 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
131 | #define CONFIG_NAND_ACTL | |
132 | #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ | |
133 | #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ | |
134 | #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ | |
135 | #define CONFIG_SYS_NAND_ACTL_DELAY 25 | |
136 | #define CONFIG_SYS_NAND_QUIET_TEST | |
137 | #define CONFIG_JFFS2_NAND | |
138 | ||
139 | /* | |
140 | * NOR flash configuration | |
141 | */ | |
142 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
143 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
144 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
145 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
146 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
147 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
148 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
149 | #define CONFIG_FLASH_CFI_DRIVER | |
150 | #define CONFIG_SYS_FLASH_CFI | |
151 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
152 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ | |
153 | {0xf7f00000, 0xc0000} } | |
154 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
155 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ | |
156 | ||
157 | /* | |
158 | * Chip select configuration | |
159 | */ | |
160 | /* NOR Flash 0 on CS0 */ | |
161 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ | |
162 | BR_PS_16 |\ | |
163 | BR_V) | |
164 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ | |
165 | OR_GPCM_CSNT |\ | |
166 | OR_GPCM_XACS |\ | |
167 | OR_GPCM_ACS_DIV2 |\ | |
168 | OR_GPCM_SCY_8 |\ | |
169 | OR_GPCM_TRLX |\ | |
170 | OR_GPCM_EHTR |\ | |
171 | OR_GPCM_EAD) | |
172 | ||
173 | /* NOR Flash 1 on CS1 */ | |
174 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ | |
175 | BR_PS_16 |\ | |
176 | BR_V) | |
177 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
178 | ||
179 | /* NAND flash on CS2 */ | |
180 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ | |
181 | BR_PS_8 |\ | |
182 | BR_V) | |
183 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ | |
184 | OR_GPCM_BCTLD |\ | |
185 | OR_GPCM_CSNT |\ | |
186 | OR_GPCM_ACS_DIV4 |\ | |
187 | OR_GPCM_SCY_4 |\ | |
188 | OR_GPCM_TRLX |\ | |
189 | OR_GPCM_EHTR) | |
190 | ||
191 | /* Optional NAND flash on CS3 */ | |
192 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ | |
193 | BR_PS_8 |\ | |
194 | BR_V) | |
195 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
196 | ||
197 | /* | |
198 | * Use L1 as initial stack | |
199 | */ | |
200 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
202 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 | |
203 | ||
204 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
205 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
206 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
207 | ||
208 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
209 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
210 | ||
211 | /* | |
212 | * Serial Port | |
213 | */ | |
214 | #define CONFIG_CONS_INDEX 1 | |
215 | #define CONFIG_SYS_NS16550 | |
216 | #define CONFIG_SYS_NS16550_SERIAL | |
217 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
218 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
219 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
220 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
221 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
222 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
223 | #define CONFIG_BAUDRATE 115200 | |
224 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
225 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
226 | ||
227 | /* | |
228 | * Use the HUSH parser | |
229 | */ | |
230 | #define CONFIG_SYS_HUSH_PARSER | |
231 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
232 | ||
233 | /* | |
234 | * Pass open firmware flat tree | |
235 | */ | |
236 | #define CONFIG_OF_LIBFDT 1 | |
237 | #define CONFIG_OF_BOARD_SETUP 1 | |
238 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
239 | ||
240 | /* | |
241 | * I2C | |
242 | */ | |
243 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
244 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
245 | #define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */ | |
246 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
247 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
248 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
249 | #define CONFIG_I2C_MULTI_BUS | |
250 | ||
251 | /* PEX8518 slave I2C interface */ | |
252 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
253 | ||
254 | /* I2C DS1631 temperature sensor */ | |
255 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
256 | #define CONFIG_DTT_DS1621 | |
257 | #define CONFIG_DTT_SENSORS { 0 } | |
258 | ||
259 | /* I2C EEPROM - AT24C128B */ | |
260 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
261 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
262 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
263 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
264 | ||
265 | /* I2C RTC */ | |
266 | #define CONFIG_RTC_M41T11 1 | |
267 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
268 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
269 | ||
270 | /* GPIO/EEPROM/SRAM */ | |
271 | #define CONFIG_DS4510 | |
272 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
273 | ||
274 | /* GPIO */ | |
275 | #define CONFIG_PCA953X | |
276 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
277 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
278 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
279 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
280 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
281 | ||
282 | /* | |
283 | * PU = pulled high, PD = pulled low | |
284 | * I = input, O = output, IO = input/output | |
285 | */ | |
286 | /* PCA9557 @ 0x18*/ | |
287 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
288 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
289 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
290 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
291 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
292 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
293 | ||
294 | /* PCA9557 @ 0x1c*/ | |
295 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
296 | #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ | |
297 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
298 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
299 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
300 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
301 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
302 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
303 | ||
304 | /* PCA9557 @ 0x1e*/ | |
305 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
306 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
307 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
308 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
309 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
310 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ | |
311 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ | |
312 | ||
313 | /* PCA9557 @ 0x1f */ | |
314 | #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ | |
315 | #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ | |
316 | #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ | |
317 | #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ | |
318 | ||
319 | /* | |
320 | * General PCI | |
321 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
322 | */ | |
323 | /* PCIE1 - PEX8518 */ | |
324 | #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 | |
325 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE | |
326 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ | |
327 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
328 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 | |
329 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
330 | ||
331 | /* PCIE2 - VPX P1 */ | |
332 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 | |
333 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE | |
334 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
335 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
336 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 | |
337 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
338 | ||
339 | /* | |
340 | * Networking options | |
341 | */ | |
342 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
343 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
344 | #define CONFIG_NET_MULTI 1 | |
345 | #define CONFIG_MII 1 /* MII PHY management */ | |
346 | #define CONFIG_ETHPRIME "eTSEC1" | |
347 | ||
348 | #define CONFIG_TSEC1 1 | |
349 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
350 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
351 | #define TSEC1_PHY_ADDR 1 | |
352 | #define TSEC1_PHYIDX 0 | |
353 | #define CONFIG_HAS_ETH0 | |
354 | ||
355 | #define CONFIG_TSEC2 1 | |
356 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
357 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
358 | #define TSEC2_PHY_ADDR 2 | |
359 | #define TSEC2_PHYIDX 0 | |
360 | #define CONFIG_HAS_ETH1 | |
361 | ||
362 | /* | |
363 | * BAT mappings | |
364 | */ | |
365 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) | |
366 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
367 | BATL_PP_RW |\ | |
368 | BATL_CACHEINHIBIT |\ | |
369 | BATL_GUARDEDSTORAGE) | |
370 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
371 | BATU_BL_1M |\ | |
372 | BATU_VS |\ | |
373 | BATU_VP) | |
374 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ | |
375 | BATL_PP_RW |\ | |
376 | BATL_CACHEINHIBIT) | |
377 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
378 | #endif | |
379 | ||
380 | /* | |
381 | * BAT0 2G Cacheable, non-guarded | |
382 | * 0x0000_0000 2G DDR | |
383 | */ | |
384 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
385 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
386 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
387 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
388 | ||
389 | /* | |
390 | * BAT1 1G Cache-inhibited, guarded | |
391 | * 0x8000_0000 1G PCI-Express 1 Memory | |
392 | */ | |
393 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
394 | BATL_PP_RW |\ | |
395 | BATL_CACHEINHIBIT |\ | |
396 | BATL_GUARDEDSTORAGE) | |
397 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
398 | BATU_BL_1G |\ | |
399 | BATU_VS |\ | |
400 | BATU_VP) | |
401 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ | |
402 | BATL_PP_RW |\ | |
403 | BATL_CACHEINHIBIT) | |
404 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
405 | ||
406 | /* | |
407 | * BAT2 512M Cache-inhibited, guarded | |
408 | * 0xc000_0000 512M PCI-Express 2 Memory | |
409 | */ | |
410 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
411 | BATL_PP_RW |\ | |
412 | BATL_CACHEINHIBIT |\ | |
413 | BATL_GUARDEDSTORAGE) | |
414 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
415 | BATU_BL_512M |\ | |
416 | BATU_VS |\ | |
417 | BATU_VP) | |
418 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ | |
419 | BATL_PP_RW |\ | |
420 | BATL_CACHEINHIBIT) | |
421 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
422 | ||
423 | /* | |
424 | * BAT3 1M Cache-inhibited, guarded | |
425 | * 0xe000_0000 1M CCSR | |
426 | */ | |
427 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ | |
428 | BATL_PP_RW |\ | |
429 | BATL_CACHEINHIBIT |\ | |
430 | BATL_GUARDEDSTORAGE) | |
431 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ | |
432 | BATU_BL_1M |\ | |
433 | BATU_VS |\ | |
434 | BATU_VP) | |
435 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ | |
436 | BATL_PP_RW |\ | |
437 | BATL_CACHEINHIBIT) | |
438 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
439 | ||
440 | /* | |
441 | * BAT4 32M Cache-inhibited, guarded | |
442 | * 0xe200_0000 16M PCI-Express 1 I/O | |
443 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
444 | */ | |
445 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
446 | BATL_PP_RW |\ | |
447 | BATL_CACHEINHIBIT |\ | |
448 | BATL_GUARDEDSTORAGE) | |
449 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
450 | BATU_BL_32M |\ | |
451 | BATU_VS |\ | |
452 | BATU_VP) | |
453 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ | |
454 | BATL_PP_RW |\ | |
455 | BATL_CACHEINHIBIT) | |
456 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U | |
457 | ||
458 | /* | |
459 | * BAT5 128K Cacheable, non-guarded | |
460 | * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
461 | */ | |
462 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ | |
463 | BATL_PP_RW |\ | |
464 | BATL_MEMCOHERENCE) | |
465 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ | |
466 | BATU_BL_128K |\ | |
467 | BATU_VS |\ | |
468 | BATU_VP) | |
469 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
470 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
471 | ||
472 | /* | |
473 | * BAT6 256M Cache-inhibited, guarded | |
474 | * 0xf000_0000 256M FLASH | |
475 | */ | |
476 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ | |
477 | BATL_PP_RW |\ | |
478 | BATL_CACHEINHIBIT |\ | |
479 | BATL_GUARDEDSTORAGE) | |
480 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ | |
481 | BATU_BL_256M |\ | |
482 | BATU_VS |\ | |
483 | BATU_VP) | |
484 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ | |
485 | BATL_PP_RW |\ | |
486 | BATL_MEMCOHERENCE) | |
487 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
488 | ||
489 | /* Map the last 1M of flash where we're running from reset */ | |
490 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ | |
491 | BATL_PP_RW |\ | |
492 | BATL_CACHEINHIBIT |\ | |
493 | BATL_GUARDEDSTORAGE) | |
494 | #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\ | |
495 | BATU_BL_1M |\ | |
496 | BATU_VS |\ | |
497 | BATU_VP) | |
498 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ | |
499 | BATL_PP_RW |\ | |
500 | BATL_MEMCOHERENCE) | |
501 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
502 | ||
503 | /* | |
504 | * BAT7 64M Cache-inhibited, guarded | |
505 | * 0xe800_0000 64K NAND FLASH | |
506 | * 0xe804_0000 128K DUART Registers | |
507 | */ | |
508 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ | |
509 | BATL_PP_RW |\ | |
510 | BATL_CACHEINHIBIT |\ | |
511 | BATL_GUARDEDSTORAGE) | |
512 | #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ | |
513 | BATU_BL_512K |\ | |
514 | BATU_VS |\ | |
515 | BATU_VP) | |
516 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ | |
517 | BATL_PP_RW |\ | |
518 | BATL_CACHEINHIBIT) | |
519 | #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U | |
520 | ||
521 | /* | |
522 | * Command configuration. | |
523 | */ | |
524 | #include <config_cmd_default.h> | |
525 | ||
526 | #define CONFIG_CMD_ASKENV | |
527 | #define CONFIG_CMD_DATE | |
528 | #define CONFIG_CMD_DHCP | |
529 | #define CONFIG_CMD_DS4510 | |
530 | #define CONFIG_CMD_DS4510_INFO | |
531 | #define CONFIG_CMD_DTT | |
532 | #define CONFIG_CMD_EEPROM | |
533 | #define CONFIG_CMD_ELF | |
534 | #define CONFIG_CMD_SAVEENV | |
535 | #define CONFIG_CMD_FLASH | |
536 | #define CONFIG_CMD_I2C | |
537 | #define CONFIG_CMD_IRQ | |
538 | #define CONFIG_CMD_JFFS2 | |
539 | #define CONFIG_CMD_MII | |
540 | #define CONFIG_CMD_NAND | |
541 | #define CONFIG_CMD_NET | |
542 | #define CONFIG_CMD_PCA953X | |
543 | #define CONFIG_CMD_PCA953X_INFO | |
544 | #define CONFIG_CMD_PCI | |
545 | #define CONFIG_CMD_PING | |
546 | #define CONFIG_CMD_REGINFO | |
547 | #define CONFIG_CMD_SNTP | |
548 | ||
549 | /* | |
550 | * Miscellaneous configurable options | |
551 | */ | |
552 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
553 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
554 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
555 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
556 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
557 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
558 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
559 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
560 | #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ | |
561 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ | |
562 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ | |
563 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
564 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
565 | #define CONFIG_FIT 1 | |
566 | #define CONFIG_FIT_VERBOSE 1 | |
567 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ | |
568 | ||
569 | /* | |
570 | * For booting Linux, the board info and command line data | |
571 | * have to be in the first 16 MB of memory, since this is | |
572 | * the maximum mapped by the Linux kernel during initialization. | |
573 | */ | |
574 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
575 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
576 | ||
577 | /* | |
578 | * Boot Flags | |
579 | */ | |
580 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
581 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
582 | ||
583 | /* | |
584 | * Environment Configuration | |
585 | */ | |
586 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
587 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
588 | #define CONFIG_ENV_SIZE 0x8000 | |
589 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
590 | ||
591 | /* | |
592 | * Flash memory map: | |
593 | * fffc0000 - ffffffff Pri FDT (256KB) | |
594 | * fff80000 - fffbffff Pri U-Boot Environment (256 KB) | |
595 | * fff00000 - fff7ffff Pri U-Boot (512 KB) | |
596 | * fef00000 - ffefffff Pri OS image (16MB) | |
597 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
598 | * | |
599 | * f7fc0000 - f7ffffff Sec FDT (256KB) | |
600 | * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) | |
601 | * f7f00000 - f7f7ffff Sec U-Boot (512 KB) | |
602 | * f6f00000 - f7efffff Sec OS image (16MB) | |
603 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
604 | */ | |
605 | #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000) | |
606 | #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000) | |
607 | #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000) | |
608 | #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000) | |
609 | #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) | |
610 | #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) | |
611 | ||
612 | #define CONFIG_PROG_UBOOT1 \ | |
613 | "$download_cmd $loadaddr $ubootfile; " \ | |
614 | "if test $? -eq 0; then " \ | |
615 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
616 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
617 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
618 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
619 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
620 | "if test $? -ne 0; then " \ | |
621 | "echo PROGRAM FAILED; " \ | |
622 | "else; " \ | |
623 | "echo PROGRAM SUCCEEDED; " \ | |
624 | "fi; " \ | |
625 | "else; " \ | |
626 | "echo DOWNLOAD FAILED; " \ | |
627 | "fi;" | |
628 | ||
629 | #define CONFIG_PROG_UBOOT2 \ | |
630 | "$download_cmd $loadaddr $ubootfile; " \ | |
631 | "if test $? -eq 0; then " \ | |
632 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
633 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
634 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
635 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
636 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
637 | "if test $? -ne 0; then " \ | |
638 | "echo PROGRAM FAILED; " \ | |
639 | "else; " \ | |
640 | "echo PROGRAM SUCCEEDED; " \ | |
641 | "fi; " \ | |
642 | "else; " \ | |
643 | "echo DOWNLOAD FAILED; " \ | |
644 | "fi;" | |
645 | ||
646 | #define CONFIG_BOOT_OS_NET \ | |
647 | "$download_cmd $osaddr $osfile; " \ | |
648 | "if test $? -eq 0; then " \ | |
649 | "if test -n $fdtaddr; then " \ | |
650 | "$download_cmd $fdtaddr $fdtfile; " \ | |
651 | "if test $? -eq 0; then " \ | |
652 | "bootm $osaddr - $fdtaddr; " \ | |
653 | "else; " \ | |
654 | "echo FDT DOWNLOAD FAILED; " \ | |
655 | "fi; " \ | |
656 | "else; " \ | |
657 | "bootm $osaddr; " \ | |
658 | "fi; " \ | |
659 | "else; " \ | |
660 | "echo OS DOWNLOAD FAILED; " \ | |
661 | "fi;" | |
662 | ||
663 | #define CONFIG_PROG_OS1 \ | |
664 | "$download_cmd $osaddr $osfile; " \ | |
665 | "if test $? -eq 0; then " \ | |
666 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
667 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
668 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
669 | "if test $? -ne 0; then " \ | |
670 | "echo OS PROGRAM FAILED; " \ | |
671 | "else; " \ | |
672 | "echo OS PROGRAM SUCCEEDED; " \ | |
673 | "fi; " \ | |
674 | "else; " \ | |
675 | "echo OS DOWNLOAD FAILED; " \ | |
676 | "fi;" | |
677 | ||
678 | #define CONFIG_PROG_OS2 \ | |
679 | "$download_cmd $osaddr $osfile; " \ | |
680 | "if test $? -eq 0; then " \ | |
681 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
682 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
683 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
684 | "if test $? -ne 0; then " \ | |
685 | "echo OS PROGRAM FAILED; " \ | |
686 | "else; " \ | |
687 | "echo OS PROGRAM SUCCEEDED; " \ | |
688 | "fi; " \ | |
689 | "else; " \ | |
690 | "echo OS DOWNLOAD FAILED; " \ | |
691 | "fi;" | |
692 | ||
693 | #define CONFIG_PROG_FDT1 \ | |
694 | "$download_cmd $fdtaddr $fdtfile; " \ | |
695 | "if test $? -eq 0; then " \ | |
696 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
697 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
698 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
699 | "if test $? -ne 0; then " \ | |
700 | "echo FDT PROGRAM FAILED; " \ | |
701 | "else; " \ | |
702 | "echo FDT PROGRAM SUCCEEDED; " \ | |
703 | "fi; " \ | |
704 | "else; " \ | |
705 | "echo FDT DOWNLOAD FAILED; " \ | |
706 | "fi;" | |
707 | ||
708 | #define CONFIG_PROG_FDT2 \ | |
709 | "$download_cmd $fdtaddr $fdtfile; " \ | |
710 | "if test $? -eq 0; then " \ | |
711 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
712 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
713 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
714 | "if test $? -ne 0; then " \ | |
715 | "echo FDT PROGRAM FAILED; " \ | |
716 | "else; " \ | |
717 | "echo FDT PROGRAM SUCCEEDED; " \ | |
718 | "fi; " \ | |
719 | "else; " \ | |
720 | "echo FDT DOWNLOAD FAILED; " \ | |
721 | "fi;" | |
722 | ||
723 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
724 | "autoload=yes\0" \ | |
725 | "download_cmd=tftp\0" \ | |
726 | "console_args=console=ttyS0,115200\0" \ | |
727 | "root_args=root=/dev/nfs rw\0" \ | |
728 | "misc_args=ip=on\0" \ | |
729 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
730 | "bootfile=/home/user/file\0" \ | |
731 | "osfile=/home/user/uImage-XPedite5170\0" \ | |
732 | "fdtfile=/home/user/xpedite5170.dtb\0" \ | |
733 | "ubootfile=/home/user/u-boot.bin\0" \ | |
734 | "fdtaddr=c00000\0" \ | |
735 | "osaddr=0x1000000\0" \ | |
736 | "loadaddr=0x1000000\0" \ | |
737 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
738 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
739 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
740 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
741 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
742 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
743 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
744 | "bootcmd_flash1=run set_bootargs; " \ | |
745 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
746 | "bootcmd_flash2=run set_bootargs; " \ | |
747 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
748 | "bootcmd=run bootcmd_flash1\0" | |
749 | #endif /* __CONFIG_H */ |