| | 1 | /* |
| | 2 | * U-boot - Configuration file for BF533 STAMP board |
| | 3 | */ |
| | 4 | |
| | 5 | #ifndef __CONFIG_BF533_STAMP_H__ |
| | 6 | #define __CONFIG_BF533_STAMP_H__ |
| | 7 | |
| | 8 | #include <asm/config-pre.h> |
| | 9 | |
| | 10 | |
| | 11 | /* |
| | 12 | * Processor Settings |
| | 13 | */ |
| | 14 | #define CONFIG_BFIN_CPU bf533-0.3 |
| | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
| | 16 | |
| | 17 | /* |
| | 18 | * Clock Settings |
| | 19 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| | 20 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
| | 21 | */ |
| | 22 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| | 23 | #define CONFIG_CLKIN_HZ 11059200 |
| | 24 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| | 25 | /* 1 = CLKIN / 2 */ |
| | 26 | #define CONFIG_CLKIN_HALF 0 |
| | 27 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| | 28 | /* 1 = bypass PLL */ |
| | 29 | #define CONFIG_PLL_BYPASS 0 |
| | 30 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| | 31 | /* Values can range from 0-63 (where 0 means 64) */ |
| | 32 | #define CONFIG_VCO_MULT 45 |
| | 33 | /* CCLK_DIV controls the core clock divider */ |
| | 34 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| | 35 | #define CONFIG_CCLK_DIV 1 |
| | 36 | /* SCLK_DIV controls the system clock divider */ |
| | 37 | /* Values can range from 1-15 */ |
| | 38 | #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ |
| | 39 | |
| | 40 | /* |
| | 41 | * Memory Settings |
| | 42 | */ |
| | 43 | #define CONFIG_MEM_ADD_WDTH 11 |
| | 44 | #define CONFIG_MEM_SIZE 128 |
| | 45 | |
| | 46 | #define CONFIG_EBIU_SDRRC_VAL 0x268 |
| | 47 | #define CONFIG_EBIU_SDGCTL_VAL 0x911109 |
| | 48 | |
| | 49 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
| | 50 | #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 |
| | 51 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 |
| | 52 | |
| | 53 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| | 54 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
| | 55 | |
| | 56 | |
| | 57 | /* |
| | 58 | * Network Settings |
| | 59 | */ |
| | 60 | #define ADI_CMDS_NETWORK 1 |
| | 61 | #define CONFIG_SMC91111 1 |
| | 62 | #define CONFIG_SMC91111_BASE 0x20300300 |
| | 63 | #define SMC91111_EEPROM_INIT() \ |
| | 64 | do { \ |
| | 65 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
| | 66 | bfin_write_FIO_FLAG_C(PF1); \ |
| | 67 | bfin_write_FIO_FLAG_S(PF0); \ |
| | 68 | SSYNC(); \ |
| | 69 | } while (0) |
| | 70 | #define CONFIG_HOSTNAME bf533-stamp |
| | 71 | /* Uncomment next line to use fixed MAC address */ |
| | 72 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ |
| | 73 | |
| | 74 | |
| | 75 | /* I2C */ |
| | 76 | #define CONFIG_SYS_I2C |
| | 77 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
| | 78 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| | 79 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 |
| | 80 | /* |
| | 81 | * Software (bit-bang) I2C driver configuration |
| | 82 | */ |
| | 83 | #define PF_SCL PF3 |
| | 84 | #define PF_SDA PF2 |
| | 85 | #define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
| | 86 | #define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); \ |
| | 87 | *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
| | 88 | #define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); \ |
| | 89 | *pFIO_INEN |= PF_SDA; asm("ssync;") |
| | 90 | #define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \ |
| | 91 | asm("ssync;") |
| | 92 | #define I2C_SDA(bit) if (bit) { \ |
| | 93 | *pFIO_FLAG_S = PF_SDA; \ |
| | 94 | asm("ssync;"); \ |
| | 95 | } \ |
| | 96 | else { \ |
| | 97 | *pFIO_FLAG_C = PF_SDA; \ |
| | 98 | asm("ssync;"); \ |
| | 99 | } |
| | 100 | #define I2C_SCL(bit) if (bit) { \ |
| | 101 | *pFIO_FLAG_S = PF_SCL; \ |
| | 102 | asm("ssync;"); \ |
| | 103 | } \ |
| | 104 | else { \ |
| | 105 | *pFIO_FLAG_C = PF_SCL; \ |
| | 106 | asm("ssync;"); \ |
| | 107 | } |
| | 108 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| | 109 | |
| | 110 | |
| | 111 | /* |
| | 112 | * Flash Settings |
| | 113 | */ |
| | 114 | #define CONFIG_FLASH_CFI_DRIVER |
| | 115 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| | 116 | #define CONFIG_SYS_FLASH_CFI |
| | 117 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET |
| | 118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| | 119 | #define CONFIG_SYS_MAX_FLASH_SECT 67 |
| | 120 | |
| | 121 | /* |
| | 122 | * SPI Settings |
| | 123 | */ |
| | 124 | #define CONFIG_BFIN_SPI |
| | 125 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
| | 126 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
| | 127 | #define CONFIG_SPI_FLASH |
| | 128 | #define CONFIG_SPI_FLASH_ALL |
| | 129 | |
| | 130 | |
| | 131 | /* |
| | 132 | * Env Storage Settings |
| | 133 | */ |
| | 134 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
| | 135 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| | 136 | #define CONFIG_ENV_OFFSET 0x10000 |
| | 137 | #define CONFIG_ENV_SIZE 0x2000 |
| | 138 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| | 139 | #else |
| | 140 | #define CONFIG_ENV_IS_IN_FLASH |
| | 141 | #define CONFIG_ENV_OFFSET 0x4000 |
| | 142 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| | 143 | #define CONFIG_ENV_SIZE 0x2000 |
| | 144 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
| | 145 | #endif |
| | 146 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
| | 147 | #define ENV_IS_EMBEDDED |
| | 148 | #else |
| | 149 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
| | 150 | #endif |
| | 151 | #ifdef ENV_IS_EMBEDDED |
| | 152 | /* WARNING - the following is hand-optimized to fit within |
| | 153 | * the sector before the environment sector. If it throws |
| | 154 | * an error during compilation remove an object here to get |
| | 155 | * it linked after the configuration sector. |
| | 156 | */ |
| | 157 | # define LDS_BOARD_TEXT \ |
| | 158 | arch/blackfin/lib/libblackfin.o (.text*); \ |
| | 159 | arch/blackfin/cpu/libblackfin.o (.text*); \ |
| | 160 | . = DEFINED(env_offset) ? env_offset : .; \ |
| | 161 | common/env_embedded.o (.text*); |
| | 162 | #endif |
| | 163 | |
| | 164 | |
| | 165 | /* |
| | 166 | * I2C Settings |
| | 167 | */ |
| | 168 | #define CONFIG_SYS_I2C_SOFT |
| | 169 | #ifdef CONFIG_SYS_I2C_SOFT |
| | 170 | #define CONFIG_SYS_I2C |
| | 171 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
| | 172 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 |
| | 173 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| | 174 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| | 175 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 |
| | 176 | #endif |
| | 177 | |
| | 178 | /* |
| | 179 | * Compact Flash / IDE / ATA Settings |
| | 180 | */ |
| | 181 | |
| | 182 | /* Enabled below option for CF support */ |
| | 183 | /* #define CONFIG_STAMP_CF */ |
| | 184 | #if defined(CONFIG_STAMP_CF) |
| | 185 | #define CONFIG_MISC_INIT_R |
| | 186 | #define CONFIG_DOS_PARTITION 1 |
| | 187 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| | 188 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| | 189 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ |
| | 190 | |
| | 191 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| | 192 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) |
| | 193 | |
| | 194 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 |
| | 195 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| | 196 | |
| | 197 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
| | 198 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ |
| | 199 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ |
| | 200 | |
| | 201 | #define CONFIG_SYS_ATA_STRIDE 2 |
| | 202 | |
| | 203 | #undef CONFIG_EBIU_AMBCTL1_VAL |
| | 204 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 |
| | 205 | #endif |
| | 206 | |
| | 207 | |
| | 208 | /* |
| | 209 | * Misc Settings |
| | 210 | */ |
| | 211 | #define CONFIG_RTC_BFIN |
| | 212 | #define CONFIG_UART_CONSOLE 0 |
| | 213 | |
| | 214 | /* FLASH/ETHERNET uses the same async bank */ |
| | 215 | #define SHARED_RESOURCES 1 |
| | 216 | |
| | 217 | /* define to enable boot progress via leds */ |
| | 218 | /* #define CONFIG_SHOW_BOOT_PROGRESS */ |
| | 219 | |
| | 220 | /* define to enable run status via led */ |
| | 221 | /* #define CONFIG_STATUS_LED */ |
| | 222 | #ifdef CONFIG_STATUS_LED |
| | 223 | #define CONFIG_GPIO_LED |
| | 224 | #define CONFIG_BOARD_SPECIFIC_LED |
| | 225 | /* use LED0 to indicate booting/alive */ |
| | 226 | #define STATUS_LED_BOOT 0 |
| | 227 | #define STATUS_LED_BIT GPIO_PF2 |
| | 228 | #define STATUS_LED_STATE STATUS_LED_ON |
| | 229 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) |
| | 230 | /* use LED1 to indicate crash */ |
| | 231 | #define STATUS_LED_CRASH 1 |
| | 232 | #define STATUS_LED_BIT1 GPIO_PF3 |
| | 233 | #define STATUS_LED_STATE1 STATUS_LED_ON |
| | 234 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) |
| | 235 | /* #define STATUS_LED_BIT2 GPIO_PF4 */ |
| | 236 | #endif |
| | 237 | |
| | 238 | /* define to enable splash screen support */ |
| | 239 | /* #define CONFIG_VIDEO */ |
| | 240 | |
| | 241 | |
| | 242 | /* |
| | 243 | * Pull in common ADI header for remaining command/environment setup |
| | 244 | */ |
| | 245 | #include <configs/bfin_adi_common.h> |
| | 246 | |
| | 247 | #endif |
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