[people/ms/u-boot.git] / include / configs / dbau1x00.h

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file contains the configuration parameters for the dbau1x00 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_DBAU1X00		1
#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */

#ifdef CONFIG_DBAU1000
/* Also known as Merlot */
#define CONFIG_SOC_AU1000	1
#else
#ifdef CONFIG_DBAU1100
#define CONFIG_SOC_AU1100	1
#else
#ifdef CONFIG_DBAU1500
#define CONFIG_SOC_AU1500	1
#else
#ifdef CONFIG_DBAU1550
/* Cabernet */
#define CONFIG_SOC_AU1550	1
#else
#error "No valid board set"
#endif
#endif
#endif
#endif

/* valid baudrates */

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"addmisc=setenv bootargs ${bootargs} "				\
		"console=ttyS0,${baudrate} "				\
		"panic=1\0"						\
	"bootfile=/tftpboot/vmlinux.srec\0"				\
	"load=tftp 80500000 ${u-boot}\0"				\
	""

#ifdef CONFIG_DBAU1550
/* Boot from flash by default, revert to bootp */
#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
#else /* CONFIG_DBAU1550 */
#define CONFIG_BOOTCOMMAND	"bootp;bootm"
#endif /* CONFIG_DBAU1550 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#ifdef CONFIG_DBAU1550

#undef CONFIG_CMD_PCMCIA
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */

#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/

#define CONFIG_SYS_MALLOC_LEN		128*1024

#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024

#define CONFIG_SYS_MHZ			396

#if (CONFIG_SYS_MHZ % 12) != 0
#error "Invalid CPU frequency - must be multiple of 12!"
#endif

#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)

#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */

#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/

#define CONFIG_SYS_MEMTEST_START	0x80100000
#define CONFIG_SYS_MEMTEST_END		0x80800000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef CONFIG_DBAU1550

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */

#else /* CONFIG_DBAU1550 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */

#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */

#endif /* CONFIG_DBAU1550 */

#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}

#define CONFIG_SYS_FLASH_CFI           1
#define CONFIG_FLASH_CFI_DRIVER    1

#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)

#define CONFIG_SYS_INIT_SP_OFFSET	0x400000

/* We boot from this flash, selected with dip switch */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */

#define	CONFIG_ENV_IS_NOWHERE	1

/* Address and size of Primary Environment Sector	*/
#define CONFIG_ENV_ADDR		0xB0030000
#define CONFIG_ENV_SIZE		0x10000

#define CONFIG_FLASH_16BIT

#define CONFIG_NR_DRAM_BANKS	2

#ifdef CONFIG_DBAU1550
#define MEM_SIZE 192
#else
#define MEM_SIZE 64
#endif

#define CONFIG_MEMSIZE_IN_BYTES

#ifndef CONFIG_DBAU1550
/*---ATA PCMCIA ------------------------------------*/
#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
#define CONFIG_PCMCIA_SLOT_A

#define CONFIG_ATAPI 1

/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1

/* We only support one slot for now */
#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET     8

/* Offset for normal register accesses  */
#define CONFIG_SYS_ATA_REG_OFFSET      0

/* Offset for alternate registers       */
#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
#endif /* CONFIG_DBAU1550 */

#endif	/* __CONFIG_H */
Commit	Line	Data
	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	/*
	9	* This file contains the configuration parameters for the dbau1x00 board.
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#define CONFIG_DBAU1X00 1
	16	#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
	17
	18	#ifdef CONFIG_DBAU1000
	19	/* Also known as Merlot */
	20	#define CONFIG_SOC_AU1000 1
	21	#else
	22	#ifdef CONFIG_DBAU1100
	23	#define CONFIG_SOC_AU1100 1
	24	#else
	25	#ifdef CONFIG_DBAU1500
	26	#define CONFIG_SOC_AU1500 1
	27	#else
	28	#ifdef CONFIG_DBAU1550
	29	/* Cabernet */
	30	#define CONFIG_SOC_AU1550 1
	31	#else
	32	#error "No valid board set"
	33	#endif
	34	#endif
	35	#endif
	36	#endif
	37
	38	/* valid baudrates */
	39
	40	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	41	#undef CONFIG_BOOTARGS
	42
	43	#define CONFIG_EXTRA_ENV_SETTINGS \
	44	"addmisc=setenv bootargs ${bootargs} " \
	45	"console=ttyS0,${baudrate} " \
	46	"panic=1\0" \
	47	"bootfile=/tftpboot/vmlinux.srec\0" \
	48	"load=tftp 80500000 ${u-boot}\0" \
	49	""
	50
	51	#ifdef CONFIG_DBAU1550
	52	/* Boot from flash by default, revert to bootp */
	53	#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
	54	#else /* CONFIG_DBAU1550 */
	55	#define CONFIG_BOOTCOMMAND "bootp;bootm"
	56	#endif /* CONFIG_DBAU1550 */
	57
	58	/*
	59	* BOOTP options
	60	*/
	61	#define CONFIG_BOOTP_BOOTFILESIZE
	62	#define CONFIG_BOOTP_BOOTPATH
	63	#define CONFIG_BOOTP_GATEWAY
	64	#define CONFIG_BOOTP_HOSTNAME
	65
	66	/*
	67	* Command line configuration.
	68	*/
	69
	70	#ifdef CONFIG_DBAU1550
	71
	72	#undef CONFIG_CMD_PCMCIA
	73	#endif
	74
	75	/*
	76	* Miscellaneous configurable options
	77	*/
	78	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	79
	80	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	81	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	82	#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
	83
	84	#define CONFIG_SYS_MALLOC_LEN 128*1024
	85
	86	#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
	87
	88	#define CONFIG_SYS_MHZ 396
	89
	90	#if (CONFIG_SYS_MHZ % 12) != 0
	91	#error "Invalid CPU frequency - must be multiple of 12!"
	92	#endif
	93
	94	#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
	95
	96	#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
	97
	98	#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
	99
	100	#define CONFIG_SYS_MEMTEST_START 0x80100000
	101	#define CONFIG_SYS_MEMTEST_END 0x80800000
	102
	103	/*-----------------------------------------------------------------------
	104	* FLASH and environment organization
	105	*/
	106	#ifdef CONFIG_DBAU1550
	107
	108	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	109	#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
	110
	111	#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
	112	#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
	113
	114	#else /* CONFIG_DBAU1550 */
	115
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	117	#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
	118
	119	#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
	120	#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
	121
	122	#endif /* CONFIG_DBAU1550 */
	123
	124	#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
	125
	126	#define CONFIG_SYS_FLASH_CFI 1
	127	#define CONFIG_FLASH_CFI_DRIVER 1
	128
	129	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	130	#define CONFIG_SYS_MONITOR_LEN (192 << 10)
	131
	132	#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
	133
	134	/* We boot from this flash, selected with dip switch */
	135	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
	136
	137	/* timeout values are in ticks */
	138	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
	139	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
	140
	141	#define CONFIG_ENV_IS_NOWHERE 1
	142
	143	/* Address and size of Primary Environment Sector */
	144	#define CONFIG_ENV_ADDR 0xB0030000
	145	#define CONFIG_ENV_SIZE 0x10000
	146
	147	#define CONFIG_FLASH_16BIT
	148
	149	#define CONFIG_NR_DRAM_BANKS 2
	150
	151	#ifdef CONFIG_DBAU1550
	152	#define MEM_SIZE 192
	153	#else
	154	#define MEM_SIZE 64
	155	#endif
	156
	157	#define CONFIG_MEMSIZE_IN_BYTES
	158
	159	#ifndef CONFIG_DBAU1550
	160	/---ATA PCMCIA ------------------------------------/
	161	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
	162	#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
	163	#define CONFIG_PCMCIA_SLOT_A
	164
	165	#define CONFIG_ATAPI 1
	166
	167	/* We run CF in "true ide" mode or a harddrive via pcmcia */
	168	#define CONFIG_IDE_PCMCIA 1
	169
	170	/* We only support one slot for now */
	171	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	172	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	173
	174	#undef CONFIG_IDE_LED /* LED for ide not supported */
	175	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	176
	177	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	178
	179	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
	180
	181	/* Offset for data I/O */
	182	#define CONFIG_SYS_ATA_DATA_OFFSET 8
	183
	184	/* Offset for normal register accesses */
	185	#define CONFIG_SYS_ATA_REG_OFFSET 0
	186
	187	/* Offset for alternate registers */
	188	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
	189	#endif /* CONFIG_DBAU1550 */
	190
	191	#endif /* __CONFIG_H */