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1 | /* | |
2 | * Copyright 2017 NXP | |
3 | * Copyright 2015 Freescale Semiconductor | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __LS2_RDB_H | |
9 | #define __LS2_RDB_H | |
10 | ||
11 | #include "ls2080a_common.h" | |
12 | ||
13 | #undef CONFIG_CONS_INDEX | |
14 | #define CONFIG_CONS_INDEX 2 | |
15 | ||
16 | #ifdef CONFIG_FSL_QSPI | |
17 | #ifdef CONFIG_TARGET_LS2081ARDB | |
18 | #define CONFIG_QIXIS_I2C_ACCESS | |
19 | #endif | |
20 | #define CONFIG_SYS_I2C_EARLY_INIT | |
21 | #endif | |
22 | ||
23 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
24 | #define I2C_VOL_MONITOR_ADDR 0x38 | |
25 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
26 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
27 | ||
28 | #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" | |
29 | #ifndef CONFIG_SPL_BUILD | |
30 | #define CONFIG_VID | |
31 | #endif | |
32 | /* step the IR regulator in 5mV increments */ | |
33 | #define IR_VDD_STEP_DOWN 5 | |
34 | #define IR_VDD_STEP_UP 5 | |
35 | /* The lowest and highest voltage allowed for LS2080ARDB */ | |
36 | #define VDD_MV_MIN 819 | |
37 | #define VDD_MV_MAX 1212 | |
38 | ||
39 | #ifndef __ASSEMBLY__ | |
40 | unsigned long get_board_sys_clk(void); | |
41 | #endif | |
42 | ||
43 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
44 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
45 | #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) | |
46 | ||
47 | #define CONFIG_DDR_SPD | |
48 | #define CONFIG_DDR_ECC | |
49 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
50 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
51 | #define SPD_EEPROM_ADDRESS1 0x51 | |
52 | #define SPD_EEPROM_ADDRESS2 0x52 | |
53 | #define SPD_EEPROM_ADDRESS3 0x53 | |
54 | #define SPD_EEPROM_ADDRESS4 0x54 | |
55 | #define SPD_EEPROM_ADDRESS5 0x55 | |
56 | #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ | |
57 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 | |
58 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ | |
59 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
60 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
61 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR | |
62 | #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 | |
63 | #endif | |
64 | #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ | |
65 | ||
66 | /* SATA */ | |
67 | #define CONFIG_SCSI_AHCI_PLAT | |
68 | ||
69 | #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 | |
70 | #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 | |
71 | ||
72 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
73 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
74 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
75 | CONFIG_SYS_SCSI_MAX_LUN) | |
76 | ||
77 | #ifndef CONFIG_FSL_QSPI | |
78 | /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ | |
79 | ||
80 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
81 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
82 | #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) | |
83 | ||
84 | #define CONFIG_SYS_NOR0_CSPR \ | |
85 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
86 | CSPR_PORT_SIZE_16 | \ | |
87 | CSPR_MSEL_NOR | \ | |
88 | CSPR_V) | |
89 | #define CONFIG_SYS_NOR0_CSPR_EARLY \ | |
90 | (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ | |
91 | CSPR_PORT_SIZE_16 | \ | |
92 | CSPR_MSEL_NOR | \ | |
93 | CSPR_V) | |
94 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) | |
95 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
96 | FTIM0_NOR_TEADC(0x5) | \ | |
97 | FTIM0_NOR_TEAHC(0x5)) | |
98 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
99 | FTIM1_NOR_TRAD_NOR(0x1a) |\ | |
100 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
101 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
102 | FTIM2_NOR_TCH(0x4) | \ | |
103 | FTIM2_NOR_TWPH(0x0E) | \ | |
104 | FTIM2_NOR_TWP(0x1c)) | |
105 | #define CONFIG_SYS_NOR_FTIM3 0x04000000 | |
106 | #define CONFIG_SYS_IFC_CCR 0x01000000 | |
107 | ||
108 | #ifdef CONFIG_MTD_NOR_FLASH | |
109 | #define CONFIG_FLASH_CFI_DRIVER | |
110 | #define CONFIG_SYS_FLASH_CFI | |
111 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
112 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
113 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
114 | ||
115 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
116 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
117 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
118 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
119 | ||
120 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
121 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
122 | CONFIG_SYS_FLASH_BASE + 0x40000000} | |
123 | #endif | |
124 | ||
125 | #define CONFIG_NAND_FSL_IFC | |
126 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
127 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
128 | ||
129 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
130 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
131 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
132 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
133 | | CSPR_V) | |
134 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) | |
135 | ||
136 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
137 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
138 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
139 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
140 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
141 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
142 | | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ | |
143 | ||
144 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
145 | ||
146 | /* ONFI NAND Flash mode0 Timing Params */ | |
147 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ | |
148 | FTIM0_NAND_TWP(0x30) | \ | |
149 | FTIM0_NAND_TWCHT(0x0e) | \ | |
150 | FTIM0_NAND_TWH(0x14)) | |
151 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ | |
152 | FTIM1_NAND_TWBE(0xab) | \ | |
153 | FTIM1_NAND_TRR(0x1c) | \ | |
154 | FTIM1_NAND_TRP(0x30)) | |
155 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ | |
156 | FTIM2_NAND_TREH(0x14) | \ | |
157 | FTIM2_NAND_TWHRE(0x3c)) | |
158 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
159 | ||
160 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
161 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
162 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
163 | ||
164 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
165 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
166 | #define QIXIS_LBMAP_SWITCH 0x06 | |
167 | #define QIXIS_LBMAP_MASK 0x0f | |
168 | #define QIXIS_LBMAP_SHIFT 0 | |
169 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
170 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
171 | #define QIXIS_LBMAP_NAND 0x09 | |
172 | #define QIXIS_RST_CTL_RESET 0x31 | |
173 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
174 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
175 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
176 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
177 | #define QIXIS_RCW_SRC_NAND 0x119 | |
178 | #define QIXIS_RST_FORCE_MEM 0x01 | |
179 | ||
180 | #define CONFIG_SYS_CSPR3_EXT (0x0) | |
181 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | |
182 | | CSPR_PORT_SIZE_8 \ | |
183 | | CSPR_MSEL_GPCM \ | |
184 | | CSPR_V) | |
185 | #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
186 | | CSPR_PORT_SIZE_8 \ | |
187 | | CSPR_MSEL_GPCM \ | |
188 | | CSPR_V) | |
189 | ||
190 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
191 | #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) | |
192 | /* QIXIS Timing parameters for IFC CS3 */ | |
193 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
194 | FTIM0_GPCM_TEADC(0x0e) | \ | |
195 | FTIM0_GPCM_TEAHC(0x0e)) | |
196 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
197 | FTIM1_GPCM_TRAD(0x3f)) | |
198 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
199 | FTIM2_GPCM_TCH(0xf) | \ | |
200 | FTIM2_GPCM_TWP(0x3E)) | |
201 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
202 | ||
203 | #if defined(CONFIG_SPL) && defined(CONFIG_NAND) | |
204 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
205 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY | |
206 | #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR | |
207 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
208 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
209 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
210 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
211 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
212 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
213 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
214 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
215 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
216 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
217 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
218 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
219 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
220 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
221 | ||
222 | #define CONFIG_ENV_OFFSET (2048 * 1024) | |
223 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
224 | #define CONFIG_ENV_SIZE 0x2000 | |
225 | #define CONFIG_SPL_PAD_TO 0x80000 | |
226 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) | |
227 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) | |
228 | #else | |
229 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
230 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY | |
231 | #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR | |
232 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
233 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
234 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
235 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
236 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
237 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
238 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
239 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
240 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
241 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
242 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
243 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
244 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
245 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
246 | ||
247 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) | |
248 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
249 | #define CONFIG_ENV_SIZE 0x2000 | |
250 | #endif | |
251 | ||
252 | /* Debug Server firmware */ | |
253 | #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR | |
254 | #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL | |
255 | #endif | |
256 | #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 | |
257 | ||
258 | #ifdef CONFIG_TARGET_LS2081ARDB | |
259 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
260 | #define QIXIS_QMAP_MASK 0x07 | |
261 | #define QIXIS_QMAP_SHIFT 5 | |
262 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
263 | #define QIXIS_LBMAP_QSPI 0x00 | |
264 | #define QIXIS_RCW_SRC_QSPI 0x62 | |
265 | #define QIXIS_LBMAP_ALTBANK 0x20 | |
266 | #define QIXIS_RST_CTL_RESET 0x31 | |
267 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
268 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
269 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
270 | #define QIXIS_LBMAP_MASK 0x0f | |
271 | #define QIXIS_RST_CTL_RESET_EN 0x30 | |
272 | #endif | |
273 | ||
274 | /* | |
275 | * I2C | |
276 | */ | |
277 | #ifdef CONFIG_TARGET_LS2081ARDB | |
278 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
279 | #endif | |
280 | #define I2C_MUX_PCA_ADDR 0x75 | |
281 | #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ | |
282 | ||
283 | /* I2C bus multiplexer */ | |
284 | #define I2C_MUX_CH_DEFAULT 0x8 | |
285 | ||
286 | /* SPI */ | |
287 | #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) | |
288 | #define CONFIG_SPI_FLASH | |
289 | #ifdef CONFIG_FSL_DSPI | |
290 | #define CONFIG_SPI_FLASH_STMICRO | |
291 | #endif | |
292 | #ifdef CONFIG_FSL_QSPI | |
293 | #define CONFIG_SPI_FLASH_SPANSION | |
294 | #endif | |
295 | #define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ | |
296 | #define FSL_QSPI_FLASH_NUM 2 | |
297 | #endif | |
298 | ||
299 | /* | |
300 | * RTC configuration | |
301 | */ | |
302 | #define RTC | |
303 | #ifdef CONFIG_TARGET_LS2081ARDB | |
304 | #define CONFIG_RTC_PCF8563 1 | |
305 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 | |
306 | #else | |
307 | #define CONFIG_RTC_DS3231 1 | |
308 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
309 | #endif | |
310 | ||
311 | /* EEPROM */ | |
312 | #define CONFIG_ID_EEPROM | |
313 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
314 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
315 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
316 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
317 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
318 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
319 | ||
320 | #define CONFIG_FSL_MEMAC | |
321 | ||
322 | #ifdef CONFIG_PCI | |
323 | #define CONFIG_PCI_SCAN_SHOW | |
324 | #endif | |
325 | ||
326 | /* MMC */ | |
327 | #ifdef CONFIG_MMC | |
328 | #define CONFIG_FSL_ESDHC | |
329 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
330 | #endif | |
331 | ||
332 | #define CONFIG_MISC_INIT_R | |
333 | ||
334 | #undef CONFIG_CMDLINE_EDITING | |
335 | #include <config_distro_defaults.h> | |
336 | ||
337 | #define BOOT_TARGET_DEVICES(func) \ | |
338 | func(USB, usb, 0) \ | |
339 | func(MMC, mmc, 0) \ | |
340 | func(SCSI, scsi, 0) \ | |
341 | func(DHCP, dhcp, na) | |
342 | #include <config_distro_bootcmd.h> | |
343 | ||
344 | #ifdef CONFIG_QSPI_BOOT | |
345 | #define MC_INIT_CMD \ | |
346 | "mcinitcmd=env exists secureboot && " \ | |
347 | "esbc_validate 0x20700000 && " \ | |
348 | "esbc_validate 0x20740000;" \ | |
349 | "fsl_mc start mc 0x20a00000 0x20e00000 \0" | |
350 | #elif defined(CONFIG_SD_BOOT) | |
351 | #define MC_INIT_CMD \ | |
352 | "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ | |
353 | "mmc read 0x80100000 0x7000 0x800;" \ | |
354 | "env exists secureboot && " \ | |
355 | "mmc read 0x80700000 0x3800 0x10 && " \ | |
356 | "mmc read 0x80740000 0x3A00 0x10 && " \ | |
357 | "esbc_validate 0x80700000 && " \ | |
358 | "esbc_validate 0x80740000 ;" \ | |
359 | "fsl_mc start mc 0x80000000 0x80100000\0" \ | |
360 | "mcmemsize=0x70000000\0" | |
361 | #else | |
362 | #define MC_INIT_CMD \ | |
363 | "mcinitcmd=env exists secureboot && " \ | |
364 | "esbc_validate 0x580700000 && " \ | |
365 | "esbc_validate 0x580740000; " \ | |
366 | "fsl_mc start mc 0x580a00000 0x580e00000 \0" | |
367 | #endif | |
368 | ||
369 | /* Initial environment variables */ | |
370 | #undef CONFIG_EXTRA_ENV_SETTINGS | |
371 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
372 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
373 | "ramdisk_addr=0x800000\0" \ | |
374 | "ramdisk_size=0x2000000\0" \ | |
375 | "fdt_high=0xa0000000\0" \ | |
376 | "initrd_high=0xffffffffffffffff\0" \ | |
377 | "fdt_addr=0x64f00000\0" \ | |
378 | "kernel_addr=0x65000000\0" \ | |
379 | "kernel_start=0x1000000\0" \ | |
380 | "kernelheader_start=0x800000\0" \ | |
381 | "scriptaddr=0x80000000\0" \ | |
382 | "scripthdraddr=0x80080000\0" \ | |
383 | "fdtheader_addr_r=0x80100000\0" \ | |
384 | "kernelheader_addr_r=0x80200000\0" \ | |
385 | "kernelheader_addr=0x580800000\0" \ | |
386 | "kernel_addr_r=0x81000000\0" \ | |
387 | "kernelheader_size=0x40000\0" \ | |
388 | "fdt_addr_r=0x90000000\0" \ | |
389 | "load_addr=0xa0000000\0" \ | |
390 | "kernel_size=0x2800000\0" \ | |
391 | "kernel_addr_sd=0x8000\0" \ | |
392 | "kernel_size_sd=0x14000\0" \ | |
393 | "console=ttyAMA0,38400n8\0" \ | |
394 | "mcmemsize=0x70000000\0" \ | |
395 | "sd_bootcmd=echo Trying load from SD ..;" \ | |
396 | "mmcinfo; mmc read $load_addr " \ | |
397 | "$kernel_addr_sd $kernel_size_sd && " \ | |
398 | "bootm $load_addr#$board\0" \ | |
399 | MC_INIT_CMD \ | |
400 | BOOTENV \ | |
401 | "boot_scripts=ls2088ardb_boot.scr\0" \ | |
402 | "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ | |
403 | "scan_dev_for_boot_part=" \ | |
404 | "part list ${devtype} ${devnum} devplist; " \ | |
405 | "env exists devplist || setenv devplist 1; " \ | |
406 | "for distro_bootpart in ${devplist}; do " \ | |
407 | "if fstype ${devtype} " \ | |
408 | "${devnum}:${distro_bootpart} " \ | |
409 | "bootfstype; then " \ | |
410 | "run scan_dev_for_boot; " \ | |
411 | "fi; " \ | |
412 | "done\0" \ | |
413 | "scan_dev_for_boot=" \ | |
414 | "echo Scanning ${devtype} " \ | |
415 | "${devnum}:${distro_bootpart}...; " \ | |
416 | "for prefix in ${boot_prefixes}; do " \ | |
417 | "run scan_dev_for_scripts; " \ | |
418 | "done;\0" \ | |
419 | "boot_a_script=" \ | |
420 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
421 | "${scriptaddr} ${prefix}${script}; " \ | |
422 | "env exists secureboot && load ${devtype} " \ | |
423 | "${devnum}:${distro_bootpart} " \ | |
424 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
425 | "&& esbc_validate ${scripthdraddr};" \ | |
426 | "source ${scriptaddr}\0" \ | |
427 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
428 | "sf probe && sf read $load_addr " \ | |
429 | "$kernel_start $kernel_size ; env exists secureboot &&" \ | |
430 | "sf read $kernelheader_addr_r $kernelheader_start " \ | |
431 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
432 | " bootm $load_addr#$board\0" \ | |
433 | "nor_bootcmd=echo Trying load from nor..;" \ | |
434 | "cp.b $kernel_addr $load_addr " \ | |
435 | "$kernel_size ; env exists secureboot && " \ | |
436 | "cp.b $kernelheader_addr $kernelheader_addr_r " \ | |
437 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ | |
438 | "bootm $load_addr#$board\0" | |
439 | ||
440 | #undef CONFIG_BOOTCOMMAND | |
441 | #ifdef CONFIG_QSPI_BOOT | |
442 | /* Try to boot an on-QSPI kernel first, then do normal distro boot */ | |
443 | #define CONFIG_BOOTCOMMAND \ | |
444 | "env exists mcinitcmd && env exists secureboot "\ | |
445 | "&& esbc_validate 0x20780000; " \ | |
446 | "env exists mcinitcmd && " \ | |
447 | "fsl_mc lazyapply dpl 0x20d00000; " \ | |
448 | "run distro_bootcmd;env exists secureboot " \ | |
449 | " && esbc_halt;run qspi_bootcmd; " | |
450 | #elif defined(CONFIG_SD_BOOT) | |
451 | /* Try to boot an on-SD kernel first, then do normal distro boot */ | |
452 | #define CONFIG_BOOTCOMMAND \ | |
453 | "env exists mcinitcmd && env exists secureboot "\ | |
454 | "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ | |
455 | "&& esbc_validate $load_addr; " \ | |
456 | "env exists mcinitcmd && run mcinitcmd " \ | |
457 | "&& mmc read 0x88000000 0x6800 0x800 " \ | |
458 | "&& fsl_mc lazyapply dpl 0x88000000; " \ | |
459 | "run distro_bootcmd;env exists secureboot " \ | |
460 | "&& esbc_halt;run sd_bootcmd;" | |
461 | #else | |
462 | /* Try to boot an on-NOR kernel first, then do normal distro boot */ | |
463 | #define CONFIG_BOOTCOMMAND \ | |
464 | "env exists mcinitcmd && env exists secureboot "\ | |
465 | "&& esbc_validate 0x580780000; env exists mcinitcmd "\ | |
466 | "&& fsl_mc lazyapply dpl 0x580d00000;" \ | |
467 | "run distro_bootcmd; env exists secureboot " \ | |
468 | "&& esbc_halt; run nor_bootcmd;" | |
469 | #endif | |
470 | ||
471 | /* MAC/PHY configuration */ | |
472 | #ifdef CONFIG_FSL_MC_ENET | |
473 | #define CONFIG_PHYLIB_10G | |
474 | #define CONFIG_PHY_AQUANTIA | |
475 | #define CONFIG_PHY_CORTINA | |
476 | #define CONFIG_SYS_CORTINA_FW_IN_NOR | |
477 | #ifdef CONFIG_QSPI_BOOT | |
478 | #define CONFIG_CORTINA_FW_ADDR 0x20980000 | |
479 | #else | |
480 | #define CONFIG_CORTINA_FW_ADDR 0x580980000 | |
481 | #endif | |
482 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
483 | ||
484 | #define CORTINA_PHY_ADDR1 0x10 | |
485 | #define CORTINA_PHY_ADDR2 0x11 | |
486 | #define CORTINA_PHY_ADDR3 0x12 | |
487 | #define CORTINA_PHY_ADDR4 0x13 | |
488 | #define AQ_PHY_ADDR1 0x00 | |
489 | #define AQ_PHY_ADDR2 0x01 | |
490 | #define AQ_PHY_ADDR3 0x02 | |
491 | #define AQ_PHY_ADDR4 0x03 | |
492 | #define AQR405_IRQ_MASK 0x36 | |
493 | ||
494 | #define CONFIG_MII | |
495 | #define CONFIG_ETHPRIME "DPMAC1@xgmii" | |
496 | #define CONFIG_PHY_AQUANTIA | |
497 | #endif | |
498 | ||
499 | #include <asm/fsl_secure_boot.h> | |
500 | ||
501 | #endif /* __LS2_RDB_H */ |