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1 | /* | |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
16 | ||
17 | /* | |
18 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
19 | * 64 bytes before this address should be set aside for u-boot.img's | |
20 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
21 | * other needs. We use this rather than the inherited defines from | |
22 | * ti_armv7_common.h for backwards compatibility. | |
23 | */ | |
24 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
25 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
26 | #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ | |
27 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
28 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
29 | ||
30 | #include <configs/ti_omap3_common.h> | |
31 | ||
32 | /* | |
33 | * Display CPU and Board information | |
34 | */ | |
35 | #define CONFIG_DISPLAY_CPUINFO 1 | |
36 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
37 | ||
38 | #define CONFIG_MISC_INIT_R | |
39 | ||
40 | #define CONFIG_REVISION_TAG 1 | |
41 | #define CONFIG_ENV_OVERWRITE | |
42 | ||
43 | /* Status LED */ | |
44 | #define CONFIG_STATUS_LED 1 | |
45 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
46 | #define STATUS_LED_BIT 0x01 | |
47 | #define STATUS_LED_STATE STATUS_LED_ON | |
48 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
49 | #define STATUS_LED_BIT1 0x02 | |
50 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
51 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
52 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
53 | #define STATUS_LED_GREEN STATUS_LED_BIT1 | |
54 | ||
55 | /* Enable Multi Bus support for I2C */ | |
56 | #define CONFIG_I2C_MULTI_BUS 1 | |
57 | ||
58 | /* Probe all devices */ | |
59 | #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} | |
60 | ||
61 | /* USB */ | |
62 | #define CONFIG_USB_MUSB_GADGET | |
63 | #define CONFIG_USB_MUSB_OMAP2PLUS | |
64 | #define CONFIG_USB_MUSB_PIO_ONLY | |
65 | #define CONFIG_USB_GADGET_DUALSPEED | |
66 | #define CONFIG_TWL4030_USB 1 | |
67 | #define CONFIG_USB_ETHER | |
68 | #define CONFIG_USB_ETHER_RNDIS | |
69 | #define CONFIG_USB_GADGET | |
70 | #define CONFIG_USB_GADGET_VBUS_DRAW 0 | |
71 | #define CONFIG_USB_GADGET_DOWNLOAD | |
72 | #define CONFIG_G_DNL_VENDOR_NUM 0x0451 | |
73 | #define CONFIG_G_DNL_PRODUCT_NUM 0xd022 | |
74 | #define CONFIG_G_DNL_MANUFACTURER "TI" | |
75 | #define CONFIG_USB_FUNCTION_FASTBOOT | |
76 | #define CONFIG_CMD_FASTBOOT | |
77 | #define CONFIG_ANDROID_BOOT_IMAGE | |
78 | #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR | |
79 | #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 | |
80 | ||
81 | /* USB EHCI */ | |
82 | #define CONFIG_CMD_USB | |
83 | #define CONFIG_USB_EHCI | |
84 | ||
85 | #define CONFIG_USB_EHCI_OMAP | |
86 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 | |
87 | ||
88 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 | |
89 | #define CONFIG_USB_HOST_ETHER | |
90 | #define CONFIG_USB_ETHER_ASIX | |
91 | #define CONFIG_USB_ETHER_MCS7830 | |
92 | #define CONFIG_USB_ETHER_SMSC95XX | |
93 | ||
94 | /* GPIO banks */ | |
95 | #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ | |
96 | #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ | |
97 | ||
98 | /* commands to include */ | |
99 | #define CONFIG_CMD_ASKENV | |
100 | ||
101 | #define CONFIG_CMD_CACHE | |
102 | ||
103 | #define MTDIDS_DEFAULT "nand0=nand" | |
104 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
105 | "1920k(u-boot),128k(u-boot-env),"\ | |
106 | "4m(kernel),-(fs)" | |
107 | ||
108 | #define CONFIG_USB_STORAGE /* USB storage support */ | |
109 | #define CONFIG_CMD_NAND /* NAND support */ | |
110 | #define CONFIG_CMD_LED /* LED support */ | |
111 | #define CONFIG_CMD_GPIO /* Enable gpio command */ | |
112 | #define CONFIG_CMD_DHCP | |
113 | ||
114 | #define CONFIG_VIDEO_OMAP3 /* DSS Support */ | |
115 | ||
116 | /* | |
117 | * TWL4030 | |
118 | */ | |
119 | #define CONFIG_TWL4030_LED 1 | |
120 | ||
121 | /* | |
122 | * Board NAND Info. | |
123 | */ | |
124 | #define CONFIG_SYS_NAND_QUIET_TEST 1 | |
125 | #define CONFIG_NAND_OMAP_GPMC | |
126 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
127 | /* devices */ | |
128 | ||
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
130 | "loadaddr=0x80200000\0" \ | |
131 | "rdaddr=0x81000000\0" \ | |
132 | "fdt_high=0xffffffff\0" \ | |
133 | "fdtaddr=0x80f80000\0" \ | |
134 | "usbtty=cdc_acm\0" \ | |
135 | "bootfile=uImage\0" \ | |
136 | "ramdisk=ramdisk.gz\0" \ | |
137 | "bootdir=/boot\0" \ | |
138 | "bootpart=0:2\0" \ | |
139 | "console=ttyO2,115200n8\0" \ | |
140 | "mpurate=auto\0" \ | |
141 | "buddy=none\0" \ | |
142 | "optargs=\0" \ | |
143 | "camera=none\0" \ | |
144 | "vram=12M\0" \ | |
145 | "dvimode=640x480MR-16@60\0" \ | |
146 | "defaultdisplay=dvi\0" \ | |
147 | "mmcdev=0\0" \ | |
148 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
149 | "mmcrootfstype=ext3 rootwait\0" \ | |
150 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ | |
151 | "nandrootfstype=ubifs\0" \ | |
152 | "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ | |
153 | "ramrootfstype=ext2\0" \ | |
154 | "mmcargs=setenv bootargs console=${console} " \ | |
155 | "${optargs} " \ | |
156 | "mpurate=${mpurate} " \ | |
157 | "buddy=${buddy} "\ | |
158 | "camera=${camera} "\ | |
159 | "vram=${vram} " \ | |
160 | "omapfb.mode=dvi:${dvimode} " \ | |
161 | "omapdss.def_disp=${defaultdisplay} " \ | |
162 | "root=${mmcroot} " \ | |
163 | "rootfstype=${mmcrootfstype}\0" \ | |
164 | "nandargs=setenv bootargs console=${console} " \ | |
165 | "${optargs} " \ | |
166 | "mpurate=${mpurate} " \ | |
167 | "buddy=${buddy} "\ | |
168 | "camera=${camera} "\ | |
169 | "vram=${vram} " \ | |
170 | "omapfb.mode=dvi:${dvimode} " \ | |
171 | "omapdss.def_disp=${defaultdisplay} " \ | |
172 | "root=${nandroot} " \ | |
173 | "rootfstype=${nandrootfstype}\0" \ | |
174 | "findfdt=" \ | |
175 | "if test $beaglerev = AxBx; then " \ | |
176 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
177 | "if test $beaglerev = Cx; then " \ | |
178 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
179 | "if test $beaglerev = C4; then " \ | |
180 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
181 | "if test $beaglerev = xMAB; then " \ | |
182 | "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ | |
183 | "if test $beaglerev = xMC; then " \ | |
184 | "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ | |
185 | "if test $fdtfile = undefined; then " \ | |
186 | "echo WARNING: Could not determine device tree to use; fi; \0" \ | |
187 | "validatefdt=" \ | |
188 | "if test $beaglerev = xMAB; then " \ | |
189 | "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ | |
190 | "setenv fdtfile omap3-beagle-xm.dtb; " \ | |
191 | "fi; " \ | |
192 | "fi; \0" \ | |
193 | "bootenv=uEnv.txt\0" \ | |
194 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ | |
195 | "importbootenv=echo Importing environment from mmc ...; " \ | |
196 | "env import -t -r $loadaddr $filesize\0" \ | |
197 | "ramargs=setenv bootargs console=${console} " \ | |
198 | "${optargs} " \ | |
199 | "mpurate=${mpurate} " \ | |
200 | "buddy=${buddy} "\ | |
201 | "vram=${vram} " \ | |
202 | "omapfb.mode=dvi:${dvimode} " \ | |
203 | "omapdss.def_disp=${defaultdisplay} " \ | |
204 | "root=${ramroot} " \ | |
205 | "rootfstype=${ramrootfstype}\0" \ | |
206 | "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ | |
207 | "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ | |
208 | "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
209 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ | |
210 | "source ${loadaddr}\0" \ | |
211 | "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ | |
212 | "mmcboot=echo Booting from mmc ...; " \ | |
213 | "run mmcargs; " \ | |
214 | "bootm ${loadaddr}\0" \ | |
215 | "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ | |
216 | "run mmcargs; " \ | |
217 | "bootz ${loadaddr} - ${fdtaddr}\0" \ | |
218 | "nandboot=echo Booting from nand ...; " \ | |
219 | "run nandargs; " \ | |
220 | "nand read ${loadaddr} 280000 400000; " \ | |
221 | "bootm ${loadaddr}\0" \ | |
222 | "ramboot=echo Booting from ramdisk ...; " \ | |
223 | "run ramargs; " \ | |
224 | "bootm ${loadaddr}\0" \ | |
225 | "userbutton=if gpio input 173; then run userbutton_xm; " \ | |
226 | "else run userbutton_nonxm; fi;\0" \ | |
227 | "userbutton_xm=gpio input 4;\0" \ | |
228 | "userbutton_nonxm=gpio input 7;\0" | |
229 | /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ | |
230 | #define CONFIG_BOOTCOMMAND \ | |
231 | "run findfdt; " \ | |
232 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
233 | "if run userbutton; then " \ | |
234 | "setenv bootenv uEnv.txt;" \ | |
235 | "else " \ | |
236 | "setenv bootenv user.txt;" \ | |
237 | "fi;" \ | |
238 | "echo SD/MMC found on device ${mmcdev};" \ | |
239 | "if run loadbootenv; then " \ | |
240 | "echo Loaded environment from ${bootenv};" \ | |
241 | "run importbootenv;" \ | |
242 | "fi;" \ | |
243 | "if test -n $uenvcmd; then " \ | |
244 | "echo Running uenvcmd ...;" \ | |
245 | "run uenvcmd;" \ | |
246 | "fi;" \ | |
247 | "if run loadbootscript; then " \ | |
248 | "run bootscript; " \ | |
249 | "else " \ | |
250 | "if run loadimage; then " \ | |
251 | "run mmcboot;" \ | |
252 | "fi;" \ | |
253 | "fi; " \ | |
254 | "fi;" \ | |
255 | "run nandboot;" \ | |
256 | "setenv bootfile zImage;" \ | |
257 | "if run loadimage; then " \ | |
258 | "run loadfdt;" \ | |
259 | "run mmcbootz; " \ | |
260 | "fi; " \ | |
261 | ||
262 | /* | |
263 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
264 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
265 | * This rate is divided by a local divisor. | |
266 | */ | |
267 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
268 | ||
269 | /*----------------------------------------------------------------------- | |
270 | * FLASH and environment organization | |
271 | */ | |
272 | ||
273 | /* **** PISMO SUPPORT *** */ | |
274 | #if defined(CONFIG_CMD_NAND) | |
275 | #define CONFIG_SYS_FLASH_BASE NAND_BASE | |
276 | #endif | |
277 | ||
278 | /* Monitor at start of flash */ | |
279 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
280 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
281 | ||
282 | #define CONFIG_ENV_IS_IN_NAND 1 | |
283 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ | |
284 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
285 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
286 | ||
287 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
288 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
289 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
290 | ||
291 | #define CONFIG_OMAP3_SPI | |
292 | ||
293 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
294 | ||
295 | /* Defines for SPL */ | |
296 | #define CONFIG_SPL_OMAP3_ID_NAND | |
297 | ||
298 | /* NAND boot config */ | |
299 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT | |
300 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
301 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
302 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
303 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
304 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
305 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
306 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
307 | 10, 11, 12, 13} | |
308 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
309 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
310 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
311 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
312 | /* NAND: SPL falcon mode configs */ | |
313 | #ifdef CONFIG_SPL_OS_BOOT | |
314 | #define CONFIG_CMD_SPL_NAND_OFS 0x240000 | |
315 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 | |
316 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 | |
317 | #endif | |
318 | ||
319 | #endif /* __CONFIG_H */ |