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1 | #ifndef __CONFIG_H | |
2 | #define __CONFIG_H | |
3 | ||
4 | #define CONFIG_CPU_SH7751 1 | |
5 | #define CONFIG_CPU_SH_TYPE_R 1 | |
6 | #define CONFIG_R2DPLUS 1 | |
7 | #define __LITTLE_ENDIAN__ 1 | |
8 | ||
9 | #define CONFIG_DISPLAY_BOARDINFO | |
10 | ||
11 | /* | |
12 | * Command line configuration. | |
13 | */ | |
14 | #define CONFIG_CMD_PCI | |
15 | #define CONFIG_CMD_SH_ZIMAGEBOOT | |
16 | ||
17 | /* SCIF */ | |
18 | #define CONFIG_SCIF_CONSOLE 1 | |
19 | #define CONFIG_CONS_SCIF1 1 | |
20 | ||
21 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
22 | #define CONFIG_ENV_OVERWRITE 1 | |
23 | ||
24 | /* SDRAM */ | |
25 | #define CONFIG_SYS_SDRAM_BASE 0x8C000000 | |
26 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
27 | ||
28 | #define CONFIG_SYS_TEXT_BASE 0x8FE00000 | |
29 | #define CONFIG_SYS_LONGHELP | |
30 | #define CONFIG_SYS_CBSIZE 256 | |
31 | #define CONFIG_SYS_PBSIZE 256 | |
32 | #define CONFIG_SYS_MAXARGS 16 | |
33 | #define CONFIG_SYS_BARGSIZE 512 | |
34 | ||
35 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
36 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) | |
37 | ||
38 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) | |
39 | /* Address of u-boot image in Flash */ | |
40 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
41 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
42 | /* Size of DRAM reserved for malloc() use */ | |
43 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) | |
44 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) | |
45 | ||
46 | /* | |
47 | * NOR Flash ( Spantion S29GL256P ) | |
48 | */ | |
49 | #define CONFIG_SYS_FLASH_CFI | |
50 | #define CONFIG_FLASH_CFI_DRIVER | |
51 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
52 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) | |
53 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
54 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
55 | ||
56 | #define CONFIG_ENV_IS_IN_FLASH | |
57 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
58 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
59 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
60 | ||
61 | /* | |
62 | * SuperH Clock setting | |
63 | */ | |
64 | #define CONFIG_SYS_CLK_FREQ 60000000 | |
65 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
66 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
67 | #define CONFIG_SYS_TMU_CLK_DIV 4 | |
68 | #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ | |
69 | ||
70 | /* | |
71 | * IDE support | |
72 | */ | |
73 | #define CONFIG_IDE_RESET 1 | |
74 | #define CONFIG_SYS_PIO_MODE 1 | |
75 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
76 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
77 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
78 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
79 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
80 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
81 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
82 | #define CONFIG_IDE_SWAP_IO | |
83 | ||
84 | /* | |
85 | * SuperH PCI Bridge Configration | |
86 | */ | |
87 | #define CONFIG_SH4_PCI | |
88 | #define CONFIG_SH7751_PCI | |
89 | #define CONFIG_PCI_SCAN_SHOW 1 | |
90 | #define __mem_pci | |
91 | ||
92 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
93 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
94 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
95 | #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ | |
96 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
97 | #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ | |
98 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
99 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE | |
100 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
101 | ||
102 | #endif /* __CONFIG_H */ |