| | 1 | /* |
| | 2 | * (C) Copyright 2006-2008 |
| | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| | 4 | * |
| | 5 | * (C) Copyright 2006 |
| | 6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
| | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
| | 8 | * |
| | 9 | * This program is free software; you can redistribute it and/or |
| | 10 | * modify it under the terms of the GNU General Public License as |
| | 11 | * published by the Free Software Foundation; either version 2 of |
| | 12 | * the License, or (at your option) any later version. |
| | 13 | * |
| | 14 | * This program is distributed in the hope that it will be useful, |
| | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 17 | * GNU General Public License for more details. |
| | 18 | * |
| | 19 | * You should have received a copy of the GNU General Public License |
| | 20 | * along with this program; if not, write to the Free Software |
| | 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| | 22 | * MA 02111-1307 USA |
| | 23 | */ |
| | 24 | |
| | 25 | /* |
| | 26 | * sequoia.h - configuration for Sequoia & Rainier boards |
| | 27 | */ |
| | 28 | #ifndef __CONFIG_H |
| | 29 | #define __CONFIG_H |
| | 30 | |
| | 31 | /* |
| | 32 | * High Level Configuration Options |
| | 33 | */ |
| | 34 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
| | 35 | #ifndef CONFIG_RAINIER |
| | 36 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
| | 37 | #define CONFIG_HOSTNAME sequoia |
| | 38 | #else |
| | 39 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ |
| | 40 | #define CONFIG_HOSTNAME rainier |
| | 41 | #endif |
| | 42 | #define CONFIG_440 1 /* ... PPC440 family */ |
| | 43 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| | 44 | |
| | 45 | /* |
| | 46 | * Include common defines/options for all AMCC eval boards |
| | 47 | */ |
| | 48 | #include "amcc-common.h" |
| | 49 | |
| | 50 | /* Detect Sequoia PLL input clock automatically via CPLD bit */ |
| | 51 | #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \ |
| | 52 | 33333333 : 33000000) |
| | 53 | |
| | 54 | /* |
| | 55 | * Define this if you want support for video console with radeon 9200 pci card |
| | 56 | * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case |
| | 57 | */ |
| | 58 | #undef CONFIG_VIDEO |
| | 59 | |
| | 60 | #ifdef CONFIG_VIDEO |
| | 61 | /* |
| | 62 | * 44x dcache supported is working now on sequoia, but we don't enable |
| | 63 | * it yet since it needs further testing |
| | 64 | */ |
| | 65 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
| | 66 | #endif |
| | 67 | |
| | 68 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| | 69 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
| | 70 | |
| | 71 | /* |
| | 72 | * Base addresses -- Note these are effective addresses where the actual |
| | 73 | * resources get mapped (not physical addresses). |
| | 74 | */ |
| | 75 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003 |
| | 76 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
| | 77 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
| | 78 | #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */ |
| | 79 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ |
| | 80 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE |
| | 81 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ |
| | 82 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
| | 83 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 |
| | 84 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 |
| | 85 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 |
| | 86 | |
| | 87 | /* Don't change either of these */ |
| | 88 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
| | 89 | |
| | 90 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
| | 91 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 |
| | 92 | #define CONFIG_SYS_USB_HOST 0xe0000400 |
| | 93 | #define CONFIG_SYS_BCSR_BASE 0xc0000000 |
| | 94 | |
| | 95 | /* |
| | 96 | * Initial RAM & stack pointer |
| | 97 | */ |
| | 98 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
| | 99 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
| | 100 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) |
| | 101 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ |
| | 102 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| | 103 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR |
| | 104 | |
| | 105 | /* |
| | 106 | * Serial Port |
| | 107 | */ |
| | 108 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
| | 109 | /* define this if you want console on UART1 */ |
| | 110 | #undef CONFIG_UART1_CONSOLE |
| | 111 | |
| | 112 | /* |
| | 113 | * Environment |
| | 114 | */ |
| | 115 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| | 116 | #define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ |
| | 117 | #define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ |
| | 118 | #elif defined(CONFIG_SYS_RAMBOOT) |
| | 119 | #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ |
| | 120 | #define CONFIG_ENV_SIZE (8 << 10) |
| | 121 | /* |
| | 122 | * In RAM-booting version, we have no environment storage. So we need to |
| | 123 | * provide at least preliminary MAC addresses for the 4xx EMAC driver to |
| | 124 | * register the interfaces. Those two addresses are generated via the |
| | 125 | * tools/gen_eth_addr tool and should only be used in a closed laboratory |
| | 126 | * environment. |
| | 127 | */ |
| | 128 | #define CONFIG_ETHADDR 4a:56:49:22:3e:43 |
| | 129 | #define CONFIG_ETH1ADDR 02:93:53:d5:06:98 |
| | 130 | #else |
| | 131 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */ |
| | 132 | #endif |
| | 133 | |
| | 134 | #if defined(CONFIG_CMD_FLASH) |
| | 135 | /* |
| | 136 | * FLASH related |
| | 137 | */ |
| | 138 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| | 139 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| | 140 | |
| | 141 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| | 142 | |
| | 143 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| | 144 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
| | 145 | |
| | 146 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| | 147 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| | 148 | |
| | 149 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| | 150 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ |
| | 151 | |
| | 152 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| | 153 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
| | 154 | |
| | 155 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| | 156 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| | 157 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
| | 158 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| | 159 | |
| | 160 | /* Address and size of Redundant Environment Sector */ |
| | 161 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| | 162 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
| | 163 | #endif |
| | 164 | #endif /* CONFIG_CMD_FLASH */ |
| | 165 | |
| | 166 | /* |
| | 167 | * IPL (Initial Program Loader, integrated inside CPU) |
| | 168 | * Will load first 4k from NAND (SPL) into cache and execute it from there. |
| | 169 | * |
| | 170 | * SPL (Secondary Program Loader) |
| | 171 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL |
| | 172 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM |
| | 173 | * controller and the NAND controller so that the special U-Boot image can be |
| | 174 | * loaded from NAND to SDRAM. |
| | 175 | * |
| | 176 | * NUB (NAND U-Boot) |
| | 177 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started |
| | 178 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. |
| | 179 | * |
| | 180 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is |
| | 181 | * set up. While still running from cache, I experienced problems accessing |
| | 182 | * the NAND controller. sr - 2006-08-25 |
| | 183 | */ |
| | 184 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
| | 185 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ |
| | 186 | #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ |
| | 187 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ |
| | 188 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ |
| | 189 | /* this addr */ |
| | 190 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) |
| | 191 | |
| | 192 | /* |
| | 193 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) |
| | 194 | */ |
| | 195 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
| | 196 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ |
| | 197 | |
| | 198 | /* |
| | 199 | * Now the NAND chip has to be defined (no autodetection used!) |
| | 200 | */ |
| | 201 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
| | 202 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ |
| | 203 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ |
| | 204 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ |
| | 205 | #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ |
| | 206 | |
| | 207 | #define CONFIG_SYS_NAND_ECCSIZE 256 |
| | 208 | #define CONFIG_SYS_NAND_ECCBYTES 3 |
| | 209 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) |
| | 210 | #define CONFIG_SYS_NAND_OOBSIZE 16 |
| | 211 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) |
| | 212 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} |
| | 213 | |
| | 214 | #ifdef CONFIG_ENV_IS_IN_NAND |
| | 215 | /* |
| | 216 | * For NAND booting the environment is embedded in the U-Boot image. Please take |
| | 217 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. |
| | 218 | */ |
| | 219 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| | 220 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) |
| | 221 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| | 222 | #endif |
| | 223 | |
| | 224 | /* |
| | 225 | * DDR SDRAM |
| | 226 | */ |
| | 227 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
| | 228 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| | 229 | !defined(CONFIG_SYS_RAMBOOT) |
| | 230 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
| | 231 | #endif |
| | 232 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
| | 233 | /* 440EPx errata CHIP 11 */ |
| | 234 | |
| | 235 | /* |
| | 236 | * I2C |
| | 237 | */ |
| | 238 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| | 239 | |
| | 240 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| | 241 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
| | 242 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| | 243 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| | 244 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
| | 245 | |
| | 246 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
| | 247 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
| | 248 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ |
| | 249 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
| | 250 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| | 251 | #define CONFIG_SYS_DTT_LOW_TEMP -30 |
| | 252 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
| | 253 | |
| | 254 | /* |
| | 255 | * Default environment variables |
| | 256 | */ |
| | 257 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| | 258 | CONFIG_AMCC_DEF_ENV \ |
| | 259 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
| | 260 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ |
| | 261 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
| | 262 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ |
| | 263 | "kernel_addr=FC000000\0" \ |
| | 264 | "ramdisk_addr=FC180000\0" \ |
| | 265 | "" |
| | 266 | |
| | 267 | #define CONFIG_M88E1111_PHY 1 |
| | 268 | #define CONFIG_IBM_EMAC4_V4 1 |
| | 269 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
| | 270 | |
| | 271 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
| | 272 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| | 273 | |
| | 274 | #define CONFIG_HAS_ETH0 |
| | 275 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| | 276 | #define CONFIG_PHY1_ADDR 1 |
| | 277 | |
| | 278 | /* USB */ |
| | 279 | #ifdef CONFIG_440EPX |
| | 280 | #define CONFIG_USB_OHCI_NEW |
| | 281 | #define CONFIG_USB_STORAGE |
| | 282 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
| | 283 | |
| | 284 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
| | 285 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
| | 286 | #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST |
| | 287 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" |
| | 288 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| | 289 | |
| | 290 | /* Comment this out to enable USB 1.1 device */ |
| | 291 | #define USB_2_0_DEVICE |
| | 292 | |
| | 293 | #endif /* CONFIG_440EPX */ |
| | 294 | |
| | 295 | /* Partitions */ |
| | 296 | #define CONFIG_MAC_PARTITION |
| | 297 | #define CONFIG_DOS_PARTITION |
| | 298 | #define CONFIG_ISO_PARTITION |
| | 299 | |
| | 300 | /* |
| | 301 | * Commands additional to the ones defined in amcc-common.h |
| | 302 | */ |
| | 303 | #define CONFIG_CMD_DTT |
| | 304 | #define CONFIG_CMD_FAT |
| | 305 | #define CONFIG_CMD_NAND |
| | 306 | #define CONFIG_CMD_PCI |
| | 307 | #define CONFIG_CMD_SDRAM |
| | 308 | |
| | 309 | #ifdef CONFIG_440EPX |
| | 310 | #define CONFIG_CMD_USB |
| | 311 | #endif |
| | 312 | |
| | 313 | #ifndef CONFIG_RAINIER |
| | 314 | #define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU |
| | 315 | #else |
| | 316 | #define CONFIG_SYS_POST_FPU_ON 0 |
| | 317 | #endif |
| | 318 | |
| | 319 | /* |
| | 320 | * Don't run the memory POST on the NAND-booting version. It will |
| | 321 | * overwrite part of the U-Boot image which is already loaded from NAND |
| | 322 | * to SDRAM. |
| | 323 | */ |
| | 324 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) |
| | 325 | #define CONFIG_SYS_POST_MEMORY_ON 0 |
| | 326 | #else |
| | 327 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY |
| | 328 | #endif |
| | 329 | |
| | 330 | /* POST support */ |
| | 331 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
| | 332 | CONFIG_SYS_POST_CPU | \ |
| | 333 | CONFIG_SYS_POST_ETHER | \ |
| | 334 | CONFIG_SYS_POST_FPU_ON | \ |
| | 335 | CONFIG_SYS_POST_I2C | \ |
| | 336 | CONFIG_SYS_POST_MEMORY_ON | \ |
| | 337 | CONFIG_SYS_POST_SPR | \ |
| | 338 | CONFIG_SYS_POST_UART) |
| | 339 | |
| | 340 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
| | 341 | #define CONFIG_LOGBUFFER |
| | 342 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
| | 343 | |
| | 344 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
| | 345 | |
| | 346 | #define CONFIG_SUPPORT_VFAT |
| | 347 | |
| | 348 | /* |
| | 349 | * PCI stuff |
| | 350 | */ |
| | 351 | /* General PCI */ |
| | 352 | #define CONFIG_PCI /* include pci support */ |
| | 353 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| | 354 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
| | 355 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| | 356 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ |
| | 357 | /* CONFIG_SYS_PCI_MEMBASE */ |
| | 358 | /* Board-specific PCI */ |
| | 359 | #define CONFIG_SYS_PCI_TARGET_INIT |
| | 360 | #define CONFIG_SYS_PCI_MASTER_INIT |
| | 361 | |
| | 362 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| | 363 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
| | 364 | |
| | 365 | /* |
| | 366 | * External Bus Controller (EBC) Setup |
| | 367 | */ |
| | 368 | |
| | 369 | /* |
| | 370 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting |
| | 371 | */ |
| | 372 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| | 373 | !defined(CONFIG_SYS_RAMBOOT) |
| | 374 | #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ |
| | 375 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| | 376 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
| | 377 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) |
| | 378 | |
| | 379 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
| | 380 | #define CONFIG_SYS_EBC_PB3AP 0x018003c0 |
| | 381 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000) |
| | 382 | #else |
| | 383 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
| | 384 | /* Memory Bank 3 (NOR-FLASH) initialization */ |
| | 385 | #define CONFIG_SYS_EBC_PB3AP 0x03017200 |
| | 386 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000) |
| | 387 | |
| | 388 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
| | 389 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
| | 390 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) |
| | 391 | #endif |
| | 392 | |
| | 393 | /* Memory Bank 2 (CPLD) initialization */ |
| | 394 | #define CONFIG_SYS_EBC_PB2AP 0x24814580 |
| | 395 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000) |
| | 396 | |
| | 397 | #define CONFIG_SYS_BCSR5_PCI66EN 0x80 |
| | 398 | |
| | 399 | /* |
| | 400 | * NAND FLASH |
| | 401 | */ |
| | 402 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| | 403 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
| | 404 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
| | 405 | |
| | 406 | /* |
| | 407 | * PPC440 GPIO Configuration |
| | 408 | */ |
| | 409 | /* test-only: take GPIO init from pcs440ep ???? in config file */ |
| | 410 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| | 411 | { \ |
| | 412 | /* GPIO Core 0 */ \ |
| | 413 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ |
| | 414 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ |
| | 415 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ |
| | 416 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ |
| | 417 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ |
| | 418 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ |
| | 419 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ |
| | 420 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ |
| | 421 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ |
| | 422 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ |
| | 423 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ |
| | 424 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ |
| | 425 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ |
| | 426 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ |
| | 427 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \ |
| | 428 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ |
| | 429 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ |
| | 430 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ |
| | 431 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ |
| | 432 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ |
| | 433 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ |
| | 434 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ |
| | 435 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ |
| | 436 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ |
| | 437 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ |
| | 438 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ |
| | 439 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ |
| | 440 | {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ |
| | 441 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \ |
| | 442 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ |
| | 443 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ |
| | 444 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ |
| | 445 | }, \ |
| | 446 | { \ |
| | 447 | /* GPIO Core 1 */ \ |
| | 448 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ |
| | 449 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ |
| | 450 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ |
| | 451 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ |
| | 452 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \ |
| | 453 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ |
| | 454 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \ |
| | 455 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \ |
| | 456 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ |
| | 457 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ |
| | 458 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ |
| | 459 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ |
| | 460 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ |
| | 461 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ |
| | 462 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ |
| | 463 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ |
| | 464 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ |
| | 465 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ |
| | 466 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
| | 467 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
| | 468 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ |
| | 469 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
| | 470 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
| | 471 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ |
| | 472 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ |
| | 473 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ |
| | 474 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
| | 475 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
| | 476 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ |
| | 477 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ |
| | 478 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ |
| | 479 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ |
| | 480 | } \ |
| | 481 | } |
| | 482 | |
| | 483 | #ifdef CONFIG_VIDEO |
| | 484 | #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ |
| | 485 | #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ |
| | 486 | #define VIDEO_IO_OFFSET 0xe8000000 |
| | 487 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| | 488 | #define CONFIG_VIDEO_SW_CURSOR |
| | 489 | #define CONFIG_VIDEO_LOGO |
| | 490 | #define CONFIG_CFB_CONSOLE |
| | 491 | #define CONFIG_SPLASH_SCREEN |
| | 492 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| | 493 | #define CONFIG_CMD_BMP |
| | 494 | #endif |
| | 495 | |
| | 496 | #endif /* __CONFIG_H */ |
projects / people / ms / u-boot.git / blame_incremental