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1 | /* | |
2 | * (C) Copyright 2003 Embedded Edge, LLC | |
3 | * Dan Malek <dan@embeddededge.com> | |
4 | * Copied from ADS85xx. | |
5 | * Updates for Silicon Tx GP3 8560 board. | |
6 | * | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* mpc8560ads board configuration file */ | |
30 | /* please refer to doc/README.mpc85xx for more info */ | |
31 | /* make sure you change the MAC address and other network params first, | |
32 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | /* High Level Configuration Options */ | |
39 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
40 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
41 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
42 | #define CONFIG_CPM2 1 /* has CPM2 */ | |
43 | #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ | |
44 | #define CONFIG_MPC8560 1 | |
45 | ||
46 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
47 | ||
48 | #undef CONFIG_PCI /* pci ethernet support */ | |
49 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ | |
50 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ | |
51 | #define CONFIG_ENV_OVERWRITE | |
52 | ||
53 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
54 | ||
55 | /* sysclk for MPC85xx | |
56 | */ | |
57 | ||
58 | #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ | |
59 | ||
60 | /* Blinkin' LEDs for Robert :-) | |
61 | */ | |
62 | #define CONFIG_SHOW_ACTIVITY 1 | |
63 | ||
64 | /* | |
65 | * These can be toggled for performance analysis, otherwise use default. | |
66 | */ | |
67 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
68 | #define CONFIG_BTB /* toggle branch predition */ | |
69 | ||
70 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
71 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ | |
72 | ||
73 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ | |
74 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
75 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
76 | ||
77 | ||
78 | /* Localbus SDRAM is an option, not all boards have it. | |
79 | * This address, however, is used to configure a 256M local bus | |
80 | * window that includes the Config latch below. | |
81 | */ | |
82 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
83 | #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ | |
84 | ||
85 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ | |
86 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
87 | ||
88 | #define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ | |
89 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
90 | #define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ | |
91 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
92 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ | |
93 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
94 | ||
95 | /* The configuration latch is Chip Select 1. | |
96 | * It's an 8-bit latch in the lower 8 bits of the word. | |
97 | */ | |
98 | #define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ | |
99 | #define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ | |
100 | #define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ | |
101 | ||
102 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
103 | ||
104 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
105 | #define CONFIG_SYS_RAMBOOT | |
106 | #else | |
107 | #undef CONFIG_SYS_RAMBOOT | |
108 | #endif | |
109 | ||
110 | #ifdef CONFIG_SYS_RAMBOOT | |
111 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ | |
112 | #endif | |
113 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 | |
114 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
115 | ||
116 | /* DDR Setup */ | |
117 | #define CONFIG_FSL_DDR1 | |
118 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
119 | #define CONFIG_DDR_SPD | |
120 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
121 | ||
122 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
123 | #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ | |
124 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
125 | ||
126 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
127 | ||
128 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
129 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
130 | ||
131 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
132 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
133 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
134 | ||
135 | /* I2C addresses of SPD EEPROMs */ | |
136 | #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ | |
137 | ||
138 | #undef CONFIG_CLOCKS_IN_MHZ | |
139 | ||
140 | /* local bus definitions */ | |
141 | #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ | |
142 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
143 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ | |
144 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
145 | #define CONFIG_SYS_LBC_LSRT 0x20000000 | |
146 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
147 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 | |
148 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 | |
149 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 | |
150 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 | |
151 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 | |
152 | ||
153 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
154 | #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ | |
155 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ | |
156 | ||
157 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
158 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
159 | ||
160 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
161 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
162 | ||
163 | /* Serial Port */ | |
164 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
165 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
166 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
167 | ||
168 | #define CONFIG_BAUDRATE 38400 | |
169 | ||
170 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
171 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
172 | ||
173 | /* Use the HUSH parser */ | |
174 | #define CONFIG_SYS_HUSH_PARSER | |
175 | #ifdef CONFIG_SYS_HUSH_PARSER | |
176 | #endif | |
177 | ||
178 | /* | |
179 | * I2C | |
180 | */ | |
181 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
182 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
183 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
184 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
185 | #if 0 | |
186 | #define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ | |
187 | #else | |
188 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ | |
189 | #undef CONFIG_SYS_I2C_NOPROBES | |
190 | #endif | |
191 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
192 | ||
193 | /* RapdIO Map configuration, mapped 1:1. | |
194 | */ | |
195 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 | |
196 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE | |
197 | #define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ | |
198 | ||
199 | /* Standard 8560 PCI addressing, mapped 1:1. | |
200 | */ | |
201 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 | |
202 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
203 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
204 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
205 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
206 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ | |
207 | ||
208 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ | |
209 | ||
210 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
211 | ||
212 | #undef CONFIG_EEPRO100 | |
213 | #undef CONFIG_TULIP | |
214 | ||
215 | #if !defined(CONFIG_PCI_PNP) | |
216 | #define PCI_ENET0_IOADDR 0xe0000000 | |
217 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
218 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
219 | #endif | |
220 | ||
221 | #undef CONFIG_PCI_SCAN_SHOW | |
222 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
223 | ||
224 | #endif /* CONFIG_PCI */ | |
225 | ||
226 | #if defined(CONFIG_TSEC_ENET) | |
227 | ||
228 | #define CONFIG_MII 1 /* MII PHY management */ | |
229 | ||
230 | #define CONFIG_TSEC1 1 | |
231 | #define CONFIG_TSEC1_NAME "TSEC0" | |
232 | #define CONFIG_TSEC2 1 | |
233 | #define CONFIG_TSEC2_NAME "TSEC1" | |
234 | ||
235 | #define TSEC1_PHY_ADDR 2 | |
236 | #define TSEC2_PHY_ADDR 4 | |
237 | #define TSEC1_PHYIDX 0 | |
238 | #define TSEC2_PHYIDX 0 | |
239 | #define TSEC1_FLAGS TSEC_GIGABIT | |
240 | #define TSEC2_FLAGS TSEC_GIGABIT | |
241 | #define CONFIG_ETHPRIME "TSEC0" | |
242 | ||
243 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ | |
244 | ||
245 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ | |
246 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
247 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
248 | ||
249 | #if (CONFIG_ETHER_INDEX == 2) | |
250 | /* | |
251 | * - Rx-CLK is CLK13 | |
252 | * - Tx-CLK is CLK14 | |
253 | * - Select bus for bd/buffers | |
254 | * - Full duplex | |
255 | */ | |
256 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
257 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
258 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
259 | #if 0 | |
260 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
261 | #else | |
262 | #define CONFIG_SYS_FCC_PSMR 0 | |
263 | #endif | |
264 | #define FETH2_RST 0x01 | |
265 | #elif (CONFIG_ETHER_INDEX == 3) | |
266 | /* need more definitions here for FE3 */ | |
267 | #define FETH3_RST 0x80 | |
268 | #endif /* CONFIG_ETHER_INDEX */ | |
269 | ||
270 | /* MDIO is done through the TSEC0 control. | |
271 | */ | |
272 | #define CONFIG_MII /* MII PHY management */ | |
273 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
274 | ||
275 | #endif | |
276 | ||
277 | /* Environment */ | |
278 | /* We use the top boot sector flash, so we have some 16K sectors for env | |
279 | */ | |
280 | #ifndef CONFIG_SYS_RAMBOOT | |
281 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
282 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) | |
283 | #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ | |
284 | #define CONFIG_ENV_SIZE 0x2000 | |
285 | #else | |
286 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ | |
287 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
288 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
289 | #define CONFIG_ENV_SIZE 0x2000 | |
290 | #endif | |
291 | ||
292 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" | |
293 | #define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" | |
294 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ | |
295 | ||
296 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
297 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
298 | ||
299 | /* | |
300 | * BOOTP options | |
301 | */ | |
302 | #define CONFIG_BOOTP_BOOTFILESIZE | |
303 | #define CONFIG_BOOTP_BOOTPATH | |
304 | #define CONFIG_BOOTP_GATEWAY | |
305 | #define CONFIG_BOOTP_HOSTNAME | |
306 | ||
307 | ||
308 | /* | |
309 | * Command line configuration. | |
310 | */ | |
311 | #include <config_cmd_default.h> | |
312 | ||
313 | #define CONFIG_CMD_PING | |
314 | #define CONFIG_CMD_I2C | |
315 | #define CONFIG_CMD_REGINFO | |
316 | ||
317 | #if defined(CONFIG_SYS_RAMBOOT) | |
318 | #undef CONFIG_CMD_SAVEENV | |
319 | #undef CONFIG_CMD_LOADS | |
320 | #else | |
321 | #define CONFIG_CMD_ELF | |
322 | #endif | |
323 | ||
324 | #if defined(CONFIG_PCI) | |
325 | #define CONFIG_CMD_PCI | |
326 | #endif | |
327 | ||
328 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
329 | #define CONFIG_CMD_MII | |
330 | #endif | |
331 | ||
332 | ||
333 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
334 | ||
335 | /* | |
336 | * Miscellaneous configurable options | |
337 | */ | |
338 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
339 | #define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */ | |
340 | #if defined(CONFIG_CMD_KGDB) | |
341 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
342 | #else | |
343 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
344 | #endif | |
345 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
346 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
347 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
348 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
349 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
350 | ||
351 | /* | |
352 | * For booting Linux, the board info and command line data | |
353 | * have to be in the first 8 MB of memory, since this is | |
354 | * the maximum mapped by the Linux kernel during initialization. | |
355 | */ | |
356 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
357 | ||
358 | #if defined(CONFIG_CMD_KGDB) | |
359 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
360 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
361 | #endif | |
362 | ||
363 | /*Note: change below for your network setting!!! */ | |
364 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
365 | #define CONFIG_HAS_ETH0 | |
366 | #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a | |
367 | #define CONFIG_HAS_ETH1 | |
368 | #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b | |
369 | #define CONFIG_HAS_ETH2 | |
370 | #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c | |
371 | #endif | |
372 | ||
373 | #define CONFIG_SERVERIP 192.168.85.1 | |
374 | #define CONFIG_IPADDR 192.168.85.60 | |
375 | #define CONFIG_GATEWAYIP 192.168.85.1 | |
376 | #define CONFIG_NETMASK 255.255.255.0 | |
377 | #define CONFIG_HOSTNAME STX_GP3 | |
378 | #define CONFIG_ROOTPATH "/gppproot" | |
379 | #define CONFIG_BOOTFILE "uImage" | |
380 | #define CONFIG_LOADADDR 0x1000000 | |
381 | ||
382 | #endif /* __CONFIG_H */ |