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1 | /* | |
2 | * (C) Copyright 2006-2008 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ | |
37 | #define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */ | |
38 | #define CONFIG_TQM8xxL 1 | |
39 | ||
40 | #define CONFIG_SYS_TEXT_BASE 0x40000000 | |
41 | ||
42 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
43 | #define CONFIG_SYS_SMC_RXBUFLEN 128 | |
44 | #define CONFIG_SYS_MAXIDLE 10 | |
45 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
46 | ||
47 | #define CONFIG_BOOTCOUNT_LIMIT | |
48 | ||
49 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
50 | ||
51 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
52 | ||
53 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" | |
54 | ||
55 | #undef CONFIG_BOOTARGS | |
56 | ||
57 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
58 | "netdev=eth0\0" \ | |
59 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
60 | "nfsroot=${serverip}:${rootpath}\0" \ | |
61 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
62 | "addip=setenv bootargs ${bootargs} " \ | |
63 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
64 | ":${hostname}:${netdev}:off panic=1\0" \ | |
65 | "flash_nfs=run nfsargs addip;" \ | |
66 | "bootm ${kernel_addr}\0" \ | |
67 | "flash_self=run ramargs addip;" \ | |
68 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
69 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
70 | "rootpath=/opt/eldk/ppc_8xx\0" \ | |
71 | "hostname=virtlab2\0" \ | |
72 | "bootfile=virtlab2/uImage\0" \ | |
73 | "fdt_addr=40040000\0" \ | |
74 | "kernel_addr=40060000\0" \ | |
75 | "ramdisk_addr=40200000\0" \ | |
76 | "u-boot=virtlab2/u-image.bin\0" \ | |
77 | "load=tftp 200000 ${u-boot}\0" \ | |
78 | "update=prot off 40000000 +${filesize};" \ | |
79 | "era 40000000 +${filesize};" \ | |
80 | "cp.b 200000 40000000 ${filesize};" \ | |
81 | "sete filesize;save\0" \ | |
82 | "" | |
83 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
84 | ||
85 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
86 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
87 | ||
88 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
89 | ||
90 | #if defined(CONFIG_LCD) | |
91 | # undef CONFIG_STATUS_LED /* disturbs display */ | |
92 | #else | |
93 | # define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
94 | #endif /* CONFIG_LCD */ | |
95 | ||
96 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
97 | ||
98 | /* | |
99 | * BOOTP options | |
100 | */ | |
101 | #define CONFIG_BOOTP_SUBNETMASK | |
102 | #define CONFIG_BOOTP_GATEWAY | |
103 | #define CONFIG_BOOTP_HOSTNAME | |
104 | #define CONFIG_BOOTP_BOOTPATH | |
105 | #define CONFIG_BOOTP_BOOTFILESIZE | |
106 | ||
107 | ||
108 | #define CONFIG_MAC_PARTITION | |
109 | #define CONFIG_DOS_PARTITION | |
110 | ||
111 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
112 | ||
113 | ||
114 | /* | |
115 | * Command line configuration. | |
116 | */ | |
117 | #include <config_cmd_default.h> | |
118 | ||
119 | #define CONFIG_CMD_ASKENV | |
120 | #define CONFIG_CMD_DATE | |
121 | #define CONFIG_CMD_DHCP | |
122 | #define CONFIG_CMD_EXT2 | |
123 | #define CONFIG_CMD_IDE | |
124 | #define CONFIG_CMD_JFFS2 | |
125 | #define CONFIG_CMD_NFS | |
126 | #define CONFIG_CMD_SNTP | |
127 | ||
128 | #if defined(CONFIG_SPLASH_SCREEN) | |
129 | #define CONFIG_CMD_BMP | |
130 | #endif | |
131 | ||
132 | ||
133 | #define CONFIG_NETCONSOLE | |
134 | ||
135 | /* | |
136 | * Miscellaneous configurable options | |
137 | */ | |
138 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
139 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
140 | ||
141 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
142 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ | |
143 | ||
144 | #if defined(CONFIG_CMD_KGDB) | |
145 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
146 | #else | |
147 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
148 | #endif | |
149 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
150 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
151 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
152 | ||
153 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ | |
154 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
155 | ||
156 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
157 | ||
158 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
159 | ||
160 | /* | |
161 | * Low Level Configuration Settings | |
162 | * (address mappings, register initial values, etc.) | |
163 | * You should know what you are doing if you make changes here. | |
164 | */ | |
165 | /*----------------------------------------------------------------------- | |
166 | * Internal Memory Mapped Register | |
167 | */ | |
168 | #define CONFIG_SYS_IMMR 0xFFF00000 | |
169 | ||
170 | /*----------------------------------------------------------------------- | |
171 | * Definitions for initial stack pointer and data area (in DPRAM) | |
172 | */ | |
173 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
174 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ | |
175 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
176 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
177 | ||
178 | /*----------------------------------------------------------------------- | |
179 | * Start addresses for the final memory configuration | |
180 | * (Set up by the startup code) | |
181 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
182 | */ | |
183 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
184 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
185 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
186 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
187 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
188 | ||
189 | /* | |
190 | * For booting Linux, the board info and command line data | |
191 | * have to be in the first 8 MB of memory, since this is | |
192 | * the maximum mapped by the Linux kernel during initialization. | |
193 | */ | |
194 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
195 | ||
196 | /*----------------------------------------------------------------------- | |
197 | * FLASH organization | |
198 | */ | |
199 | ||
200 | /* use CFI flash driver */ | |
201 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ | |
202 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
203 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } | |
204 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
205 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
206 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
207 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
208 | ||
209 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
210 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ | |
211 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
212 | ||
213 | /* Address and size of Redundant Environment Sector */ | |
214 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) | |
215 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
216 | ||
217 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ | |
218 | ||
219 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ | |
220 | ||
221 | /*----------------------------------------------------------------------- | |
222 | * Dynamic MTD partition support | |
223 | */ | |
224 | #define CONFIG_CMD_MTDPARTS | |
225 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
226 | #define CONFIG_FLASH_CFI_MTD | |
227 | #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" | |
228 | ||
229 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ | |
230 | "128k(dtb)," \ | |
231 | "1664k(kernel)," \ | |
232 | "2m(rootfs)," \ | |
233 | "4m(data)" | |
234 | ||
235 | /*----------------------------------------------------------------------- | |
236 | * Hardware Information Block | |
237 | */ | |
238 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ | |
239 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
240 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
241 | ||
242 | /*----------------------------------------------------------------------- | |
243 | * Cache Configuration | |
244 | */ | |
245 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
246 | #if defined(CONFIG_CMD_KGDB) | |
247 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
248 | #endif | |
249 | ||
250 | /*----------------------------------------------------------------------- | |
251 | * SYPCR - System Protection Control 11-9 | |
252 | * SYPCR can only be written once after reset! | |
253 | *----------------------------------------------------------------------- | |
254 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
255 | */ | |
256 | #if defined(CONFIG_WATCHDOG) | |
257 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
258 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
259 | #else | |
260 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
261 | #endif | |
262 | ||
263 | /*----------------------------------------------------------------------- | |
264 | * SIUMCR - SIU Module Configuration 11-6 | |
265 | *----------------------------------------------------------------------- | |
266 | * PCMCIA config., multi-function pin tri-state | |
267 | */ | |
268 | #ifndef CONFIG_CAN_DRIVER | |
269 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
270 | #else /* we must activate GPL5 in the SIUMCR for CAN */ | |
271 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) | |
272 | #endif /* CONFIG_CAN_DRIVER */ | |
273 | ||
274 | /*----------------------------------------------------------------------- | |
275 | * TBSCR - Time Base Status and Control 11-26 | |
276 | *----------------------------------------------------------------------- | |
277 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
278 | */ | |
279 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
280 | ||
281 | /*----------------------------------------------------------------------- | |
282 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
283 | *----------------------------------------------------------------------- | |
284 | */ | |
285 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
286 | ||
287 | /*----------------------------------------------------------------------- | |
288 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
289 | *----------------------------------------------------------------------- | |
290 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
291 | */ | |
292 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
296 | *----------------------------------------------------------------------- | |
297 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
298 | * interrupt status bit | |
299 | */ | |
300 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) | |
301 | ||
302 | /*----------------------------------------------------------------------- | |
303 | * SCCR - System Clock and reset Control Register 15-27 | |
304 | *----------------------------------------------------------------------- | |
305 | * Set clock output, timebase and RTC source and divider, | |
306 | * power management and some other internal clocks | |
307 | */ | |
308 | #define SCCR_MASK SCCR_EBDF11 | |
309 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
310 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
311 | SCCR_DFALCD00) | |
312 | ||
313 | /*----------------------------------------------------------------------- | |
314 | * PCMCIA stuff | |
315 | *----------------------------------------------------------------------- | |
316 | * | |
317 | */ | |
318 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) | |
319 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
320 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
321 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
322 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
323 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
324 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
325 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
326 | ||
327 | /*----------------------------------------------------------------------- | |
328 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
329 | *----------------------------------------------------------------------- | |
330 | */ | |
331 | ||
332 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ | |
333 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
334 | ||
335 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
336 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
337 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
338 | ||
339 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
340 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
341 | ||
342 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
343 | ||
344 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR | |
345 | ||
346 | /* Offset for data I/O */ | |
347 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
348 | ||
349 | /* Offset for normal register accesses */ | |
350 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) | |
351 | ||
352 | /* Offset for alternate registers */ | |
353 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 | |
354 | ||
355 | /*----------------------------------------------------------------------- | |
356 | * | |
357 | *----------------------------------------------------------------------- | |
358 | * | |
359 | */ | |
360 | #define CONFIG_SYS_DER 0 | |
361 | ||
362 | /* | |
363 | * Init Memory Controller: | |
364 | * | |
365 | * BR0/1 and OR0/1 (FLASH) | |
366 | */ | |
367 | ||
368 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
369 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
370 | ||
371 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
372 | * restrict access enough to keep SRAM working (if any) | |
373 | * but not too much to meddle with FLASH accesses | |
374 | */ | |
375 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ | |
376 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
377 | ||
378 | /* | |
379 | * FLASH timing: | |
380 | */ | |
381 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ | |
382 | OR_SCY_3_CLK | OR_EHTR | OR_BI) | |
383 | ||
384 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
385 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
386 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
387 | ||
388 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP | |
389 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
390 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
391 | ||
392 | /* | |
393 | * BR2/3 and OR2/3 (SDRAM) | |
394 | * | |
395 | */ | |
396 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
397 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
398 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
399 | ||
400 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
401 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 | |
402 | ||
403 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) | |
404 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
405 | ||
406 | #ifndef CONFIG_CAN_DRIVER | |
407 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
408 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
409 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ | |
410 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ | |
411 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
412 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
413 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
414 | BR_PS_8 | BR_MS_UPMB | BR_V ) | |
415 | #endif /* CONFIG_CAN_DRIVER */ | |
416 | ||
417 | /* | |
418 | * Memory Periodic Timer Prescaler | |
419 | * | |
420 | * The Divider for PTA (refresh timer) configuration is based on an | |
421 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
422 | * the number of chip selects (NCS) and the actually needed refresh | |
423 | * rate is done by setting MPTPR. | |
424 | * | |
425 | * PTA is calculated from | |
426 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
427 | * | |
428 | * gclk CPU clock (not bus clock!) | |
429 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
430 | * | |
431 | * 4096 Rows from SDRAM example configuration | |
432 | * 1000 factor s -> ms | |
433 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
434 | * 4 Number of refresh cycles per period | |
435 | * 64 Refresh cycle in ms per number of rows | |
436 | * -------------------------------------------- | |
437 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
438 | * | |
439 | * 50 MHz => 50.000.000 / Divider = 98 | |
440 | * 66 Mhz => 66.000.000 / Divider = 129 | |
441 | * 80 Mhz => 80.000.000 / Divider = 156 | |
442 | */ | |
443 | ||
444 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) | |
445 | #define CONFIG_SYS_MAMR_PTA 98 | |
446 | ||
447 | /* | |
448 | * For 16 MBit, refresh rates could be 31.3 us | |
449 | * (= 64 ms / 2K = 125 / quad bursts). | |
450 | * For a simpler initialization, 15.6 us is used instead. | |
451 | * | |
452 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
453 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
454 | */ | |
455 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
456 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
457 | ||
458 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
459 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
460 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
461 | ||
462 | /* | |
463 | * MAMR settings for SDRAM | |
464 | */ | |
465 | ||
466 | /* 8 column SDRAM */ | |
467 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
468 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
469 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
470 | /* 9 column SDRAM */ | |
471 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
472 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
473 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
474 | ||
475 | /* Map peripheral control registers on CS4 */ | |
476 | #define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000 | |
477 | #define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
478 | #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \ | |
479 | OR_SCY_2_CLK) | |
480 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) | |
481 | #define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) | |
482 | ||
483 | /* pass open firmware flat tree */ | |
484 | #define CONFIG_OF_LIBFDT 1 | |
485 | #define CONFIG_OF_BOARD_SETUP 1 | |
486 | #define CONFIG_HWCONFIG 1 | |
487 | ||
488 | #endif /* __CONFIG_H */ |