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Merge tag 'pm-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[thirdparty/linux.git] / include / linux / pci.h
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
26#include <linux/args.h>
27#include <linux/mod_devicetable.h>
28
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/list.h>
33#include <linux/compiler.h>
34#include <linux/errno.h>
35#include <linux/kobject.h>
36#include <linux/atomic.h>
37#include <linux/device.h>
38#include <linux/interrupt.h>
39#include <linux/io.h>
40#include <linux/resource_ext.h>
41#include <linux/msi_api.h>
42#include <uapi/linux/pci.h>
43
44#include <linux/pci_ids.h>
45
46#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53/* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54#define PCI_NUM_RESET_METHODS 8
55
56#define PCI_RESET_PROBE true
57#define PCI_RESET_DO_RESET false
58
59/*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75/* pci_slot represents a physical slot */
76struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82};
83
84static inline const char *pci_slot_name(const struct pci_slot *slot)
85{
86 return kobject_name(&slot->kobj);
87}
88
89/* File state for mmap()s on /proc/bus/pci/X/Y */
90enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93};
94
95/* For PCI devices, the region numbers are assigned this way: */
96enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105#ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108#endif
109
110/* PCI-to-PCI (P2P) bridge windows */
111#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115/* CardBus bridge windows */
116#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121/* Total number of bridge resources for P2P and CardBus */
122#define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134};
135
136/**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153};
154
155/* The number of legacy PCI INTx interrupts */
156#define PCI_NUM_INTX 4
157
158/*
159 * Reading from a device that doesn't respond typically returns ~0. A
160 * successful read from a device may also return ~0, so you need additional
161 * information to reliably identify errors.
162 */
163#define PCI_ERROR_RESPONSE (~0ULL)
164#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
165#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
166
167/*
168 * pci_power_t values must match the bits in the Capabilities PME_Support
169 * and Control/Status PowerState fields in the Power Management capability.
170 */
171typedef int __bitwise pci_power_t;
172
173#define PCI_D0 ((pci_power_t __force) 0)
174#define PCI_D1 ((pci_power_t __force) 1)
175#define PCI_D2 ((pci_power_t __force) 2)
176#define PCI_D3hot ((pci_power_t __force) 3)
177#define PCI_D3cold ((pci_power_t __force) 4)
178#define PCI_UNKNOWN ((pci_power_t __force) 5)
179#define PCI_POWER_ERROR ((pci_power_t __force) -1)
180
181/* Remember to update this when the list above changes! */
182extern const char *pci_power_names[];
183
184static inline const char *pci_power_name(pci_power_t state)
185{
186 return pci_power_names[1 + (__force int) state];
187}
188
189/**
190 * typedef pci_channel_state_t
191 *
192 * The pci_channel state describes connectivity between the CPU and
193 * the PCI device. If some PCI bus between here and the PCI device
194 * has crashed or locked up, this info is reflected here.
195 */
196typedef unsigned int __bitwise pci_channel_state_t;
197
198enum {
199 /* I/O channel is in normal state */
200 pci_channel_io_normal = (__force pci_channel_state_t) 1,
201
202 /* I/O to channel is blocked */
203 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
204
205 /* PCI card is dead */
206 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
207};
208
209typedef unsigned int __bitwise pcie_reset_state_t;
210
211enum pcie_reset_state {
212 /* Reset is NOT asserted (Use to deassert reset) */
213 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
214
215 /* Use #PERST to reset PCIe device */
216 pcie_warm_reset = (__force pcie_reset_state_t) 2,
217
218 /* Use PCIe Hot Reset to reset device */
219 pcie_hot_reset = (__force pcie_reset_state_t) 3
220};
221
222typedef unsigned short __bitwise pci_dev_flags_t;
223enum pci_dev_flags {
224 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
225 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
226 /* Device configuration is irrevocably lost if disabled into D3 */
227 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
228 /* Provide indication device is assigned by a Virtual Machine Manager */
229 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
230 /* Flag for quirk use to store if quirk-specific ACS is enabled */
231 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
232 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
233 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
234 /* Do not use bus resets for device */
235 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
236 /* Do not use PM reset even if device advertises NoSoftRst- */
237 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
238 /* Get VPD from function 0 VPD */
239 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
240 /* A non-root bridge where translation occurs, stop alias search here */
241 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
242 /* Do not use FLR even if device advertises PCI_AF_CAP */
243 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
244 /* Don't use Relaxed Ordering for TLPs directed at this device */
245 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
246 /* Device does honor MSI masking despite saying otherwise */
247 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
248 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
249 PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13),
250};
251
252enum pci_irq_reroute_variant {
253 INTEL_IRQ_REROUTE_VARIANT = 1,
254 MAX_IRQ_REROUTE_VARIANTS = 3
255};
256
257typedef unsigned short __bitwise pci_bus_flags_t;
258enum pci_bus_flags {
259 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
260 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
261 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
262 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
263};
264
265/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
266enum pcie_link_width {
267 PCIE_LNK_WIDTH_RESRV = 0x00,
268 PCIE_LNK_X1 = 0x01,
269 PCIE_LNK_X2 = 0x02,
270 PCIE_LNK_X4 = 0x04,
271 PCIE_LNK_X8 = 0x08,
272 PCIE_LNK_X12 = 0x0c,
273 PCIE_LNK_X16 = 0x10,
274 PCIE_LNK_X32 = 0x20,
275 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
276};
277
278/* See matching string table in pci_speed_string() */
279enum pci_bus_speed {
280 PCI_SPEED_33MHz = 0x00,
281 PCI_SPEED_66MHz = 0x01,
282 PCI_SPEED_66MHz_PCIX = 0x02,
283 PCI_SPEED_100MHz_PCIX = 0x03,
284 PCI_SPEED_133MHz_PCIX = 0x04,
285 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
286 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
287 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
288 PCI_SPEED_66MHz_PCIX_266 = 0x09,
289 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
290 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
291 AGP_UNKNOWN = 0x0c,
292 AGP_1X = 0x0d,
293 AGP_2X = 0x0e,
294 AGP_4X = 0x0f,
295 AGP_8X = 0x10,
296 PCI_SPEED_66MHz_PCIX_533 = 0x11,
297 PCI_SPEED_100MHz_PCIX_533 = 0x12,
298 PCI_SPEED_133MHz_PCIX_533 = 0x13,
299 PCIE_SPEED_2_5GT = 0x14,
300 PCIE_SPEED_5_0GT = 0x15,
301 PCIE_SPEED_8_0GT = 0x16,
302 PCIE_SPEED_16_0GT = 0x17,
303 PCIE_SPEED_32_0GT = 0x18,
304 PCIE_SPEED_64_0GT = 0x19,
305 PCI_SPEED_UNKNOWN = 0xff,
306};
307
308enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
309enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
310
311struct pci_vpd {
312 struct mutex lock;
313 unsigned int len;
314 u8 cap;
315};
316
317struct irq_affinity;
318struct pcie_bwctrl_data;
319struct pcie_link_state;
320struct pci_sriov;
321struct pci_p2pdma;
322struct rcec_ea;
323
324/* struct pci_dev - describes a PCI device
325 *
326 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at
327 * LSB). 0 when the supported speeds cannot be
328 * determined (e.g., for Root Complex Integrated
329 * Endpoints without the relevant Capability
330 * Registers).
331 */
332struct pci_dev {
333 struct list_head bus_list; /* Node in per-bus list */
334 struct pci_bus *bus; /* Bus this device is on */
335 struct pci_bus *subordinate; /* Bus this device bridges to */
336
337 void *sysdata; /* Hook for sys-specific extension */
338 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
339 struct pci_slot *slot; /* Physical slot this device is in */
340
341 unsigned int devfn; /* Encoded device & function index */
342 unsigned short vendor;
343 unsigned short device;
344 unsigned short subsystem_vendor;
345 unsigned short subsystem_device;
346 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
347 u8 revision; /* PCI revision, low byte of class word */
348 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
349#ifdef CONFIG_PCIEAER
350 u16 aer_cap; /* AER capability offset */
351 struct aer_info *aer_info; /* AER info for this device */
352#endif
353#ifdef CONFIG_PCIEPORTBUS
354 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
355 struct pci_dev *rcec; /* Associated RCEC device */
356#endif
357 u32 devcap; /* PCIe Device Capabilities */
358 u16 rebar_cap; /* Resizable BAR capability offset */
359 u8 pcie_cap; /* PCIe capability offset */
360 u8 msi_cap; /* MSI capability offset */
361 u8 msix_cap; /* MSI-X capability offset */
362 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
363 u8 rom_base_reg; /* Config register controlling ROM */
364 u8 pin; /* Interrupt pin this device uses */
365 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
366 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
367
368 struct pci_driver *driver; /* Driver bound to this device */
369 u64 dma_mask; /* Mask of the bits of bus address this
370 device implements. Normally this is
371 0xffffffff. You only need to change
372 this if your device has broken DMA
373 or supports 64-bit transfers. */
374
375 struct device_dma_parameters dma_parms;
376
377 pci_power_t current_state; /* Current operating state. In ACPI,
378 this is D0-D3, D0 being fully
379 functional, and D3 being off. */
380 u8 pm_cap; /* PM capability offset */
381 unsigned int pme_support:5; /* Bitmask of states from which PME#
382 can be generated */
383 unsigned int pme_poll:1; /* Poll device's PME status bit */
384 unsigned int pinned:1; /* Whether this dev is pinned */
385 unsigned int config_rrs_sv:1; /* Config RRS software visibility */
386 unsigned int imm_ready:1; /* Supports Immediate Readiness */
387 unsigned int d1_support:1; /* Low power state D1 is supported */
388 unsigned int d2_support:1; /* Low power state D2 is supported */
389 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
390 unsigned int no_d3cold:1; /* D3cold is forbidden */
391 unsigned int bridge_d3:1; /* Allow D3 for bridge */
392 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
393 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
394 decoding during BAR sizing */
395 unsigned int wakeup_prepared:1;
396 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
397 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
398 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
399 controlled exclusively by
400 user sysfs */
401 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
402 bit manually */
403 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
404 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
405
406 u16 l1ss; /* L1SS Capability pointer */
407#ifdef CONFIG_PCIEASPM
408 struct pcie_link_state *link_state; /* ASPM link state */
409 unsigned int ltr_path:1; /* Latency Tolerance Reporting
410 supported from root to here */
411#endif
412 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
413 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */
414
415 pci_channel_state_t error_state; /* Current connectivity state */
416 struct device dev; /* Generic device interface */
417
418 int cfg_size; /* Size of config space */
419
420 /*
421 * Instead of touching interrupt line and base address registers
422 * directly, use the values stored here. They might be different!
423 */
424 unsigned int irq;
425 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
426 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */
427
428 unsigned int transparent:1; /* Subtractive decode bridge */
429 unsigned int io_window:1; /* Bridge has I/O window */
430 unsigned int pref_window:1; /* Bridge has pref mem window */
431 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
432 unsigned int multifunction:1; /* Multi-function device */
433
434 unsigned int is_busmaster:1; /* Is busmaster */
435 unsigned int no_msi:1; /* May not use MSI */
436 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
437 unsigned int block_cfg_access:1; /* Config space access blocked */
438 unsigned int broken_parity_status:1; /* Generates false positive parity */
439 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
440 unsigned int msi_enabled:1;
441 unsigned int msix_enabled:1;
442 unsigned int ari_enabled:1; /* ARI forwarding */
443 unsigned int ats_enabled:1; /* Address Translation Svc */
444 unsigned int pasid_enabled:1; /* Process Address Space ID */
445 unsigned int pri_enabled:1; /* Page Request Interface */
446 unsigned int tph_enabled:1; /* TLP Processing Hints */
447 unsigned int is_managed:1; /* Managed via devres */
448 unsigned int is_msi_managed:1; /* MSI release via devres installed */
449 unsigned int needs_freset:1; /* Requires fundamental reset */
450 unsigned int state_saved:1;
451 unsigned int is_physfn:1;
452 unsigned int is_virtfn:1;
453 unsigned int is_hotplug_bridge:1;
454 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
455 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
456 /*
457 * Devices marked being untrusted are the ones that can potentially
458 * execute DMA attacks and similar. They are typically connected
459 * through external ports such as Thunderbolt but not limited to
460 * that. When an IOMMU is enabled they should be getting full
461 * mappings to make sure they cannot access arbitrary memory.
462 */
463 unsigned int untrusted:1;
464 /*
465 * Info from the platform, e.g., ACPI or device tree, may mark a
466 * device as "external-facing". An external-facing device is
467 * itself internal but devices downstream from it are external.
468 */
469 unsigned int external_facing:1;
470 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
471 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
472 unsigned int irq_managed:1;
473 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
474 unsigned int is_probed:1; /* Device probing in progress */
475 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
476 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
477 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
478 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */
479 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */
480 unsigned int non_mappable_bars:1; /* BARs can't be mapped to user-space */
481 pci_dev_flags_t dev_flags;
482 atomic_t enable_cnt; /* pci_enable_device has been called */
483
484 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */
485 u32 saved_config_space[16]; /* Config space saved at suspend time */
486 struct hlist_head saved_cap_space;
487 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
488 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
489
490#ifdef CONFIG_HOTPLUG_PCI_PCIE
491 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
492#endif
493#ifdef CONFIG_PCIE_PTM
494 u16 ptm_cap; /* PTM Capability */
495 unsigned int ptm_root:1;
496 unsigned int ptm_enabled:1;
497 u8 ptm_granularity;
498#endif
499#ifdef CONFIG_PCI_MSI
500 void __iomem *msix_base;
501 raw_spinlock_t msi_lock;
502#endif
503 struct pci_vpd vpd;
504#ifdef CONFIG_PCIE_DPC
505 u16 dpc_cap;
506 unsigned int dpc_rp_extensions:1;
507 u8 dpc_rp_log_size;
508#endif
509 struct pcie_bwctrl_data *link_bwctrl;
510#ifdef CONFIG_PCI_ATS
511 union {
512 struct pci_sriov *sriov; /* PF: SR-IOV info */
513 struct pci_dev *physfn; /* VF: related PF */
514 };
515 u16 ats_cap; /* ATS Capability offset */
516 u8 ats_stu; /* ATS Smallest Translation Unit */
517#endif
518#ifdef CONFIG_PCI_PRI
519 u16 pri_cap; /* PRI Capability offset */
520 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
521 unsigned int pasid_required:1; /* PRG Response PASID Required */
522#endif
523#ifdef CONFIG_PCI_PASID
524 u16 pasid_cap; /* PASID Capability offset */
525 u16 pasid_features;
526#endif
527#ifdef CONFIG_PCI_P2PDMA
528 struct pci_p2pdma __rcu *p2pdma;
529#endif
530#ifdef CONFIG_PCI_DOE
531 struct xarray doe_mbs; /* Data Object Exchange mailboxes */
532#endif
533#ifdef CONFIG_PCI_NPEM
534 struct npem *npem; /* Native PCIe Enclosure Management */
535#endif
536 u16 acs_cap; /* ACS Capability offset */
537 u8 supported_speeds; /* Supported Link Speeds Vector */
538 phys_addr_t rom; /* Physical address if not from BAR */
539 size_t romlen; /* Length if not from BAR */
540 /*
541 * Driver name to force a match. Do not set directly, because core
542 * frees it. Use driver_set_override() to set or clear it.
543 */
544 const char *driver_override;
545
546 unsigned long priv_flags; /* Private flags for the PCI driver */
547
548 /* These methods index pci_reset_fn_methods[] */
549 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
550
551#ifdef CONFIG_PCIE_TPH
552 u16 tph_cap; /* TPH capability offset */
553 u8 tph_mode; /* TPH mode */
554 u8 tph_req_type; /* TPH requester type */
555#endif
556};
557
558static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
559{
560#ifdef CONFIG_PCI_IOV
561 if (dev->is_virtfn)
562 dev = dev->physfn;
563#endif
564 return dev;
565}
566
567struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
568
569#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
570#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
571
572static inline int pci_channel_offline(struct pci_dev *pdev)
573{
574 return (pdev->error_state != pci_channel_io_normal);
575}
576
577/*
578 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
579 * Group number is limited to a 16-bit value, therefore (int)-1 is
580 * not a valid PCI domain number, and can be used as a sentinel
581 * value indicating ->domain_nr is not set by the driver (and
582 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
583 * pci_bus_find_domain_nr()).
584 */
585#define PCI_DOMAIN_NR_NOT_SET (-1)
586
587struct pci_host_bridge {
588 struct device dev;
589 struct pci_bus *bus; /* Root bus */
590 struct pci_ops *ops;
591 struct pci_ops *child_ops;
592 void *sysdata;
593 int busnr;
594 int domain_nr;
595 struct list_head windows; /* resource_entry */
596 struct list_head dma_ranges; /* dma ranges resource list */
597 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
598 int (*map_irq)(const struct pci_dev *, u8, u8);
599 void (*release_fn)(struct pci_host_bridge *);
600 int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev);
601 void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev);
602 void *release_data;
603 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
604 unsigned int no_ext_tags:1; /* No Extended Tags */
605 unsigned int no_inc_mrrs:1; /* No Increase MRRS */
606 unsigned int native_aer:1; /* OS may use PCIe AER */
607 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
608 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
609 unsigned int native_pme:1; /* OS may use PCIe PME */
610 unsigned int native_ltr:1; /* OS may use PCIe LTR */
611 unsigned int native_dpc:1; /* OS may use PCIe DPC */
612 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
613 unsigned int preserve_config:1; /* Preserve FW resource setup */
614 unsigned int size_windows:1; /* Enable root bus sizing */
615 unsigned int msi_domain:1; /* Bridge wants MSI domain */
616
617 /* Resource alignment requirements */
618 resource_size_t (*align_resource)(struct pci_dev *dev,
619 const struct resource *res,
620 resource_size_t start,
621 resource_size_t size,
622 resource_size_t align);
623 unsigned long private[] ____cacheline_aligned;
624};
625
626#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
627
628static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
629{
630 return (void *)bridge->private;
631}
632
633static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
634{
635 return container_of(priv, struct pci_host_bridge, private);
636}
637
638struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
639struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
640 size_t priv);
641void pci_free_host_bridge(struct pci_host_bridge *bridge);
642struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
643
644void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
645 void (*release_fn)(struct pci_host_bridge *),
646 void *release_data);
647
648int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
649
650#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
651
652struct pci_bus {
653 struct list_head node; /* Node in list of buses */
654 struct pci_bus *parent; /* Parent bus this bridge is on */
655 struct list_head children; /* List of child buses */
656 struct list_head devices; /* List of devices on this bus */
657 struct pci_dev *self; /* Bridge device as seen by parent */
658 struct list_head slots; /* List of slots on this bus;
659 protected by pci_slot_mutex */
660 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
661 struct list_head resources; /* Address space routed to this bus */
662 struct resource busn_res; /* Bus numbers routed to this bus */
663
664 struct pci_ops *ops; /* Configuration access functions */
665 void *sysdata; /* Hook for sys-specific extension */
666 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
667
668 unsigned char number; /* Bus number */
669 unsigned char primary; /* Number of primary bridge */
670 unsigned char max_bus_speed; /* enum pci_bus_speed */
671 unsigned char cur_bus_speed; /* enum pci_bus_speed */
672#ifdef CONFIG_PCI_DOMAINS_GENERIC
673 int domain_nr;
674#endif
675
676 char name[48];
677
678 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
679 pci_bus_flags_t bus_flags; /* Inherited by child buses */
680 struct device *bridge;
681 struct device dev;
682 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
683 struct bin_attribute *legacy_mem; /* Legacy mem */
684 unsigned int is_added:1;
685 unsigned int unsafe_warn:1; /* warned about RW1C config write */
686 unsigned int flit_mode:1; /* Link in Flit mode */
687};
688
689#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
690
691static inline u16 pci_dev_id(struct pci_dev *dev)
692{
693 return PCI_DEVID(dev->bus->number, dev->devfn);
694}
695
696/*
697 * Returns true if the PCI bus is root (behind host-PCI bridge),
698 * false otherwise
699 *
700 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
701 * This is incorrect because "virtual" buses added for SR-IOV (via
702 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
703 */
704static inline bool pci_is_root_bus(struct pci_bus *pbus)
705{
706 return !(pbus->parent);
707}
708
709/**
710 * pci_is_bridge - check if the PCI device is a bridge
711 * @dev: PCI device
712 *
713 * Return true if the PCI device is bridge whether it has subordinate
714 * or not.
715 */
716static inline bool pci_is_bridge(struct pci_dev *dev)
717{
718 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
719 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
720}
721
722/**
723 * pci_is_vga - check if the PCI device is a VGA device
724 * @pdev: PCI device
725 *
726 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define
727 * VGA Base Class and Sub-Classes:
728 *
729 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible
730 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code)
731 *
732 * Return true if the PCI device is a VGA device and uses the legacy VGA
733 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and
734 * aliases).
735 */
736static inline bool pci_is_vga(struct pci_dev *pdev)
737{
738 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
739 return true;
740
741 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA)
742 return true;
743
744 return false;
745}
746
747#define for_each_pci_bridge(dev, bus) \
748 list_for_each_entry(dev, &bus->devices, bus_list) \
749 if (!pci_is_bridge(dev)) {} else
750
751static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
752{
753 dev = pci_physfn(dev);
754 if (pci_is_root_bus(dev->bus))
755 return NULL;
756
757 return dev->bus->self;
758}
759
760#ifdef CONFIG_PCI_MSI
761static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
762{
763 return pci_dev->msi_enabled || pci_dev->msix_enabled;
764}
765#else
766static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
767#endif
768
769/* Error values that may be returned by PCI functions */
770#define PCIBIOS_SUCCESSFUL 0x00
771#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
772#define PCIBIOS_BAD_VENDOR_ID 0x83
773#define PCIBIOS_DEVICE_NOT_FOUND 0x86
774#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
775#define PCIBIOS_SET_FAILED 0x88
776#define PCIBIOS_BUFFER_TOO_SMALL 0x89
777
778/* Translate above to generic errno for passing back through non-PCI code */
779static inline int pcibios_err_to_errno(int err)
780{
781 if (err <= PCIBIOS_SUCCESSFUL)
782 return err; /* Assume already errno */
783
784 switch (err) {
785 case PCIBIOS_FUNC_NOT_SUPPORTED:
786 return -ENOENT;
787 case PCIBIOS_BAD_VENDOR_ID:
788 return -ENOTTY;
789 case PCIBIOS_DEVICE_NOT_FOUND:
790 return -ENODEV;
791 case PCIBIOS_BAD_REGISTER_NUMBER:
792 return -EFAULT;
793 case PCIBIOS_SET_FAILED:
794 return -EIO;
795 case PCIBIOS_BUFFER_TOO_SMALL:
796 return -ENOSPC;
797 }
798
799 return -ERANGE;
800}
801
802/* Low-level architecture-dependent routines */
803
804struct pci_ops {
805 int (*add_bus)(struct pci_bus *bus);
806 void (*remove_bus)(struct pci_bus *bus);
807 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
808 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
809 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
810};
811
812/*
813 * ACPI needs to be able to access PCI config space before we've done a
814 * PCI bus scan and created pci_bus structures.
815 */
816int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
817 int reg, int len, u32 *val);
818int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
819 int reg, int len, u32 val);
820
821#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
822typedef u64 pci_bus_addr_t;
823#else
824typedef u32 pci_bus_addr_t;
825#endif
826
827struct pci_bus_region {
828 pci_bus_addr_t start;
829 pci_bus_addr_t end;
830};
831
832struct pci_dynids {
833 spinlock_t lock; /* Protects list, index */
834 struct list_head list; /* For IDs added at runtime */
835};
836
837
838/*
839 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
840 * a set of callbacks in struct pci_error_handlers, that device driver
841 * will be notified of PCI bus errors, and will be driven to recovery
842 * when an error occurs.
843 */
844
845typedef unsigned int __bitwise pci_ers_result_t;
846
847enum pci_ers_result {
848 /* No result/none/not supported in device driver */
849 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
850
851 /* Device driver can recover without slot reset */
852 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
853
854 /* Device driver wants slot to be reset */
855 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
856
857 /* Device has completely failed, is unrecoverable */
858 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
859
860 /* Device driver is fully recovered and operational */
861 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
862
863 /* No AER capabilities registered for the driver */
864 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
865};
866
867/* PCI bus error event callbacks */
868struct pci_error_handlers {
869 /* PCI bus error detected on this device */
870 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
871 pci_channel_state_t error);
872
873 /* MMIO has been re-enabled, but not DMA */
874 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
875
876 /* PCI slot has been reset */
877 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
878
879 /* PCI function reset prepare or completed */
880 void (*reset_prepare)(struct pci_dev *dev);
881 void (*reset_done)(struct pci_dev *dev);
882
883 /* Device driver may resume normal operations */
884 void (*resume)(struct pci_dev *dev);
885
886 /* Allow device driver to record more details of a correctable error */
887 void (*cor_error_detected)(struct pci_dev *dev);
888};
889
890
891struct module;
892
893/**
894 * struct pci_driver - PCI driver structure
895 * @name: Driver name.
896 * @id_table: Pointer to table of device IDs the driver is
897 * interested in. Most drivers should export this
898 * table using MODULE_DEVICE_TABLE(pci,...).
899 * @probe: This probing function gets called (during execution
900 * of pci_register_driver() for already existing
901 * devices or later if a new device gets inserted) for
902 * all PCI devices which match the ID table and are not
903 * "owned" by the other drivers yet. This function gets
904 * passed a "struct pci_dev \*" for each device whose
905 * entry in the ID table matches the device. The probe
906 * function returns zero when the driver chooses to
907 * take "ownership" of the device or an error code
908 * (negative number) otherwise.
909 * The probe function always gets called from process
910 * context, so it can sleep.
911 * @remove: The remove() function gets called whenever a device
912 * being handled by this driver is removed (either during
913 * deregistration of the driver or when it's manually
914 * pulled out of a hot-pluggable slot).
915 * The remove function always gets called from process
916 * context, so it can sleep.
917 * @suspend: Put device into low power state.
918 * @resume: Wake device from low power state.
919 * (Please see Documentation/power/pci.rst for descriptions
920 * of PCI Power Management and the related functions.)
921 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
922 * Intended to stop any idling DMA operations.
923 * Useful for enabling wake-on-lan (NIC) or changing
924 * the power state of a device before reboot.
925 * e.g. drivers/net/e100.c.
926 * @sriov_configure: Optional driver callback to allow configuration of
927 * number of VFs to enable via sysfs "sriov_numvfs" file.
928 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
929 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
930 * This will change MSI-X Table Size in the VF Message Control
931 * registers.
932 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
933 * MSI-X vectors available for distribution to the VFs.
934 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
935 * @groups: Sysfs attribute groups.
936 * @dev_groups: Attributes attached to the device that will be
937 * created once it is bound to the driver.
938 * @driver: Driver model structure.
939 * @dynids: List of dynamically added device IDs.
940 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA.
941 * For most device drivers, no need to care about this flag
942 * as long as all DMAs are handled through the kernel DMA API.
943 * For some special ones, for example VFIO drivers, they know
944 * how to manage the DMA themselves and set this flag so that
945 * the IOMMU layer will allow them to setup and manage their
946 * own I/O address space.
947 */
948struct pci_driver {
949 const char *name;
950 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
951 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
952 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
953 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
954 int (*resume)(struct pci_dev *dev); /* Device woken up */
955 void (*shutdown)(struct pci_dev *dev);
956 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
957 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
958 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
959 const struct pci_error_handlers *err_handler;
960 const struct attribute_group **groups;
961 const struct attribute_group **dev_groups;
962 struct device_driver driver;
963 struct pci_dynids dynids;
964 bool driver_managed_dma;
965};
966
967#define to_pci_driver(__drv) \
968 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL )
969
970/**
971 * PCI_DEVICE - macro used to describe a specific PCI device
972 * @vend: the 16 bit PCI Vendor ID
973 * @dev: the 16 bit PCI Device ID
974 *
975 * This macro is used to create a struct pci_device_id that matches a
976 * specific device. The subvendor and subdevice fields will be set to
977 * PCI_ANY_ID.
978 */
979#define PCI_DEVICE(vend,dev) \
980 .vendor = (vend), .device = (dev), \
981 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
982
983/**
984 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
985 * override_only flags.
986 * @vend: the 16 bit PCI Vendor ID
987 * @dev: the 16 bit PCI Device ID
988 * @driver_override: the 32 bit PCI Device override_only
989 *
990 * This macro is used to create a struct pci_device_id that matches only a
991 * driver_override device. The subvendor and subdevice fields will be set to
992 * PCI_ANY_ID.
993 */
994#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
995 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
996 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
997
998/**
999 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
1000 * "driver_override" PCI device.
1001 * @vend: the 16 bit PCI Vendor ID
1002 * @dev: the 16 bit PCI Device ID
1003 *
1004 * This macro is used to create a struct pci_device_id that matches a
1005 * specific device. The subvendor and subdevice fields will be set to
1006 * PCI_ANY_ID and the driver_override will be set to
1007 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
1008 */
1009#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
1010 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
1011
1012/**
1013 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
1014 * @vend: the 16 bit PCI Vendor ID
1015 * @dev: the 16 bit PCI Device ID
1016 * @subvend: the 16 bit PCI Subvendor ID
1017 * @subdev: the 16 bit PCI Subdevice ID
1018 *
1019 * This macro is used to create a struct pci_device_id that matches a
1020 * specific device with subsystem information.
1021 */
1022#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1023 .vendor = (vend), .device = (dev), \
1024 .subvendor = (subvend), .subdevice = (subdev)
1025
1026/**
1027 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
1028 * @dev_class: the class, subclass, prog-if triple for this device
1029 * @dev_class_mask: the class mask for this device
1030 *
1031 * This macro is used to create a struct pci_device_id that matches a
1032 * specific PCI class. The vendor, device, subvendor, and subdevice
1033 * fields will be set to PCI_ANY_ID.
1034 */
1035#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
1036 .class = (dev_class), .class_mask = (dev_class_mask), \
1037 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1038 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1039
1040/**
1041 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1042 * @vend: the vendor name
1043 * @dev: the 16 bit PCI Device ID
1044 *
1045 * This macro is used to create a struct pci_device_id that matches a
1046 * specific PCI device. The subvendor, and subdevice fields will be set
1047 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1048 * private data.
1049 */
1050#define PCI_VDEVICE(vend, dev) \
1051 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1052 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1053
1054/**
1055 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form
1056 * @vend: the vendor name
1057 * @dev: the 16 bit PCI Device ID
1058 * @subvend: the 16 bit PCI Subvendor ID
1059 * @subdev: the 16 bit PCI Subdevice ID
1060 *
1061 * Generate the pci_device_id struct layout for the specific PCI
1062 * device/subdevice. Private data may follow the output.
1063 */
1064#define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \
1065 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1066 .subvendor = (subvend), .subdevice = (subdev), 0, 0
1067
1068/**
1069 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1070 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1071 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1072 * @data: the driver data to be filled
1073 *
1074 * This macro is used to create a struct pci_device_id that matches a
1075 * specific PCI device. The subvendor, and subdevice fields will be set
1076 * to PCI_ANY_ID.
1077 */
1078#define PCI_DEVICE_DATA(vend, dev, data) \
1079 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1080 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1081 .driver_data = (kernel_ulong_t)(data)
1082
1083enum {
1084 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1085 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1086 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1087 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1088 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1089 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1090 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1091};
1092
1093#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
1094#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1095#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1096#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1097
1098/* These external functions are only available when PCI support is enabled */
1099#ifdef CONFIG_PCI
1100
1101extern unsigned int pci_flags;
1102
1103static inline void pci_set_flags(int flags) { pci_flags = flags; }
1104static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1105static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1106static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1107
1108void pcie_bus_configure_settings(struct pci_bus *bus);
1109
1110enum pcie_bus_config_types {
1111 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1112 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1113 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1114 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1115 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1116};
1117
1118extern enum pcie_bus_config_types pcie_bus_config;
1119
1120extern const struct bus_type pci_bus_type;
1121
1122/* Do NOT directly access these two variables, unless you are arch-specific PCI
1123 * code, or PCI core code. */
1124extern struct list_head pci_root_buses; /* List of all known PCI buses */
1125/* Some device drivers need know if PCI is initiated */
1126int no_pci_devices(void);
1127
1128void pcibios_resource_survey_bus(struct pci_bus *bus);
1129void pcibios_bus_add_device(struct pci_dev *pdev);
1130void pcibios_add_bus(struct pci_bus *bus);
1131void pcibios_remove_bus(struct pci_bus *bus);
1132void pcibios_fixup_bus(struct pci_bus *);
1133int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1134/* Architecture-specific versions may override this (weak) */
1135char *pcibios_setup(char *str);
1136
1137/* Used only when drivers/pci/setup.c is used */
1138resource_size_t pcibios_align_resource(void *, const struct resource *,
1139 resource_size_t,
1140 resource_size_t);
1141
1142/* Generic PCI functions used internally */
1143
1144void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1145 struct resource *res);
1146void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1147 struct pci_bus_region *region);
1148void pcibios_scan_specific_bus(int busn);
1149struct pci_bus *pci_find_bus(int domain, int busnr);
1150void pci_bus_add_devices(const struct pci_bus *bus);
1151struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1152struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1153 struct pci_ops *ops, void *sysdata,
1154 struct list_head *resources);
1155int pci_host_probe(struct pci_host_bridge *bridge);
1156int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1157int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1158void pci_bus_release_busn_res(struct pci_bus *b);
1159struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1160 struct pci_ops *ops, void *sysdata,
1161 struct list_head *resources);
1162int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1163struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1164 int busnr);
1165struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1166 const char *name,
1167 struct hotplug_slot *hotplug);
1168void pci_destroy_slot(struct pci_slot *slot);
1169#ifdef CONFIG_SYSFS
1170void pci_dev_assign_slot(struct pci_dev *dev);
1171#else
1172static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1173#endif
1174int pci_scan_slot(struct pci_bus *bus, int devfn);
1175struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1176void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1177unsigned int pci_scan_child_bus(struct pci_bus *bus);
1178void pci_bus_add_device(struct pci_dev *dev);
1179void pci_read_bridge_bases(struct pci_bus *child);
1180struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1181 struct resource *res);
1182u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1183int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1184u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1185struct pci_dev *pci_dev_get(struct pci_dev *dev);
1186void pci_dev_put(struct pci_dev *dev);
1187DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T))
1188void pci_remove_bus(struct pci_bus *b);
1189void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1190void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1191void pci_stop_root_bus(struct pci_bus *bus);
1192void pci_remove_root_bus(struct pci_bus *bus);
1193void pci_setup_cardbus(struct pci_bus *bus);
1194void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1195void pci_sort_breadthfirst(void);
1196#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1197#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1198
1199/* Generic PCI functions exported to card drivers */
1200
1201u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1202u8 pci_find_capability(struct pci_dev *dev, int cap);
1203u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1204u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1205u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1206u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1207u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1208struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1209u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1210u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
1211
1212u64 pci_get_dsn(struct pci_dev *dev);
1213
1214struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1215 struct pci_dev *from);
1216struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1217 unsigned int ss_vendor, unsigned int ss_device,
1218 struct pci_dev *from);
1219struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1220struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1221 unsigned int devfn);
1222struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1223struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from);
1224
1225int pci_dev_present(const struct pci_device_id *ids);
1226
1227int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1228 int where, u8 *val);
1229int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1230 int where, u16 *val);
1231int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1232 int where, u32 *val);
1233int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1234 int where, u8 val);
1235int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1236 int where, u16 val);
1237int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1238 int where, u32 val);
1239
1240int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1241 int where, int size, u32 *val);
1242int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1243 int where, int size, u32 val);
1244int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1245 int where, int size, u32 *val);
1246int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1247 int where, int size, u32 val);
1248
1249struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1250
1251int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1252int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1253int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1254int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1255int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1256int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1257void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
1258 u32 clear, u32 set);
1259
1260int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1261int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1262int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1263int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1264int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
1265 u16 clear, u16 set);
1266int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
1267 u16 clear, u16 set);
1268int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1269 u32 clear, u32 set);
1270
1271/**
1272 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers
1273 * @dev: PCI device structure of the PCI Express device
1274 * @pos: PCI Express Capability Register
1275 * @clear: Clear bitmask
1276 * @set: Set bitmask
1277 *
1278 * Perform a Read-Modify-Write (RMW) operation using @clear and @set
1279 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express
1280 * Capability Registers are accessed concurrently in RMW fashion, hence
1281 * require locking which is handled transparently to the caller.
1282 */
1283static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev,
1284 int pos,
1285 u16 clear, u16 set)
1286{
1287 switch (pos) {
1288 case PCI_EXP_LNKCTL:
1289 case PCI_EXP_LNKCTL2:
1290 case PCI_EXP_RTCTL:
1291 return pcie_capability_clear_and_set_word_locked(dev, pos,
1292 clear, set);
1293 default:
1294 return pcie_capability_clear_and_set_word_unlocked(dev, pos,
1295 clear, set);
1296 }
1297}
1298
1299static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1300 u16 set)
1301{
1302 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1303}
1304
1305static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1306 u32 set)
1307{
1308 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1309}
1310
1311static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1312 u16 clear)
1313{
1314 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1315}
1316
1317static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1318 u32 clear)
1319{
1320 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1321}
1322
1323/* User-space driven config access */
1324int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1325int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1326int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1327int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1328int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1329int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1330
1331int __must_check pci_enable_device(struct pci_dev *dev);
1332int __must_check pci_enable_device_mem(struct pci_dev *dev);
1333int __must_check pci_reenable_device(struct pci_dev *);
1334int __must_check pcim_enable_device(struct pci_dev *pdev);
1335void pcim_pin_device(struct pci_dev *pdev);
1336
1337static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1338{
1339 /*
1340 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1341 * writable and no quirk has marked the feature broken.
1342 */
1343 return !pdev->broken_intx_masking;
1344}
1345
1346static inline int pci_is_enabled(struct pci_dev *pdev)
1347{
1348 return (atomic_read(&pdev->enable_cnt) > 0);
1349}
1350
1351static inline int pci_is_managed(struct pci_dev *pdev)
1352{
1353 return pdev->is_managed;
1354}
1355
1356void pci_disable_device(struct pci_dev *dev);
1357
1358extern unsigned int pcibios_max_latency;
1359void pci_set_master(struct pci_dev *dev);
1360void pci_clear_master(struct pci_dev *dev);
1361
1362int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1363int pci_set_cacheline_size(struct pci_dev *dev);
1364int __must_check pci_set_mwi(struct pci_dev *dev);
1365int __must_check pcim_set_mwi(struct pci_dev *dev);
1366int pci_try_set_mwi(struct pci_dev *dev);
1367void pci_clear_mwi(struct pci_dev *dev);
1368void pci_disable_parity(struct pci_dev *dev);
1369void pci_intx(struct pci_dev *dev, int enable);
1370bool pci_check_and_mask_intx(struct pci_dev *dev);
1371bool pci_check_and_unmask_intx(struct pci_dev *dev);
1372int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1373int pci_wait_for_pending_transaction(struct pci_dev *dev);
1374int pcix_get_max_mmrbc(struct pci_dev *dev);
1375int pcix_get_mmrbc(struct pci_dev *dev);
1376int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1377int pcie_get_readrq(struct pci_dev *dev);
1378int pcie_set_readrq(struct pci_dev *dev, int rq);
1379int pcie_get_mps(struct pci_dev *dev);
1380int pcie_set_mps(struct pci_dev *dev, int mps);
1381u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1382 enum pci_bus_speed *speed,
1383 enum pcie_link_width *width);
1384int pcie_link_speed_mbps(struct pci_dev *pdev);
1385void pcie_print_link_status(struct pci_dev *dev);
1386int pcie_reset_flr(struct pci_dev *dev, bool probe);
1387int pcie_flr(struct pci_dev *dev);
1388int __pci_reset_function_locked(struct pci_dev *dev);
1389int pci_reset_function(struct pci_dev *dev);
1390int pci_reset_function_locked(struct pci_dev *dev);
1391int pci_try_reset_function(struct pci_dev *dev);
1392int pci_probe_reset_slot(struct pci_slot *slot);
1393int pci_probe_reset_bus(struct pci_bus *bus);
1394int pci_reset_bus(struct pci_dev *dev);
1395void pci_reset_secondary_bus(struct pci_dev *dev);
1396void pcibios_reset_secondary_bus(struct pci_dev *dev);
1397void pci_update_resource(struct pci_dev *dev, int resno);
1398int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1399void pci_release_resource(struct pci_dev *dev, int resno);
1400static inline int pci_rebar_bytes_to_size(u64 bytes)
1401{
1402 bytes = roundup_pow_of_two(bytes);
1403
1404 /* Return BAR size as defined in the resizable BAR specification */
1405 return max(ilog2(bytes), 20) - 20;
1406}
1407
1408u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1409int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1410int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1411bool pci_device_is_present(struct pci_dev *pdev);
1412void pci_ignore_hotplug(struct pci_dev *dev);
1413struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1414int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1415
1416int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1417 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1418 const char *fmt, ...);
1419void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1420
1421/* ROM control related routines */
1422int pci_enable_rom(struct pci_dev *pdev);
1423void pci_disable_rom(struct pci_dev *pdev);
1424void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1425void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1426
1427/* Power management related routines */
1428int pci_save_state(struct pci_dev *dev);
1429void pci_restore_state(struct pci_dev *dev);
1430struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1431int pci_load_saved_state(struct pci_dev *dev,
1432 struct pci_saved_state *state);
1433int pci_load_and_free_saved_state(struct pci_dev *dev,
1434 struct pci_saved_state **state);
1435int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1436int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1437int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state);
1438pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1439bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1440void pci_pme_active(struct pci_dev *dev, bool enable);
1441int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1442int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1443int pci_prepare_to_sleep(struct pci_dev *dev);
1444int pci_back_from_sleep(struct pci_dev *dev);
1445bool pci_dev_run_wake(struct pci_dev *dev);
1446void pci_d3cold_enable(struct pci_dev *dev);
1447void pci_d3cold_disable(struct pci_dev *dev);
1448bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1449void pci_resume_bus(struct pci_bus *bus);
1450void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1451
1452/* For use by arch with custom probe code */
1453void set_pcie_port_type(struct pci_dev *pdev);
1454void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1455
1456/* Functions for PCI Hotplug drivers to use */
1457unsigned int pci_rescan_bus(struct pci_bus *bus);
1458void pci_lock_rescan_remove(void);
1459void pci_unlock_rescan_remove(void);
1460
1461/* Vital Product Data routines */
1462ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1463ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1464ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1465ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1466
1467/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1468resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1469void pci_bus_assign_resources(const struct pci_bus *bus);
1470void pci_bus_claim_resources(struct pci_bus *bus);
1471void pci_bus_size_bridges(struct pci_bus *bus);
1472int pci_claim_resource(struct pci_dev *, int);
1473int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1474void pci_assign_unassigned_resources(void);
1475void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1476void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1477void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1478int pci_enable_resources(struct pci_dev *, int mask);
1479void pci_assign_irq(struct pci_dev *dev);
1480struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1481#define HAVE_PCI_REQ_REGIONS 2
1482int __must_check pci_request_regions(struct pci_dev *, const char *);
1483int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1484void pci_release_regions(struct pci_dev *);
1485int __must_check pci_request_region(struct pci_dev *, int, const char *);
1486void pci_release_region(struct pci_dev *, int);
1487int pci_request_selected_regions(struct pci_dev *, int, const char *);
1488int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1489void pci_release_selected_regions(struct pci_dev *, int);
1490
1491static inline __must_check struct resource *
1492pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset,
1493 unsigned int len, const char *name)
1494{
1495 return __request_region(&pdev->driver_exclusive_resource, offset, len,
1496 name, IORESOURCE_EXCLUSIVE);
1497}
1498
1499static inline void pci_release_config_region(struct pci_dev *pdev,
1500 unsigned int offset,
1501 unsigned int len)
1502{
1503 __release_region(&pdev->driver_exclusive_resource, offset, len);
1504}
1505
1506/* drivers/pci/bus.c */
1507void pci_add_resource(struct list_head *resources, struct resource *res);
1508void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1509 resource_size_t offset);
1510void pci_free_resource_list(struct list_head *resources);
1511void pci_bus_add_resource(struct pci_bus *bus, struct resource *res);
1512struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1513void pci_bus_remove_resources(struct pci_bus *bus);
1514void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1515int devm_request_pci_bus_resources(struct device *dev,
1516 struct list_head *resources);
1517
1518/* Temporary until new and working PCI SBR API in place */
1519int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1520
1521#define __pci_bus_for_each_res0(bus, res, ...) \
1522 for (unsigned int __b = 0; \
1523 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1524 __b++)
1525
1526#define __pci_bus_for_each_res1(bus, res, __b) \
1527 for (__b = 0; \
1528 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \
1529 __b++)
1530
1531/**
1532 * pci_bus_for_each_resource - iterate over PCI bus resources
1533 * @bus: the PCI bus
1534 * @res: pointer to the current resource
1535 * @...: optional index of the current resource
1536 *
1537 * Iterate over PCI bus resources. The first part is to go over PCI bus
1538 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries.
1539 * After that continue with the separate list of the additional resources,
1540 * if not empty. That's why the Logical OR is being used.
1541 *
1542 * Possible usage:
1543 *
1544 * struct pci_bus *bus = ...;
1545 * struct resource *res;
1546 * unsigned int i;
1547 *
1548 * // With optional index
1549 * pci_bus_for_each_resource(bus, res, i)
1550 * pr_info("PCI bus resource[%u]: %pR\n", i, res);
1551 *
1552 * // Without index
1553 * pci_bus_for_each_resource(bus, res)
1554 * _do_something_(res);
1555 */
1556#define pci_bus_for_each_resource(bus, res, ...) \
1557 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
1558 (bus, res, __VA_ARGS__)
1559
1560int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1561 struct resource *res, resource_size_t size,
1562 resource_size_t align, resource_size_t min,
1563 unsigned long type_mask,
1564 resource_alignf alignf,
1565 void *alignf_data);
1566
1567
1568int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr,
1569 resource_size_t size);
1570unsigned long pci_address_to_pio(phys_addr_t addr);
1571phys_addr_t pci_pio_to_address(unsigned long pio);
1572int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1573int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1574 phys_addr_t phys_addr);
1575void pci_unmap_iospace(struct resource *res);
1576void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1577 resource_size_t offset,
1578 resource_size_t size);
1579void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1580 struct resource *res);
1581
1582static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1583{
1584 struct pci_bus_region region;
1585
1586 pcibios_resource_to_bus(pdev->bus, &region, &pdev->resource[bar]);
1587 return region.start;
1588}
1589
1590/* Proper probing supporting hot-pluggable devices */
1591int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1592 const char *mod_name);
1593
1594/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1595#define pci_register_driver(driver) \
1596 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1597
1598void pci_unregister_driver(struct pci_driver *dev);
1599
1600/**
1601 * module_pci_driver() - Helper macro for registering a PCI driver
1602 * @__pci_driver: pci_driver struct
1603 *
1604 * Helper macro for PCI drivers which do not do anything special in module
1605 * init/exit. This eliminates a lot of boilerplate. Each module may only
1606 * use this macro once, and calling it replaces module_init() and module_exit()
1607 */
1608#define module_pci_driver(__pci_driver) \
1609 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1610
1611/**
1612 * builtin_pci_driver() - Helper macro for registering a PCI driver
1613 * @__pci_driver: pci_driver struct
1614 *
1615 * Helper macro for PCI drivers which do not do anything special in their
1616 * init code. This eliminates a lot of boilerplate. Each driver may only
1617 * use this macro once, and calling it replaces device_initcall(...)
1618 */
1619#define builtin_pci_driver(__pci_driver) \
1620 builtin_driver(__pci_driver, pci_register_driver)
1621
1622struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1623int pci_add_dynid(struct pci_driver *drv,
1624 unsigned int vendor, unsigned int device,
1625 unsigned int subvendor, unsigned int subdevice,
1626 unsigned int class, unsigned int class_mask,
1627 unsigned long driver_data);
1628const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1629 struct pci_dev *dev);
1630int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1631 int pass);
1632
1633void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1634 void *userdata);
1635int pci_cfg_space_size(struct pci_dev *dev);
1636unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1637resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1638 unsigned long type);
1639
1640#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1641#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1642
1643int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1644 unsigned int command_bits, u32 flags);
1645
1646/*
1647 * Virtual interrupts allow for more interrupts to be allocated
1648 * than the device has interrupts for. These are not programmed
1649 * into the device's MSI-X table and must be handled by some
1650 * other driver means.
1651 */
1652#define PCI_IRQ_VIRTUAL (1 << 4)
1653
1654#define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1655
1656#include <linux/dmapool.h>
1657
1658struct msix_entry {
1659 u32 vector; /* Kernel uses to write allocated vector */
1660 u16 entry; /* Driver uses to specify entry, OS writes */
1661};
1662
1663#ifdef CONFIG_PCI_MSI
1664int pci_msi_vec_count(struct pci_dev *dev);
1665void pci_disable_msi(struct pci_dev *dev);
1666int pci_msix_vec_count(struct pci_dev *dev);
1667void pci_disable_msix(struct pci_dev *dev);
1668void pci_restore_msi_state(struct pci_dev *dev);
1669bool pci_msi_enabled(void);
1670int pci_enable_msi(struct pci_dev *dev);
1671int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1672 int minvec, int maxvec);
1673static inline int pci_enable_msix_exact(struct pci_dev *dev,
1674 struct msix_entry *entries, int nvec)
1675{
1676 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1677 if (rc < 0)
1678 return rc;
1679 return 0;
1680}
1681int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1682 unsigned int max_vecs, unsigned int flags);
1683int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1684 unsigned int max_vecs, unsigned int flags,
1685 struct irq_affinity *affd);
1686
1687bool pci_msix_can_alloc_dyn(struct pci_dev *dev);
1688struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1689 const struct irq_affinity_desc *affdesc);
1690void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map);
1691
1692void pci_free_irq_vectors(struct pci_dev *dev);
1693int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1694const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1695
1696#else
1697static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1698static inline void pci_disable_msi(struct pci_dev *dev) { }
1699static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1700static inline void pci_disable_msix(struct pci_dev *dev) { }
1701static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1702static inline bool pci_msi_enabled(void) { return false; }
1703static inline int pci_enable_msi(struct pci_dev *dev)
1704{ return -ENOSYS; }
1705static inline int pci_enable_msix_range(struct pci_dev *dev,
1706 struct msix_entry *entries, int minvec, int maxvec)
1707{ return -ENOSYS; }
1708static inline int pci_enable_msix_exact(struct pci_dev *dev,
1709 struct msix_entry *entries, int nvec)
1710{ return -ENOSYS; }
1711
1712static inline int
1713pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1714 unsigned int max_vecs, unsigned int flags,
1715 struct irq_affinity *aff_desc)
1716{
1717 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq)
1718 return 1;
1719 return -ENOSPC;
1720}
1721static inline int
1722pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1723 unsigned int max_vecs, unsigned int flags)
1724{
1725 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs,
1726 flags, NULL);
1727}
1728
1729static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev)
1730{ return false; }
1731static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
1732 const struct irq_affinity_desc *affdesc)
1733{
1734 struct msi_map map = { .index = -ENOSYS, };
1735
1736 return map;
1737}
1738
1739static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
1740{
1741}
1742
1743static inline void pci_free_irq_vectors(struct pci_dev *dev)
1744{
1745}
1746
1747static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1748{
1749 if (WARN_ON_ONCE(nr > 0))
1750 return -EINVAL;
1751 return dev->irq;
1752}
1753static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1754 int vec)
1755{
1756 return cpu_possible_mask;
1757}
1758#endif
1759
1760/**
1761 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1762 * @d: the INTx IRQ domain
1763 * @node: the DT node for the device whose interrupt we're translating
1764 * @intspec: the interrupt specifier data from the DT
1765 * @intsize: the number of entries in @intspec
1766 * @out_hwirq: pointer at which to write the hwirq number
1767 * @out_type: pointer at which to write the interrupt type
1768 *
1769 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1770 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1771 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1772 * INTx value to obtain the hwirq number.
1773 *
1774 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1775 */
1776static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1777 struct device_node *node,
1778 const u32 *intspec,
1779 unsigned int intsize,
1780 unsigned long *out_hwirq,
1781 unsigned int *out_type)
1782{
1783 const u32 intx = intspec[0];
1784
1785 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1786 return -EINVAL;
1787
1788 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1789 return 0;
1790}
1791
1792#ifdef CONFIG_PCIEPORTBUS
1793extern bool pcie_ports_disabled;
1794extern bool pcie_ports_native;
1795
1796int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req,
1797 bool use_lt);
1798#else
1799#define pcie_ports_disabled true
1800#define pcie_ports_native false
1801
1802static inline int pcie_set_target_speed(struct pci_dev *port,
1803 enum pci_bus_speed speed_req,
1804 bool use_lt)
1805{
1806 return -EOPNOTSUPP;
1807}
1808#endif
1809
1810#define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */
1811#define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */
1812#define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */
1813#define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */
1814#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */
1815#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */
1816#define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\
1817 PCIE_LINK_STATE_L1 |\
1818 PCIE_LINK_STATE_L1_1 |\
1819 PCIE_LINK_STATE_L1_2 |\
1820 PCIE_LINK_STATE_L1_1_PCIPM |\
1821 PCIE_LINK_STATE_L1_2_PCIPM)
1822#define PCIE_LINK_STATE_CLKPM BIT(7)
1823#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\
1824 PCIE_LINK_STATE_CLKPM)
1825
1826#ifdef CONFIG_PCIEASPM
1827int pci_disable_link_state(struct pci_dev *pdev, int state);
1828int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1829int pci_enable_link_state(struct pci_dev *pdev, int state);
1830int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
1831void pcie_no_aspm(void);
1832bool pcie_aspm_support_enabled(void);
1833bool pcie_aspm_enabled(struct pci_dev *pdev);
1834#else
1835static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1836{ return 0; }
1837static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1838{ return 0; }
1839static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
1840{ return 0; }
1841static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1842{ return 0; }
1843static inline void pcie_no_aspm(void) { }
1844static inline bool pcie_aspm_support_enabled(void) { return false; }
1845static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1846#endif
1847
1848#ifdef CONFIG_HOTPLUG_PCI
1849void pci_hp_ignore_link_change(struct pci_dev *pdev);
1850void pci_hp_unignore_link_change(struct pci_dev *pdev);
1851#else
1852static inline void pci_hp_ignore_link_change(struct pci_dev *pdev) { }
1853static inline void pci_hp_unignore_link_change(struct pci_dev *pdev) { }
1854#endif
1855
1856#ifdef CONFIG_PCIEAER
1857bool pci_aer_available(void);
1858#else
1859static inline bool pci_aer_available(void) { return false; }
1860#endif
1861
1862bool pci_ats_disabled(void);
1863
1864#define PCIE_PTM_CONTEXT_UPDATE_AUTO 0
1865#define PCIE_PTM_CONTEXT_UPDATE_MANUAL 1
1866
1867struct pcie_ptm_ops {
1868 int (*check_capability)(void *drvdata);
1869 int (*context_update_write)(void *drvdata, u8 mode);
1870 int (*context_update_read)(void *drvdata, u8 *mode);
1871 int (*context_valid_write)(void *drvdata, bool valid);
1872 int (*context_valid_read)(void *drvdata, bool *valid);
1873 int (*local_clock_read)(void *drvdata, u64 *clock);
1874 int (*master_clock_read)(void *drvdata, u64 *clock);
1875 int (*t1_read)(void *drvdata, u64 *clock);
1876 int (*t2_read)(void *drvdata, u64 *clock);
1877 int (*t3_read)(void *drvdata, u64 *clock);
1878 int (*t4_read)(void *drvdata, u64 *clock);
1879
1880 bool (*context_update_visible)(void *drvdata);
1881 bool (*context_valid_visible)(void *drvdata);
1882 bool (*local_clock_visible)(void *drvdata);
1883 bool (*master_clock_visible)(void *drvdata);
1884 bool (*t1_visible)(void *drvdata);
1885 bool (*t2_visible)(void *drvdata);
1886 bool (*t3_visible)(void *drvdata);
1887 bool (*t4_visible)(void *drvdata);
1888};
1889
1890struct pci_ptm_debugfs {
1891 struct dentry *debugfs;
1892 const struct pcie_ptm_ops *ops;
1893 struct mutex lock;
1894 void *pdata;
1895};
1896
1897#ifdef CONFIG_PCIE_PTM
1898int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1899void pci_disable_ptm(struct pci_dev *dev);
1900bool pcie_ptm_enabled(struct pci_dev *dev);
1901#else
1902static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1903{ return -EINVAL; }
1904static inline void pci_disable_ptm(struct pci_dev *dev) { }
1905static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1906{ return false; }
1907#endif
1908
1909#if IS_ENABLED(CONFIG_DEBUG_FS) && IS_ENABLED(CONFIG_PCIE_PTM)
1910struct pci_ptm_debugfs *pcie_ptm_create_debugfs(struct device *dev, void *pdata,
1911 const struct pcie_ptm_ops *ops);
1912void pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs);
1913#else
1914static inline struct pci_ptm_debugfs
1915*pcie_ptm_create_debugfs(struct device *dev, void *pdata,
1916 const struct pcie_ptm_ops *ops) { return NULL; }
1917static inline void
1918pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs) { }
1919#endif
1920
1921void pci_cfg_access_lock(struct pci_dev *dev);
1922bool pci_cfg_access_trylock(struct pci_dev *dev);
1923void pci_cfg_access_unlock(struct pci_dev *dev);
1924
1925void pci_dev_lock(struct pci_dev *dev);
1926int pci_dev_trylock(struct pci_dev *dev);
1927void pci_dev_unlock(struct pci_dev *dev);
1928DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T))
1929
1930/*
1931 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1932 * a PCI domain is defined to be a set of PCI buses which share
1933 * configuration space.
1934 */
1935#ifdef CONFIG_PCI_DOMAINS
1936extern int pci_domains_supported;
1937#else
1938enum { pci_domains_supported = 0 };
1939static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1940static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1941#endif /* CONFIG_PCI_DOMAINS */
1942
1943/*
1944 * Generic implementation for PCI domain support. If your
1945 * architecture does not need custom management of PCI
1946 * domains then this implementation will be used
1947 */
1948#ifdef CONFIG_PCI_DOMAINS_GENERIC
1949static inline int pci_domain_nr(struct pci_bus *bus)
1950{
1951 return bus->domain_nr;
1952}
1953#ifdef CONFIG_ACPI
1954int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1955#else
1956static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1957{ return 0; }
1958#endif
1959int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1960void pci_bus_release_domain_nr(struct device *parent, int domain_nr);
1961#endif
1962
1963/* Some architectures require additional setup to direct VGA traffic */
1964typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1965 unsigned int command_bits, u32 flags);
1966void pci_register_set_vga_state(arch_set_vga_state_t func);
1967
1968static inline int
1969pci_request_io_regions(struct pci_dev *pdev, const char *name)
1970{
1971 return pci_request_selected_regions(pdev,
1972 pci_select_bars(pdev, IORESOURCE_IO), name);
1973}
1974
1975static inline void
1976pci_release_io_regions(struct pci_dev *pdev)
1977{
1978 return pci_release_selected_regions(pdev,
1979 pci_select_bars(pdev, IORESOURCE_IO));
1980}
1981
1982static inline int
1983pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1984{
1985 return pci_request_selected_regions(pdev,
1986 pci_select_bars(pdev, IORESOURCE_MEM), name);
1987}
1988
1989static inline void
1990pci_release_mem_regions(struct pci_dev *pdev)
1991{
1992 return pci_release_selected_regions(pdev,
1993 pci_select_bars(pdev, IORESOURCE_MEM));
1994}
1995
1996#else /* CONFIG_PCI is not enabled */
1997
1998static inline void pci_set_flags(int flags) { }
1999static inline void pci_add_flags(int flags) { }
2000static inline void pci_clear_flags(int flags) { }
2001static inline int pci_has_flag(int flag) { return 0; }
2002
2003/*
2004 * If the system does not have PCI, clearly these return errors. Define
2005 * these as simple inline functions to avoid hair in drivers.
2006 */
2007#define _PCI_NOP(o, s, t) \
2008 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
2009 int where, t val) \
2010 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
2011
2012#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
2013 _PCI_NOP(o, word, u16 x) \
2014 _PCI_NOP(o, dword, u32 x)
2015_PCI_NOP_ALL(read, *)
2016_PCI_NOP_ALL(write,)
2017
2018static inline struct pci_dev *pci_get_device(unsigned int vendor,
2019 unsigned int device,
2020 struct pci_dev *from)
2021{ return NULL; }
2022
2023static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
2024 unsigned int device,
2025 unsigned int ss_vendor,
2026 unsigned int ss_device,
2027 struct pci_dev *from)
2028{ return NULL; }
2029
2030static inline struct pci_dev *pci_get_class(unsigned int class,
2031 struct pci_dev *from)
2032{ return NULL; }
2033
2034static inline struct pci_dev *pci_get_base_class(unsigned int class,
2035 struct pci_dev *from)
2036{ return NULL; }
2037
2038static inline int pci_dev_present(const struct pci_device_id *ids)
2039{ return 0; }
2040
2041#define no_pci_devices() (1)
2042#define pci_dev_put(dev) do { } while (0)
2043
2044static inline void pci_set_master(struct pci_dev *dev) { }
2045static inline void pci_clear_master(struct pci_dev *dev) { }
2046static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
2047static inline void pci_disable_device(struct pci_dev *dev) { }
2048static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
2049static inline int pci_assign_resource(struct pci_dev *dev, int i)
2050{ return -EBUSY; }
2051static inline int __must_check __pci_register_driver(struct pci_driver *drv,
2052 struct module *owner,
2053 const char *mod_name)
2054{ return 0; }
2055static inline int pci_register_driver(struct pci_driver *drv)
2056{ return 0; }
2057static inline void pci_unregister_driver(struct pci_driver *drv) { }
2058static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
2059{ return 0; }
2060static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap)
2061{ return 0; }
2062static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
2063{ return 0; }
2064
2065static inline u64 pci_get_dsn(struct pci_dev *dev)
2066{ return 0; }
2067
2068/* Power management related routines */
2069static inline int pci_save_state(struct pci_dev *dev) { return 0; }
2070static inline void pci_restore_state(struct pci_dev *dev) { }
2071static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
2072{ return 0; }
2073static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state)
2074{ return 0; }
2075static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2076{ return 0; }
2077static inline pci_power_t pci_choose_state(struct pci_dev *dev,
2078 pm_message_t state)
2079{ return PCI_D0; }
2080static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
2081 int enable)
2082{ return 0; }
2083
2084static inline struct resource *pci_find_resource(struct pci_dev *dev,
2085 struct resource *res)
2086{ return NULL; }
2087static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
2088{ return -EIO; }
2089static inline void pci_release_regions(struct pci_dev *dev) { }
2090
2091static inline int pci_register_io_range(const struct fwnode_handle *fwnode,
2092 phys_addr_t addr, resource_size_t size)
2093{ return -EINVAL; }
2094
2095static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
2096
2097static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
2098{ return NULL; }
2099static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
2100 unsigned int devfn)
2101{ return NULL; }
2102static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
2103 unsigned int bus, unsigned int devfn)
2104{ return NULL; }
2105
2106static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
2107static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
2108
2109#define dev_is_pci(d) (false)
2110#define dev_is_pf(d) (false)
2111static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2112{ return false; }
2113static inline int pci_irqd_intx_xlate(struct irq_domain *d,
2114 struct device_node *node,
2115 const u32 *intspec,
2116 unsigned int intsize,
2117 unsigned long *out_hwirq,
2118 unsigned int *out_type)
2119{ return -EINVAL; }
2120
2121static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
2122 struct pci_dev *dev)
2123{ return NULL; }
2124static inline bool pci_ats_disabled(void) { return true; }
2125
2126static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
2127{
2128 return -EINVAL;
2129}
2130
2131static inline int
2132pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
2133 unsigned int max_vecs, unsigned int flags,
2134 struct irq_affinity *aff_desc)
2135{
2136 return -ENOSPC;
2137}
2138static inline int
2139pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
2140 unsigned int max_vecs, unsigned int flags)
2141{
2142 return -ENOSPC;
2143}
2144#endif /* CONFIG_PCI */
2145
2146/* Include architecture-dependent settings and functions */
2147
2148#include <asm/pci.h>
2149
2150/*
2151 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
2152 * is expected to be an offset within that region.
2153 *
2154 */
2155int pci_mmap_resource_range(struct pci_dev *dev, int bar,
2156 struct vm_area_struct *vma,
2157 enum pci_mmap_state mmap_state, int write_combine);
2158
2159#ifndef arch_can_pci_mmap_wc
2160#define arch_can_pci_mmap_wc() 0
2161#endif
2162
2163#ifndef arch_can_pci_mmap_io
2164#define arch_can_pci_mmap_io() 0
2165#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
2166#else
2167int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
2168#endif
2169
2170#ifndef pci_root_bus_fwnode
2171#define pci_root_bus_fwnode(bus) NULL
2172#endif
2173
2174/*
2175 * These helpers provide future and backwards compatibility
2176 * for accessing popular PCI BAR info
2177 */
2178#define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
2179#define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
2180#define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
2181#define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
2182#define pci_resource_len(dev,bar) \
2183 (pci_resource_end((dev), (bar)) ? \
2184 resource_size(pci_resource_n((dev), (bar))) : 0)
2185
2186#define __pci_dev_for_each_res0(dev, res, ...) \
2187 for (unsigned int __b = 0; \
2188 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2189 __b++)
2190
2191#define __pci_dev_for_each_res1(dev, res, __b) \
2192 for (__b = 0; \
2193 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \
2194 __b++)
2195
2196#define pci_dev_for_each_resource(dev, res, ...) \
2197 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \
2198 (dev, res, __VA_ARGS__)
2199
2200/*
2201 * Similar to the helpers above, these manipulate per-pci_dev
2202 * driver-specific data. They are really just a wrapper around
2203 * the generic device structure functions of these calls.
2204 */
2205static inline void *pci_get_drvdata(struct pci_dev *pdev)
2206{
2207 return dev_get_drvdata(&pdev->dev);
2208}
2209
2210static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
2211{
2212 dev_set_drvdata(&pdev->dev, data);
2213}
2214
2215static inline const char *pci_name(const struct pci_dev *pdev)
2216{
2217 return dev_name(&pdev->dev);
2218}
2219
2220void pci_resource_to_user(const struct pci_dev *dev, int bar,
2221 const struct resource *rsrc,
2222 resource_size_t *start, resource_size_t *end);
2223
2224/*
2225 * The world is not perfect and supplies us with broken PCI devices.
2226 * For at least a part of these bugs we need a work-around, so both
2227 * generic (drivers/pci/quirks.c) and per-architecture code can define
2228 * fixup hooks to be called for particular buggy devices.
2229 */
2230
2231struct pci_fixup {
2232 u16 vendor; /* Or PCI_ANY_ID */
2233 u16 device; /* Or PCI_ANY_ID */
2234 u32 class; /* Or PCI_ANY_ID */
2235 unsigned int class_shift; /* should be 0, 8, 16 */
2236#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2237 int hook_offset;
2238#else
2239 void (*hook)(struct pci_dev *dev);
2240#endif
2241};
2242
2243enum pci_fixup_pass {
2244 pci_fixup_early, /* Before probing BARs */
2245 pci_fixup_header, /* After reading configuration header */
2246 pci_fixup_final, /* Final phase of device fixups */
2247 pci_fixup_enable, /* pci_enable_device() time */
2248 pci_fixup_resume, /* pci_device_resume() */
2249 pci_fixup_suspend, /* pci_device_suspend() */
2250 pci_fixup_resume_early, /* pci_device_resume_early() */
2251 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2252};
2253
2254#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2255#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2256 class_shift, hook) \
2257 __ADDRESSABLE(hook) \
2258 asm(".section " #sec ", \"a\" \n" \
2259 ".balign 16 \n" \
2260 ".short " #vendor ", " #device " \n" \
2261 ".long " #class ", " #class_shift " \n" \
2262 ".long " #hook " - . \n" \
2263 ".previous \n");
2264
2265/*
2266 * Clang's LTO may rename static functions in C, but has no way to
2267 * handle such renamings when referenced from inline asm. To work
2268 * around this, create global C stubs for these cases.
2269 */
2270#ifdef CONFIG_LTO_CLANG
2271#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2272 class_shift, hook, stub) \
2273 void stub(struct pci_dev *dev); \
2274 void stub(struct pci_dev *dev) \
2275 { \
2276 hook(dev); \
2277 } \
2278 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2279 class_shift, stub)
2280#else
2281#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2282 class_shift, hook, stub) \
2283 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2284 class_shift, hook)
2285#endif
2286
2287#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2288 class_shift, hook) \
2289 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2290 class_shift, hook, __UNIQUE_ID(hook))
2291#else
2292/* Anonymous variables would be nice... */
2293#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2294 class_shift, hook) \
2295 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2296 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2297 = { vendor, device, class, class_shift, hook };
2298#endif
2299
2300#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2301 class_shift, hook) \
2302 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2303 hook, vendor, device, class, class_shift, hook)
2304#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2305 class_shift, hook) \
2306 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2307 hook, vendor, device, class, class_shift, hook)
2308#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2309 class_shift, hook) \
2310 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2311 hook, vendor, device, class, class_shift, hook)
2312#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2313 class_shift, hook) \
2314 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2315 hook, vendor, device, class, class_shift, hook)
2316#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2317 class_shift, hook) \
2318 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2319 resume##hook, vendor, device, class, class_shift, hook)
2320#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2321 class_shift, hook) \
2322 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2323 resume_early##hook, vendor, device, class, class_shift, hook)
2324#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2325 class_shift, hook) \
2326 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2327 suspend##hook, vendor, device, class, class_shift, hook)
2328#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2329 class_shift, hook) \
2330 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2331 suspend_late##hook, vendor, device, class, class_shift, hook)
2332
2333#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2334 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2335 hook, vendor, device, PCI_ANY_ID, 0, hook)
2336#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2337 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2338 hook, vendor, device, PCI_ANY_ID, 0, hook)
2339#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2340 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2341 hook, vendor, device, PCI_ANY_ID, 0, hook)
2342#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2343 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2344 hook, vendor, device, PCI_ANY_ID, 0, hook)
2345#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2346 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2347 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2348#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2349 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2350 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2351#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2352 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2353 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2354#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2355 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2356 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2357
2358#ifdef CONFIG_PCI_QUIRKS
2359void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2360#else
2361static inline void pci_fixup_device(enum pci_fixup_pass pass,
2362 struct pci_dev *dev) { }
2363#endif
2364
2365int pcim_intx(struct pci_dev *pdev, int enabled);
2366int pcim_request_all_regions(struct pci_dev *pdev, const char *name);
2367void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2368void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar,
2369 const char *name);
2370void pcim_iounmap_region(struct pci_dev *pdev, int bar);
2371void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2372void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2373int pcim_request_region(struct pci_dev *pdev, int bar, const char *name);
2374int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2375void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar,
2376 unsigned long offset, unsigned long len);
2377
2378extern int pci_pci_problems;
2379#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2380#define PCIPCI_TRITON 2
2381#define PCIPCI_NATOMA 4
2382#define PCIPCI_VIAETBF 8
2383#define PCIPCI_VSFX 16
2384#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2385#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2386
2387extern u8 pci_dfl_cache_line_size;
2388extern u8 pci_cache_line_size;
2389
2390/* Architecture-specific versions may override these (weak) */
2391void pcibios_disable_device(struct pci_dev *dev);
2392void pcibios_set_master(struct pci_dev *dev);
2393int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2394 enum pcie_reset_state state);
2395int pcibios_device_add(struct pci_dev *dev);
2396void pcibios_release_device(struct pci_dev *dev);
2397#ifdef CONFIG_PCI
2398void pcibios_penalize_isa_irq(int irq, int active);
2399#else
2400static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2401#endif
2402int pcibios_alloc_irq(struct pci_dev *dev);
2403void pcibios_free_irq(struct pci_dev *dev);
2404resource_size_t pcibios_default_alignment(void);
2405
2406#if !defined(HAVE_PCI_MMAP) && !defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)
2407extern int pci_create_resource_files(struct pci_dev *dev);
2408extern void pci_remove_resource_files(struct pci_dev *dev);
2409#endif
2410
2411#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2412void __init pci_mmcfg_early_init(void);
2413void __init pci_mmcfg_late_init(void);
2414#else
2415static inline void pci_mmcfg_early_init(void) { }
2416static inline void pci_mmcfg_late_init(void) { }
2417#endif
2418
2419int pci_ext_cfg_avail(void);
2420
2421void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2422void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2423
2424#ifdef CONFIG_PCI_IOV
2425int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2426int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2427int pci_iov_vf_id(struct pci_dev *dev);
2428void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
2429int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2430void pci_disable_sriov(struct pci_dev *dev);
2431
2432int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2433int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2434void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2435int pci_num_vf(struct pci_dev *dev);
2436int pci_vfs_assigned(struct pci_dev *dev);
2437int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2438int pci_sriov_get_totalvfs(struct pci_dev *dev);
2439int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2440resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2441void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2442
2443/* Arch may override these (weak) */
2444int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2445int pcibios_sriov_disable(struct pci_dev *pdev);
2446resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2447#else
2448static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2449{
2450 return -ENOSYS;
2451}
2452static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2453{
2454 return -ENOSYS;
2455}
2456
2457static inline int pci_iov_vf_id(struct pci_dev *dev)
2458{
2459 return -ENOSYS;
2460}
2461
2462static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev,
2463 struct pci_driver *pf_driver)
2464{
2465 return ERR_PTR(-EINVAL);
2466}
2467
2468static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2469{ return -ENODEV; }
2470
2471static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2472 struct pci_dev *virtfn, int id)
2473{
2474 return -ENODEV;
2475}
2476static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2477{
2478 return -ENOSYS;
2479}
2480static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2481 int id) { }
2482static inline void pci_disable_sriov(struct pci_dev *dev) { }
2483static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2484static inline int pci_vfs_assigned(struct pci_dev *dev)
2485{ return 0; }
2486static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2487{ return 0; }
2488static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2489{ return 0; }
2490#define pci_sriov_configure_simple NULL
2491static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2492{ return 0; }
2493static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2494#endif
2495
2496/**
2497 * pci_pcie_cap - get the saved PCIe capability offset
2498 * @dev: PCI device
2499 *
2500 * PCIe capability offset is calculated at PCI device initialization
2501 * time and saved in the data structure. This function returns saved
2502 * PCIe capability offset. Using this instead of pci_find_capability()
2503 * reduces unnecessary search in the PCI configuration space. If you
2504 * need to calculate PCIe capability offset from raw device for some
2505 * reasons, please use pci_find_capability() instead.
2506 */
2507static inline int pci_pcie_cap(struct pci_dev *dev)
2508{
2509 return dev->pcie_cap;
2510}
2511
2512/**
2513 * pci_is_pcie - check if the PCI device is PCI Express capable
2514 * @dev: PCI device
2515 *
2516 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2517 */
2518static inline bool pci_is_pcie(struct pci_dev *dev)
2519{
2520 return pci_pcie_cap(dev);
2521}
2522
2523/**
2524 * pcie_caps_reg - get the PCIe Capabilities Register
2525 * @dev: PCI device
2526 */
2527static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2528{
2529 return dev->pcie_flags_reg;
2530}
2531
2532/**
2533 * pci_pcie_type - get the PCIe device/port type
2534 * @dev: PCI device
2535 */
2536static inline int pci_pcie_type(const struct pci_dev *dev)
2537{
2538 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2539}
2540
2541/**
2542 * pcie_find_root_port - Get the PCIe root port device
2543 * @dev: PCI device
2544 *
2545 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2546 * for a given PCI/PCIe Device.
2547 */
2548static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2549{
2550 while (dev) {
2551 if (pci_is_pcie(dev) &&
2552 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2553 return dev;
2554 dev = pci_upstream_bridge(dev);
2555 }
2556
2557 return NULL;
2558}
2559
2560static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
2561{
2562 /*
2563 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg()
2564 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache
2565 * the value (e.g. inside the loop in pci_dev_wait()).
2566 */
2567 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure;
2568}
2569
2570void pci_request_acs(void);
2571bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2572bool pci_acs_path_enabled(struct pci_dev *start,
2573 struct pci_dev *end, u16 acs_flags);
2574int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2575
2576#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2577#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2578
2579/* Large Resource Data Type Tag Item Names */
2580#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2581#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2582#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2583
2584#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2585#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2586#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2587
2588#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2589#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2590#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2591#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2592#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2593
2594/**
2595 * pci_vpd_alloc - Allocate buffer and read VPD into it
2596 * @dev: PCI device
2597 * @size: pointer to field where VPD length is returned
2598 *
2599 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2600 */
2601void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2602
2603/**
2604 * pci_vpd_find_id_string - Locate id string in VPD
2605 * @buf: Pointer to buffered VPD data
2606 * @len: The length of the buffer area in which to search
2607 * @size: Pointer to field where length of id string is returned
2608 *
2609 * Returns the index of the id string or -ENOENT if not found.
2610 */
2611int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2612
2613/**
2614 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2615 * @buf: Pointer to buffered VPD data
2616 * @len: The length of the buffer area in which to search
2617 * @kw: The keyword to search for
2618 * @size: Pointer to field where length of found keyword data is returned
2619 *
2620 * Returns the index of the information field keyword data or -ENOENT if
2621 * not found.
2622 */
2623int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2624 const char *kw, unsigned int *size);
2625
2626/**
2627 * pci_vpd_check_csum - Check VPD checksum
2628 * @buf: Pointer to buffered VPD data
2629 * @len: VPD size
2630 *
2631 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2632 */
2633int pci_vpd_check_csum(const void *buf, unsigned int len);
2634
2635/* PCI <-> OF binding helpers */
2636#ifdef CONFIG_OF
2637struct device_node;
2638struct irq_domain;
2639struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2640bool pci_host_of_has_msi_map(struct device *dev);
2641
2642/* Arch may override this (weak) */
2643struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2644
2645#else /* CONFIG_OF */
2646static inline struct irq_domain *
2647pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2648static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2649#endif /* CONFIG_OF */
2650
2651static inline struct device_node *
2652pci_device_to_OF_node(const struct pci_dev *pdev)
2653{
2654 return pdev ? pdev->dev.of_node : NULL;
2655}
2656
2657static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2658{
2659 return bus ? bus->dev.of_node : NULL;
2660}
2661
2662#ifdef CONFIG_ACPI
2663struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2664
2665void
2666pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2667bool pci_pr3_present(struct pci_dev *pdev);
2668#else
2669static inline struct irq_domain *
2670pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2671static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2672#endif
2673
2674#if defined(CONFIG_X86) && defined(CONFIG_ACPI)
2675bool arch_pci_dev_is_removable(struct pci_dev *pdev);
2676#else
2677static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; }
2678#endif
2679
2680#ifdef CONFIG_EEH
2681static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2682{
2683 return pdev->dev.archdata.edev;
2684}
2685#endif
2686
2687void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2688bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2689int pci_for_each_dma_alias(struct pci_dev *pdev,
2690 int (*fn)(struct pci_dev *pdev,
2691 u16 alias, void *data), void *data);
2692
2693/* Helper functions for operation of device flag */
2694static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2695{
2696 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2697}
2698static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2699{
2700 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2701}
2702static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2703{
2704 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2705}
2706
2707/**
2708 * pci_ari_enabled - query ARI forwarding status
2709 * @bus: the PCI bus
2710 *
2711 * Returns true if ARI forwarding is enabled.
2712 */
2713static inline bool pci_ari_enabled(struct pci_bus *bus)
2714{
2715 return bus->self && bus->self->ari_enabled;
2716}
2717
2718/**
2719 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2720 * @pdev: PCI device to check
2721 *
2722 * Walk upwards from @pdev and check for each encountered bridge if it's part
2723 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2724 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2725 */
2726static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2727{
2728 struct pci_dev *parent = pdev;
2729
2730 if (pdev->is_thunderbolt)
2731 return true;
2732
2733 while ((parent = pci_upstream_bridge(parent)))
2734 if (parent->is_thunderbolt)
2735 return true;
2736
2737 return false;
2738}
2739
2740#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2741void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2742#endif
2743
2744#include <linux/dma-mapping.h>
2745
2746#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2747#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2748#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2749#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2750#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2751#define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg)
2752#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2753#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2754#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2755
2756#define pci_notice_ratelimited(pdev, fmt, arg...) \
2757 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2758
2759#define pci_info_ratelimited(pdev, fmt, arg...) \
2760 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2761
2762#define pci_WARN(pdev, condition, fmt, arg...) \
2763 WARN(condition, "%s %s: " fmt, \
2764 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2765
2766#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2767 WARN_ONCE(condition, "%s %s: " fmt, \
2768 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2769
2770#endif /* LINUX_PCI_H */
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