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1 | /* | |
2 | * Copyright 2008,2010 Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based (loosely) on the Linux code | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef _MMC_H_ | |
11 | #define _MMC_H_ | |
12 | ||
13 | #include <linux/list.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <part.h> | |
16 | ||
17 | #define SD_VERSION_SD 0x20000 | |
18 | #define SD_VERSION_3 (SD_VERSION_SD | 0x300) | |
19 | #define SD_VERSION_2 (SD_VERSION_SD | 0x200) | |
20 | #define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) | |
21 | #define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) | |
22 | #define MMC_VERSION_MMC 0x10000 | |
23 | #define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) | |
24 | #define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) | |
25 | #define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) | |
26 | #define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) | |
27 | #define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) | |
28 | #define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) | |
29 | #define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) | |
30 | #define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) | |
31 | #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) | |
32 | #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) | |
33 | #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) | |
34 | #define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500) | |
35 | ||
36 | #define MMC_MODE_HS (1 << 0) | |
37 | #define MMC_MODE_HS_52MHz (1 << 1) | |
38 | #define MMC_MODE_4BIT (1 << 2) | |
39 | #define MMC_MODE_8BIT (1 << 3) | |
40 | #define MMC_MODE_SPI (1 << 4) | |
41 | #define MMC_MODE_HC (1 << 5) | |
42 | #define MMC_MODE_DDR_52MHz (1 << 6) | |
43 | ||
44 | #define SD_DATA_4BIT 0x00040000 | |
45 | ||
46 | #define IS_SD(x) (x->version & SD_VERSION_SD) | |
47 | ||
48 | #define MMC_DATA_READ 1 | |
49 | #define MMC_DATA_WRITE 2 | |
50 | ||
51 | #define NO_CARD_ERR -16 /* No SD/MMC card inserted */ | |
52 | #define UNUSABLE_ERR -17 /* Unusable Card */ | |
53 | #define COMM_ERR -18 /* Communications Error */ | |
54 | #define TIMEOUT -19 | |
55 | #define IN_PROGRESS -20 /* operation is in progress */ | |
56 | #define SWITCH_ERR -21 /* Card reports failure to switch mode */ | |
57 | ||
58 | #define MMC_CMD_GO_IDLE_STATE 0 | |
59 | #define MMC_CMD_SEND_OP_COND 1 | |
60 | #define MMC_CMD_ALL_SEND_CID 2 | |
61 | #define MMC_CMD_SET_RELATIVE_ADDR 3 | |
62 | #define MMC_CMD_SET_DSR 4 | |
63 | #define MMC_CMD_SWITCH 6 | |
64 | #define MMC_CMD_SELECT_CARD 7 | |
65 | #define MMC_CMD_SEND_EXT_CSD 8 | |
66 | #define MMC_CMD_SEND_CSD 9 | |
67 | #define MMC_CMD_SEND_CID 10 | |
68 | #define MMC_CMD_STOP_TRANSMISSION 12 | |
69 | #define MMC_CMD_SEND_STATUS 13 | |
70 | #define MMC_CMD_SET_BLOCKLEN 16 | |
71 | #define MMC_CMD_READ_SINGLE_BLOCK 17 | |
72 | #define MMC_CMD_READ_MULTIPLE_BLOCK 18 | |
73 | #define MMC_CMD_SET_BLOCK_COUNT 23 | |
74 | #define MMC_CMD_WRITE_SINGLE_BLOCK 24 | |
75 | #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 | |
76 | #define MMC_CMD_ERASE_GROUP_START 35 | |
77 | #define MMC_CMD_ERASE_GROUP_END 36 | |
78 | #define MMC_CMD_ERASE 38 | |
79 | #define MMC_CMD_APP_CMD 55 | |
80 | #define MMC_CMD_SPI_READ_OCR 58 | |
81 | #define MMC_CMD_SPI_CRC_ON_OFF 59 | |
82 | #define MMC_CMD_RES_MAN 62 | |
83 | ||
84 | #define MMC_CMD62_ARG1 0xefac62ec | |
85 | #define MMC_CMD62_ARG2 0xcbaea7 | |
86 | ||
87 | ||
88 | #define SD_CMD_SEND_RELATIVE_ADDR 3 | |
89 | #define SD_CMD_SWITCH_FUNC 6 | |
90 | #define SD_CMD_SEND_IF_COND 8 | |
91 | ||
92 | #define SD_CMD_APP_SET_BUS_WIDTH 6 | |
93 | #define SD_CMD_ERASE_WR_BLK_START 32 | |
94 | #define SD_CMD_ERASE_WR_BLK_END 33 | |
95 | #define SD_CMD_APP_SEND_OP_COND 41 | |
96 | #define SD_CMD_APP_SEND_SCR 51 | |
97 | ||
98 | /* SCR definitions in different words */ | |
99 | #define SD_HIGHSPEED_BUSY 0x00020000 | |
100 | #define SD_HIGHSPEED_SUPPORTED 0x00020000 | |
101 | ||
102 | #define OCR_BUSY 0x80000000 | |
103 | #define OCR_HCS 0x40000000 | |
104 | #define OCR_VOLTAGE_MASK 0x007FFF80 | |
105 | #define OCR_ACCESS_MODE 0x60000000 | |
106 | ||
107 | #define SECURE_ERASE 0x80000000 | |
108 | ||
109 | #define MMC_STATUS_MASK (~0x0206BF7F) | |
110 | #define MMC_STATUS_SWITCH_ERROR (1 << 7) | |
111 | #define MMC_STATUS_RDY_FOR_DATA (1 << 8) | |
112 | #define MMC_STATUS_CURR_STATE (0xf << 9) | |
113 | #define MMC_STATUS_ERROR (1 << 19) | |
114 | ||
115 | #define MMC_STATE_PRG (7 << 9) | |
116 | ||
117 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ | |
118 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ | |
119 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
120 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
121 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
122 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
123 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
124 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
125 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
126 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
127 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
128 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
129 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
130 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
131 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
132 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
133 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
134 | ||
135 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ | |
136 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte | |
137 | addressed by index which are | |
138 | 1 in value field */ | |
139 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte | |
140 | addressed by index, which are | |
141 | 1 in value field */ | |
142 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ | |
143 | ||
144 | #define SD_SWITCH_CHECK 0 | |
145 | #define SD_SWITCH_SWITCH 1 | |
146 | ||
147 | /* | |
148 | * EXT_CSD fields | |
149 | */ | |
150 | #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ | |
151 | #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ | |
152 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ | |
153 | #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ | |
154 | #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ | |
155 | #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ | |
156 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ | |
157 | #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ | |
158 | #define EXT_CSD_RPMB_MULT 168 /* RO */ | |
159 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ | |
160 | #define EXT_CSD_BOOT_BUS_WIDTH 177 | |
161 | #define EXT_CSD_PART_CONF 179 /* R/W */ | |
162 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ | |
163 | #define EXT_CSD_HS_TIMING 185 /* R/W */ | |
164 | #define EXT_CSD_REV 192 /* RO */ | |
165 | #define EXT_CSD_CARD_TYPE 196 /* RO */ | |
166 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ | |
167 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ | |
168 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ | |
169 | #define EXT_CSD_BOOT_MULT 226 /* RO */ | |
170 | ||
171 | /* | |
172 | * EXT_CSD field definitions | |
173 | */ | |
174 | ||
175 | #define EXT_CSD_CMD_SET_NORMAL (1 << 0) | |
176 | #define EXT_CSD_CMD_SET_SECURE (1 << 1) | |
177 | #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) | |
178 | ||
179 | #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ | |
180 | #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ | |
181 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) | |
182 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) | |
183 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | |
184 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | |
185 | ||
186 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ | |
187 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | |
188 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ | |
189 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ | |
190 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ | |
191 | ||
192 | #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) | |
193 | #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) | |
194 | #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) | |
195 | #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) | |
196 | ||
197 | #define EXT_CSD_BOOT_ACK(x) (x << 6) | |
198 | #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) | |
199 | #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) | |
200 | ||
201 | #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) | |
202 | #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) | |
203 | #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) | |
204 | ||
205 | #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) | |
206 | ||
207 | #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ | |
208 | #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ | |
209 | ||
210 | #define R1_ILLEGAL_COMMAND (1 << 22) | |
211 | #define R1_APP_CMD (1 << 5) | |
212 | ||
213 | #define MMC_RSP_PRESENT (1 << 0) | |
214 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ | |
215 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ | |
216 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ | |
217 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ | |
218 | ||
219 | #define MMC_RSP_NONE (0) | |
220 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
221 | #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ | |
222 | MMC_RSP_BUSY) | |
223 | #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) | |
224 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) | |
225 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) | |
226 | #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
227 | #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
228 | #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
229 | ||
230 | #define MMCPART_NOAVAILABLE (0xff) | |
231 | #define PART_ACCESS_MASK (0x7) | |
232 | #define PART_SUPPORT (0x1) | |
233 | #define ENHNCD_SUPPORT (0x2) | |
234 | #define PART_ENH_ATTRIB (0x1f) | |
235 | ||
236 | /* Maximum block size for MMC */ | |
237 | #define MMC_MAX_BLOCK_LEN 512 | |
238 | ||
239 | /* The number of MMC physical partitions. These consist of: | |
240 | * boot partitions (2), general purpose partitions (4) in MMC v4.4. | |
241 | */ | |
242 | #define MMC_NUM_BOOT_PARTITION 2 | |
243 | #define MMC_PART_RPMB 3 /* RPMB partition number */ | |
244 | ||
245 | struct mmc_cid { | |
246 | unsigned long psn; | |
247 | unsigned short oid; | |
248 | unsigned char mid; | |
249 | unsigned char prv; | |
250 | unsigned char mdt; | |
251 | char pnm[7]; | |
252 | }; | |
253 | ||
254 | struct mmc_cmd { | |
255 | ushort cmdidx; | |
256 | uint resp_type; | |
257 | uint cmdarg; | |
258 | uint response[4]; | |
259 | }; | |
260 | ||
261 | struct mmc_data { | |
262 | union { | |
263 | char *dest; | |
264 | const char *src; /* src buffers don't get written to */ | |
265 | }; | |
266 | uint flags; | |
267 | uint blocks; | |
268 | uint blocksize; | |
269 | }; | |
270 | ||
271 | /* forward decl. */ | |
272 | struct mmc; | |
273 | ||
274 | struct mmc_ops { | |
275 | int (*send_cmd)(struct mmc *mmc, | |
276 | struct mmc_cmd *cmd, struct mmc_data *data); | |
277 | void (*set_ios)(struct mmc *mmc); | |
278 | int (*init)(struct mmc *mmc); | |
279 | int (*getcd)(struct mmc *mmc); | |
280 | int (*getwp)(struct mmc *mmc); | |
281 | }; | |
282 | ||
283 | struct mmc_config { | |
284 | const char *name; | |
285 | const struct mmc_ops *ops; | |
286 | uint host_caps; | |
287 | uint voltages; | |
288 | uint f_min; | |
289 | uint f_max; | |
290 | uint b_max; | |
291 | unsigned char part_type; | |
292 | }; | |
293 | ||
294 | /* TODO struct mmc should be in mmc_private but it's hard to fix right now */ | |
295 | struct mmc { | |
296 | struct list_head link; | |
297 | const struct mmc_config *cfg; /* provided configuration */ | |
298 | uint version; | |
299 | void *priv; | |
300 | uint has_init; | |
301 | int high_capacity; | |
302 | uint bus_width; | |
303 | uint clock; | |
304 | uint card_caps; | |
305 | uint ocr; | |
306 | uint dsr; | |
307 | uint dsr_imp; | |
308 | uint scr[2]; | |
309 | uint csd[4]; | |
310 | uint cid[4]; | |
311 | ushort rca; | |
312 | u8 part_support; | |
313 | u8 part_attr; | |
314 | char part_config; | |
315 | char part_num; | |
316 | uint tran_speed; | |
317 | uint read_bl_len; | |
318 | uint write_bl_len; | |
319 | uint erase_grp_size; /* in 512-byte sectors */ | |
320 | uint hc_wp_grp_size; /* in 512-byte sectors */ | |
321 | u64 capacity; | |
322 | u64 capacity_user; | |
323 | u64 capacity_boot; | |
324 | u64 capacity_rpmb; | |
325 | u64 capacity_gp[4]; | |
326 | u64 enh_user_start; | |
327 | u64 enh_user_size; | |
328 | block_dev_desc_t block_dev; | |
329 | char op_cond_pending; /* 1 if we are waiting on an op_cond command */ | |
330 | char init_in_progress; /* 1 if we have done mmc_start_init() */ | |
331 | char preinit; /* start init as early as possible */ | |
332 | uint op_cond_response; /* the response byte from the last op_cond */ | |
333 | int ddr_mode; | |
334 | }; | |
335 | ||
336 | struct mmc_hwpart_conf { | |
337 | struct { | |
338 | uint enh_start; /* in 512-byte sectors */ | |
339 | uint enh_size; /* in 512-byte sectors, if 0 no enh area */ | |
340 | } user; | |
341 | struct { | |
342 | uint size; /* in 512-byte sectors */ | |
343 | int enhanced; | |
344 | } gp_part[4]; | |
345 | }; | |
346 | ||
347 | enum mmc_hwpart_conf_mode { | |
348 | MMC_HWPART_CONF_CHECK, | |
349 | MMC_HWPART_CONF_SET, | |
350 | MMC_HWPART_CONF_COMPLETE, | |
351 | }; | |
352 | ||
353 | int mmc_register(struct mmc *mmc); | |
354 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); | |
355 | void mmc_destroy(struct mmc *mmc); | |
356 | int mmc_initialize(bd_t *bis); | |
357 | int mmc_init(struct mmc *mmc); | |
358 | int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); | |
359 | void mmc_set_clock(struct mmc *mmc, uint clock); | |
360 | struct mmc *find_mmc_device(int dev_num); | |
361 | int mmc_set_dev(int dev_num); | |
362 | void print_mmc_devices(char separator); | |
363 | int get_mmc_num(void); | |
364 | int mmc_switch_part(int dev_num, unsigned int part_num); | |
365 | int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, | |
366 | enum mmc_hwpart_conf_mode mode); | |
367 | int mmc_getcd(struct mmc *mmc); | |
368 | int board_mmc_getcd(struct mmc *mmc); | |
369 | int mmc_getwp(struct mmc *mmc); | |
370 | int board_mmc_getwp(struct mmc *mmc); | |
371 | int mmc_set_dsr(struct mmc *mmc, u16 val); | |
372 | /* Function to change the size of boot partition and rpmb partitions */ | |
373 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
374 | unsigned long rpmbsize); | |
375 | /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ | |
376 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); | |
377 | /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ | |
378 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); | |
379 | /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ | |
380 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); | |
381 | /* Functions to read / write the RPMB partition */ | |
382 | int mmc_rpmb_set_key(struct mmc *mmc, void *key); | |
383 | int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); | |
384 | int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, | |
385 | unsigned short cnt, unsigned char *key); | |
386 | int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, | |
387 | unsigned short cnt, unsigned char *key); | |
388 | /** | |
389 | * Start device initialization and return immediately; it does not block on | |
390 | * polling OCR (operation condition register) status. Then you should call | |
391 | * mmc_init, which would block on polling OCR status and complete the device | |
392 | * initializatin. | |
393 | * | |
394 | * @param mmc Pointer to a MMC device struct | |
395 | * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. | |
396 | */ | |
397 | int mmc_start_init(struct mmc *mmc); | |
398 | ||
399 | /** | |
400 | * Set preinit flag of mmc device. | |
401 | * | |
402 | * This will cause the device to be pre-inited during mmc_initialize(), | |
403 | * which may save boot time if the device is not accessed until later. | |
404 | * Some eMMC devices take 200-300ms to init, but unfortunately they | |
405 | * must be sent a series of commands to even get them to start preparing | |
406 | * for operation. | |
407 | * | |
408 | * @param mmc Pointer to a MMC device struct | |
409 | * @param preinit preinit flag value | |
410 | */ | |
411 | void mmc_set_preinit(struct mmc *mmc, int preinit); | |
412 | ||
413 | #ifdef CONFIG_GENERIC_MMC | |
414 | #ifdef CONFIG_MMC_SPI | |
415 | #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) | |
416 | #else | |
417 | #define mmc_host_is_spi(mmc) 0 | |
418 | #endif | |
419 | struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); | |
420 | #else | |
421 | int mmc_legacy_init(int verbose); | |
422 | #endif | |
423 | ||
424 | void board_mmc_power_init(void); | |
425 | int board_mmc_init(bd_t *bis); | |
426 | int cpu_mmc_init(bd_t *bis); | |
427 | int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); | |
428 | ||
429 | /* Set block count limit because of 16 bit register limit on some hardware*/ | |
430 | #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT | |
431 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 | |
432 | #endif | |
433 | ||
434 | #endif /* _MMC_H_ */ |