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1 | /* | |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * Keith Outwater, keith_outwater@mvis.com | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef _VIRTEX2_H_ | |
10 | #define _VIRTEX2_H_ | |
11 | ||
12 | #include <xilinx.h> | |
13 | ||
14 | /* | |
15 | * Slave SelectMap Implementation function table. | |
16 | */ | |
17 | typedef struct { | |
18 | xilinx_pre_fn pre; | |
19 | xilinx_pgm_fn pgm; | |
20 | xilinx_init_fn init; | |
21 | xilinx_err_fn err; | |
22 | xilinx_done_fn done; | |
23 | xilinx_clk_fn clk; | |
24 | xilinx_cs_fn cs; | |
25 | xilinx_wr_fn wr; | |
26 | xilinx_rdata_fn rdata; | |
27 | xilinx_wdata_fn wdata; | |
28 | xilinx_busy_fn busy; | |
29 | xilinx_abort_fn abort; | |
30 | xilinx_post_fn post; | |
31 | } xilinx_virtex2_slave_selectmap_fns; | |
32 | ||
33 | /* Slave Serial Implementation function table */ | |
34 | typedef struct { | |
35 | xilinx_pgm_fn pgm; | |
36 | xilinx_clk_fn clk; | |
37 | xilinx_rdata_fn rdata; | |
38 | xilinx_wdata_fn wdata; | |
39 | } xilinx_virtex2_slave_serial_fns; | |
40 | ||
41 | #if defined(CONFIG_FPGA_VIRTEX2) | |
42 | extern struct xilinx_fpga_op virtex2_op; | |
43 | # define FPGA_VIRTEX2_OPS &virtex2_op | |
44 | #else | |
45 | # define FPGA_VIRTEX2_OPS NULL | |
46 | #endif | |
47 | ||
48 | /* Device Image Sizes (in bytes) | |
49 | *********************************************************************/ | |
50 | #define XILINX_XC2V40_SIZE (338208 / 8) | |
51 | #define XILINX_XC2V80_SIZE (597408 / 8) | |
52 | #define XILINX_XC2V250_SIZE (1591584 / 8) | |
53 | #define XILINX_XC2V500_SIZE (2557857 / 8) | |
54 | #define XILINX_XC2V1000_SIZE (3749408 / 8) | |
55 | #define XILINX_XC2V1500_SIZE (5166240 / 8) | |
56 | #define XILINX_XC2V2000_SIZE (6808352 / 8) | |
57 | #define XILINX_XC2V3000_SIZE (9589408 / 8) | |
58 | #define XILINX_XC2V4000_SIZE (14220192 / 8) | |
59 | #define XILINX_XC2V6000_SIZE (19752096 / 8) | |
60 | #define XILINX_XC2V8000_SIZE (26185120 / 8) | |
61 | #define XILINX_XC2V10000_SIZE (33519264 / 8) | |
62 | ||
63 | /* Descriptor Macros | |
64 | *********************************************************************/ | |
65 | #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ | |
66 | { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ | |
67 | FPGA_VIRTEX2_OPS } | |
68 | ||
69 | #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ | |
70 | { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ | |
71 | FPGA_VIRTEX2_OPS } | |
72 | ||
73 | #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ | |
74 | { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ | |
75 | FPGA_VIRTEX2_OPS } | |
76 | ||
77 | #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ | |
78 | { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ | |
79 | FPGA_VIRTEX2_OPS } | |
80 | ||
81 | #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ | |
82 | { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ | |
83 | FPGA_VIRTEX2_OPS } | |
84 | ||
85 | #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ | |
86 | { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ | |
87 | FPGA_VIRTEX2_OPS } | |
88 | ||
89 | #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ | |
90 | { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ | |
91 | FPGA_VIRTEX2_OPS } | |
92 | ||
93 | #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ | |
94 | { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ | |
95 | FPGA_VIRTEX2_OPS } | |
96 | ||
97 | #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ | |
98 | { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ | |
99 | FPGA_VIRTEX2_OPS } | |
100 | ||
101 | #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ | |
102 | { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ | |
103 | FPGA_VIRTEX2_OPS } | |
104 | ||
105 | #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ | |
106 | { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ | |
107 | FPGA_VIRTEX2_OPS } | |
108 | ||
109 | #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ | |
110 | { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ | |
111 | FPGA_VIRTEX2_OPS } | |
112 | ||
113 | #endif /* _VIRTEX2_H_ */ |