Bindings/arm/pmu.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM Performance Monitor Units
   8
   9 maintainers:
  10   - Mark Rutland <mark.rutland@arm.com>
  11   - Will Deacon <will.deacon@arm.com>
  12
  13 description: |+
  14   ARM cores often have a PMU for counting cpu and cache events like cache misses
  15   and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
  16   representation in the device tree should be done as under:-
  17
  18 properties:
  19   compatible:
  20     items:
  21       - enum:
  22           - apm,potenza-pmu
  23           - apple,avalanche-pmu
  24           - apple,blizzard-pmu
  25           - apple,firestorm-pmu
  26           - apple,icestorm-pmu
  27           - arm,armv8-pmuv3 # Only for s/w models
  28           - arm,arm1136-pmu
  29           - arm,arm1176-pmu
  30           - arm,arm11mpcore-pmu
  31           - arm,cortex-a5-pmu
  32           - arm,cortex-a7-pmu
  33           - arm,cortex-a8-pmu
  34           - arm,cortex-a9-pmu
  35           - arm,cortex-a12-pmu
  36           - arm,cortex-a15-pmu
  37           - arm,cortex-a17-pmu
  38           - arm,cortex-a32-pmu
  39           - arm,cortex-a34-pmu
  40           - arm,cortex-a35-pmu
  41           - arm,cortex-a53-pmu
  42           - arm,cortex-a55-pmu
  43           - arm,cortex-a57-pmu
  44           - arm,cortex-a65-pmu
  45           - arm,cortex-a72-pmu
  46           - arm,cortex-a73-pmu
  47           - arm,cortex-a75-pmu
  48           - arm,cortex-a76-pmu
  49           - arm,cortex-a77-pmu
  50           - arm,cortex-a78-pmu
  51           - arm,cortex-a510-pmu
  52           - arm,cortex-a520-pmu
  53           - arm,cortex-a710-pmu
  54           - arm,cortex-a715-pmu
  55           - arm,cortex-a720-pmu
  56           - arm,cortex-x1-pmu
  57           - arm,cortex-x2-pmu
  58           - arm,cortex-x3-pmu
  59           - arm,cortex-x4-pmu
  60           - arm,neoverse-e1-pmu
  61           - arm,neoverse-n1-pmu
  62           - arm,neoverse-n2-pmu
  63           - arm,neoverse-v1-pmu
  64           - brcm,vulcan-pmu
  65           - cavium,thunder-pmu
  66           - nvidia,denver-pmu
  67           - nvidia,carmel-pmu
  68           - qcom,krait-pmu
  69           - qcom,scorpion-pmu
  70           - qcom,scorpion-mp-pmu
  71
  72   interrupts:
  73     # Don't know how many CPUs, so no constraints to specify
  74     description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
  75
  76   interrupt-affinity:
  77     $ref: /schemas/types.yaml#/definitions/phandle-array
  78     items:
  79       maxItems: 1
  80     description:
  81       When using SPIs, specifies a list of phandles to CPU
  82       nodes corresponding directly to the affinity of
  83       the SPIs listed in the interrupts property.
  84
  85       When using a PPI, specifies a list of phandles to CPU
  86       nodes corresponding to the set of CPUs which have
  87       a PMU of this type signalling the PPI listed in the
  88       interrupts property, unless this is already specified
  89       by the PPI interrupt specifier itself (in which case
  90       the interrupt-affinity property shouldn't be present).
  91
  92       This property should be present when there is more than
  93       a single SPI.
  94
  95   qcom,no-pc-write:
  96     type: boolean
  97     description:
  98       Indicates that this PMU doesn't support the 0xc and 0xd events.
  99
 100   secure-reg-access:
 101     type: boolean
 102     description:
 103       Indicates that the ARMv7 Secure Debug Enable Register
 104       (SDER) is accessible. This will cause the driver to do
 105       any setup required that is only possible in ARMv7 secure
 106       state. If not present the ARMv7 SDER will not be touched,
 107       which means the PMU may fail to operate unless external
 108       code (bootloader or security monitor) has performed the
 109       appropriate initialisation. Note that this property is
 110       not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
 111       in Non-secure state.
 112
 113 required:
 114   - compatible
 115
 116 additionalProperties: false
 117
 118 ...