Bindings/clock/mediatek,mt7988-xfi-pll.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek MT7988 XFI PLL Clock Controller
   8
   9 maintainers:
  10   - Daniel Golle <daniel@makrotopia.org>
  11
  12 description:
  13   The MediaTek XFI PLL controller provides the 156.25MHz clock for the
  14   Ethernet SerDes PHY from the 40MHz top_xtal clock.
  15
  16 properties:
  17   compatible:
  18     const: mediatek,mt7988-xfi-pll
  19
  20   reg:
  21     maxItems: 1
  22
  23   resets:
  24     maxItems: 1
  25
  26   '#clock-cells':
  27     const: 1
  28
  29 required:
  30   - compatible
  31   - reg
  32   - resets
  33   - '#clock-cells'
  34
  35 additionalProperties: false
  36
  37 examples:
  38   - |
  39     soc {
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         clock-controller@11f40000 {
  43             compatible = "mediatek,mt7988-xfi-pll";
  44             reg = <0 0x11f40000 0 0x1000>;
  45             resets = <&watchdog 16>;
  46             #clock-cells = <1>;
  47         };
  48     };