1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock Controller on SM6125
10 - Martin Botka <martin.botka@somainline.org>
13 Qualcomm display clock control module provides the clocks and power domains
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
25 - description: Board XO source
26 - description: Byte clock from DSI PHY0
27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1
29 - description: Link clock from DP PHY
30 - description: VCO DIV clock from DP PHY
31 - description: AHB config clock from GCC
32 - description: GPLL0 div source from GCC
37 - const: dsi0_phy_pll_out_byteclk
38 - const: dsi0_phy_pll_out_dsiclk
39 - const: dsi1_phy_pll_out_dsiclk
40 - const: dp_phy_pll_link_clk
41 - const: dp_phy_pll_vco_div_clk
43 - const: gcc_disp_gpll0_div_clk_src
48 '#power-domain-cells':
53 A phandle and PM domain specifier for the CX power domain.
58 A phandle to an OPP node describing the power domain's performance point.
70 - '#power-domain-cells'
72 additionalProperties: false
76 #include <dt-bindings/clock/qcom,rpmcc.h>
77 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
78 #include <dt-bindings/power/qcom-rpmpd.h>
79 clock-controller@5f00000 {
80 compatible = "qcom,sm6125-dispcc";
81 reg = <0x5f00000 0x20000>;
83 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
89 <&gcc GCC_DISP_AHB_CLK>,
90 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
91 clock-names = "bi_tcxo",
92 "dsi0_phy_pll_out_byteclk",
93 "dsi0_phy_pll_out_dsiclk",
94 "dsi1_phy_pll_out_dsiclk",
95 "dp_phy_pll_link_clk",
96 "dp_phy_pll_vco_div_clk",
98 "gcc_disp_gpll0_div_clk_src";
100 required-opps = <&rpmhpd_opp_ret>;
101 power-domains = <&rpmpd SM6125_VDDCX>;
104 #power-domain-cells = <1>;