Bindings/clock/qcom,sm8550-gcc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Global Clock & Reset Controller on SM8550
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description: |
  13   Qualcomm global clock control module provides the clocks, resets and power
  14   domains on SM8550
  15
  16   See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm8550-gcc
  21
  22   clocks:
  23     items:
  24       - description: Board XO source
  25       - description: Sleep clock source
  26       - description: PCIE 0 Pipe clock source
  27       - description: PCIE 1 Pipe clock source
  28       - description: PCIE 1 Phy Auxiliary clock source
  29       - description: UFS Phy Rx symbol 0 clock source
  30       - description: UFS Phy Rx symbol 1 clock source
  31       - description: UFS Phy Tx symbol 0 clock source
  32       - description: USB3 Phy wrapper pipe clock source
  33
  34 required:
  35   - compatible
  36   - clocks
  37
  38 allOf:
  39   - $ref: qcom,gcc.yaml#
  40
  41 unevaluatedProperties: false
  42
  43 examples:
  44   - |
  45     #include <dt-bindings/clock/qcom,rpmh.h>
  46     clock-controller@100000 {
  47       compatible = "qcom,sm8550-gcc";
  48       reg = <0x00100000 0x001f4200>;
  49       clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
  50                <&pcie0_phy>,
  51                <&pcie1_phy>,
  52                <&pcie_1_phy_aux_clk>,
  53                <&ufs_mem_phy 0>,
  54                <&ufs_mem_phy 1>,
  55                <&ufs_mem_phy 2>,
  56                <&usb_1_qmpphy>;
  57       #clock-cells = <1>;
  58       #reset-cells = <1>;
  59       #power-domain-cells = <1>;
  60     };
  61
  62 ...