Bindings/clock/silabs,si5341.txt

   1 Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
   2 i2c clock generator.
   3
   4 Reference
   5 [1] Si5341 Data Sheet
   6     https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
   7 [2] Si5341 Reference Manual
   8     https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
   9 [3] Si5345 Reference Manual
  10     https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
  11
  12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
  13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
  14 in turn can be directed to any of the 10 (or 4) outputs through a divider.
  15 The internal structure of the clock generators can be found in [2].
  16 The Si5345 is similar to the Si5341 with the addition of fractional input
  17 dividers and automatic input selection, as described in [3].
  18 The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
  19
  20 The driver can be used in "as is" mode, reading the current settings from the
  21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
  22 configured when the driver probes, it assumes the driver must fully initialize
  23 it.
  24
  25 The device type, speed grade and revision are determined runtime by probing.
  26
  27 The driver currently does not support any fancy input configurations. They can
  28 still be programmed into the chip and the driver will leave them "as is".
  29
  30 ==I2C device node==
  31
  32 Required properties:
  33 - compatible: shall be one of the following:
  34         "silabs,si5340" - Si5340 A/B/C/D
  35         "silabs,si5341" - Si5341 A/B/C/D
  36         "silabs,si5342" - Si5342 A/B/C/D
  37         "silabs,si5344" - Si5344 A/B/C/D
  38         "silabs,si5345" - Si5345 A/B/C/D
  39 - reg: i2c device address, usually 0x74
  40 - #clock-cells: from common clock binding; shall be set to 2.
  41         The first value is "0" for outputs, "1" for synthesizers.
  42         The second value is the output or synthesizer index.
  43 - clocks: from common clock binding; list of parent clock  handles,
  44         corresponding to inputs. Use a fixed clock for the "xtal" input.
  45         At least one must be present.
  46 - clock-names: One of: "xtal", "in0", "in1", "in2"
  47
  48 Optional properties:
  49 - vdd-supply: Regulator node for VDD
  50 - vdda-supply: Regulator node for VDDA
  51 - vdds-supply: Regulator node for VDDS
  52 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
  53   feedback divider. Must be such that the PLL output is in the valid range. For
  54   example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
  55   the fraction matters, using 3500 and 12 will deliver the exact same result.
  56   If these are not specified, and the PLL is not yet programmed when the driver
  57   probes, the PLL will be set to 14GHz.
  58 - silabs,reprogram: When present, the driver will always assume the device must
  59   be initialized, and always performs the soft-reset routine. Since this will
  60   temporarily stop all output clocks, don't do this if the chip is generating
  61   the CPU clock for example.
  62 - silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
  63   in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
  64 - interrupts: Interrupt for INTRb pin.
  65 - silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
  66   rather than 1.8V thresholds.
  67 - vddoX-supply (where X is an output index): Regulator node for VDDO for the
  68   specified output. The driver selects the output VDD_SEL setting based on this
  69   voltage.
  70 - #address-cells: shall be set to 1.
  71 - #size-cells: shall be set to 0.
  72
  73
  74 == Child nodes: Outputs ==
  75
  76 The child nodes list the output clocks.
  77
  78 Each of the clock outputs can be overwritten individually by using a child node.
  79 If a child node for a clock output is not set, the configuration remains
  80 unchanged.
  81
  82 Required child node properties:
  83 - reg: number of clock output.
  84
  85 Optional child node properties:
  86 - silabs,format: Output format, one of:
  87         1 = differential (defaults to LVDS levels)
  88         2 = low-power (defaults to HCSL levels)
  89         4 = LVCMOS
  90 - silabs,common-mode: Manually override output common mode, see [2] for values
  91 - silabs,amplitude: Manually override output amplitude, see [2] for values
  92 - silabs,synth-master: boolean. If present, this output is allowed to change the
  93         multisynth frequency dynamically.
  94 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
  95         when disabled, otherwise it's driven LOW.
  96
  97 ==Example==
  98
  99 /* 48MHz reference crystal */
 100 ref48: ref48M {
 101         compatible = "fixed-clock";
 102         #clock-cells = <0>;
 103         clock-frequency = <48000000>;
 104 };
 105
 106 i2c-master-node {
 107         /* Programmable clock (for logic) */
 108         si5341: clock-generator@74 {
 109                 reg = <0x74>;
 110                 compatible = "silabs,si5341";
 111                 #clock-cells = <2>;
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114                 clocks = <&ref48>;
 115                 clock-names = "xtal";
 116
 117                 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
 118                 silabs,pll-m-den = <48>;
 119                 silabs,reprogram; /* Chips are not programmed, always reset */
 120
 121                 out@0 {
 122                         reg = <0>;
 123                         silabs,format = <1>; /* LVDS 3v3 */
 124                         silabs,common-mode = <3>;
 125                         silabs,amplitude = <3>;
 126                         silabs,synth-master;
 127                 };
 128
 129                 /*
 130                  * Output 6 configuration:
 131                  *  LVDS 1v8
 132                  */
 133                 out@6 {
 134                         reg = <6>;
 135                         silabs,format = <1>; /* LVDS 1v8 */
 136                         silabs,common-mode = <13>;
 137                         silabs,amplitude = <3>;
 138                 };
 139
 140                 /*
 141                  * Output 8 configuration:
 142                  *  HCSL 3v3
 143                  */
 144                 out@8 {
 145                         reg = <8>;
 146                         silabs,format = <2>;
 147                         silabs,common-mode = <11>;
 148                         silabs,amplitude = <3>;
 149                 };
 150         };
 151 };
 152
 153 some-video-node {
 154         /* Standard clock bindings */
 155         clock-names = "pixel";
 156         clocks = <&si5341 0 7>; /* Output 7 */
 157
 158         /* Set output 7 to use syntesizer 3 as its parent */
 159         assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
 160         assigned-clock-parents = <&si5341 1 3>;
 161         /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
 162         assigned-clock-rates = <148500000>, <594000000>;
 163 };
 164
 165 some-audio-node {
 166         clock-names = "i2s-clk";
 167         clocks = <&si5341 0 0>;
 168         /*
 169          * since output 0 is a synth-master, the synth will be automatically set
 170          * to an appropriate frequency when the audio driver requests another
 171          * frequency. We give control over synth 2 to this output here.
 172          */
 173         assigned-clocks = <&si5341 0 0>;
 174         assigned-clock-parents = <&si5341 1 2>;
 175 };