1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments LMK04832 Clock Controller
10 - Liam Beguin <liambeguin@gmail.com>
13 Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
14 support. The LMK04832 is pin compatible with the LMK0482x family.
16 Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
40 - description: PLL2 reference clock.
51 Select SPI 4wire readback pin configuration.
52 Available readback pins are,
56 $ref: /schemas/types.yaml#/definitions/uint32
61 description: Optional to set VCO frequency of the PLL in Hertz.
64 description: SYSREF digital delay value.
65 $ref: /schemas/types.yaml#/definitions/uint32
72 SYSREF Mux configuration.
73 Available options are,
78 $ref: /schemas/types.yaml#/definitions/uint32
83 description: SYNC pin configuration.
84 $ref: /schemas/types.yaml#/definitions/uint32
88 ti,sysref-pulse-count:
90 Number of SYSREF pulses to send when SYSREF is not in continuous mode.
91 $ref: /schemas/types.yaml#/definitions/uint32
99 Child nodes used to configure output clocks.
104 clock output identifier.
111 Available options are,
122 CMOS (Off/Inverted) 0x0a
123 CMOS (Normal/Off) 0x0b
124 CMOS (Inverted/Inverted) 0x0c
125 CMOS (Inverted/Normal) 0x0d
126 CMOS (Normal/Inverted) 0x0e
127 CMOS (Normal/Normal) 0x0f
128 $ref: /schemas/types.yaml#/definitions/uint32
134 Select SYSREF clock path for output clock.
140 additionalProperties: false
149 additionalProperties: false
154 lmk04832_oscin: oscin {
155 compatible = "fixed-clock";
158 clock-frequency = <122880000>;
159 clock-output-names = "lmk04832-oscin";
164 #address-cells = <1>;
167 lmk04832: clock-controller@0 {
168 #address-cells = <1>;
173 compatible = "ti,lmk04832";
174 spi-max-frequency = <781250>;
176 reset-gpios = <&gpio_lmk 0 0 0>;
179 clocks = <&lmk04832_oscin>;
180 clock-names = "oscin";
182 ti,spi-4wire-rdbk = <0>;
183 ti,vco-hz = <2457600000>;
186 <&lmk04832 0>, <&lmk04832 1>,
187 <&lmk04832 2>, <&lmk04832 3>,
189 <&lmk04832 6>, <&lmk04832 7>,
190 <&lmk04832 10>, <&lmk04832 11>;
191 assigned-clock-rates =
192 <122880000>, <384000>,
193 <122880000>, <384000>,
195 <153600000>, <384000>,
196 <614400000>, <384000>;
200 ti,clkout-fmt = <0x01>; // LVDS
205 ti,clkout-fmt = <0x01>; // LVDS