Bindings/clock/xlnx,clocking-wizard.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Xilinx clocking wizard
   8
   9 maintainers:
  10   - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
  11
  12 description:
  13   The clocking wizard is a soft ip clocking block of Xilinx versal. It
  14   reads required input clock frequencies from the devicetree and acts as clock
  15   clock output.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - xlnx,clocking-wizard
  21       - xlnx,clocking-wizard-v5.2
  22       - xlnx,clocking-wizard-v6.0
  23
  24
  25   reg:
  26     maxItems: 1
  27
  28   "#clock-cells":
  29     const: 1
  30
  31   clocks:
  32     items:
  33       - description: clock input
  34       - description: axi clock
  35
  36   clock-names:
  37     items:
  38       - const: clk_in1
  39       - const: s_axi_aclk
  40
  41
  42   xlnx,speed-grade:
  43     $ref: /schemas/types.yaml#/definitions/uint32
  44     enum: [1, 2, 3]
  45     description:
  46       Speed grade of the device. Higher the speed grade faster is the FPGA device.
  47
  48   xlnx,nr-outputs:
  49     $ref: /schemas/types.yaml#/definitions/uint32
  50     minimum: 1
  51     maximum: 8
  52     description:
  53       Number of outputs.
  54
  55 required:
  56   - compatible
  57   - reg
  58   - "#clock-cells"
  59   - clocks
  60   - clock-names
  61   - xlnx,speed-grade
  62   - xlnx,nr-outputs
  63
  64 additionalProperties: false
  65
  66 examples:
  67   - |
  68     clock-controller@b0000000  {
  69         compatible = "xlnx,clocking-wizard";
  70         reg = <0xb0000000 0x10000>;
  71         #clock-cells = <1>;
  72         xlnx,speed-grade = <1>;
  73         xlnx,nr-outputs = <6>;
  74         clock-names = "clk_in1", "s_axi_aclk";
  75         clocks = <&clkc 15>, <&clkc 15>;
  76     };
  77 ...