1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
15 each IP. PPMU provides the primitive values to get performance data. These
16 PPMU events provide information of the SoC's behaviors so that you may use to
17 analyze system performance, to make behaviors visible and to count usages of
18 each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The
19 Exynos PPMU driver uses the devfreq-event class to provide event data to
20 various devfreq devices. The devfreq devices would use the event data when
21 determining the current state of each IP.
27 - samsung,exynos-ppmu-v2
43 '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
48 The unique event name among PPMU device
49 $ref: /schemas/types.yaml#/definitions/string
53 Define the type of data which shell be counted by the counter.
54 You can check include/dt-bindings/pmu/exynos_ppmu.h for all
55 possible type, i.e. count read requests, count write data in
56 bytes, etc. This field is optional and when it is missing, the
57 driver code will use default data type.
58 $ref: /schemas/types.yaml#/definitions/uint32
63 additionalProperties: false
65 additionalProperties: false
71 additionalProperties: false
75 // PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
76 #include <dt-bindings/clock/exynos3250.h>
78 ppmu_dmc0: ppmu@106a0000 {
79 compatible = "samsung,exynos-ppmu";
80 reg = <0x106a0000 0x2000>;
83 ppmu_dmc0_3: ppmu-event3-dmc0 {
84 event-name = "ppmu-event3-dmc0";
87 ppmu_dmc0_2: ppmu-event2-dmc0 {
88 event-name = "ppmu-event2-dmc0";
91 ppmu_dmc0_1: ppmu-event1-dmc0 {
92 event-name = "ppmu-event1-dmc0";
95 ppmu_dmc0_0: ppmu-event0-dmc0 {
96 event-name = "ppmu-event0-dmc0";
101 ppmu_rightbus: ppmu@112a0000 {
102 compatible = "samsung,exynos-ppmu";
103 reg = <0x112a0000 0x2000>;
104 clocks = <&cmu CLK_PPMURIGHT>;
105 clock-names = "ppmu";
108 ppmu_rightbus_3: ppmu-event3-rightbus {
109 event-name = "ppmu-event3-rightbus";
115 // PPMUv2 nodes in Exynos5433
116 ppmu_d0_cpu: ppmu@10480000 {
117 compatible = "samsung,exynos-ppmu-v2";
118 reg = <0x10480000 0x2000>;
121 ppmu_d0_general: ppmu@10490000 {
122 compatible = "samsung,exynos-ppmu-v2";
123 reg = <0x10490000 0x2000>;
126 ppmu_event0_d0_general: ppmu-event0-d0-general {
127 event-name = "ppmu-event0-d0-general";
132 ppmu_d0_rt: ppmu@104a0000 {
133 compatible = "samsung,exynos-ppmu-v2";
134 reg = <0x104a0000 0x2000>;
137 ppmu_d1_cpu: ppmu@104b0000 {
138 compatible = "samsung,exynos-ppmu-v2";
139 reg = <0x104b0000 0x2000>;
142 ppmu_d1_general: ppmu@104c0000 {
143 compatible = "samsung,exynos-ppmu-v2";
144 reg = <0x104c0000 0x2000>;
147 ppmu_d1_rt: ppmu@104d0000 {
148 compatible = "samsung,exynos-ppmu-v2";
149 reg = <0x104d0000 0x2000>;
153 // PPMUv1 nodes with event-data-type for Exynos4412
154 #include <dt-bindings/pmu/exynos_ppmu.h>
157 compatible = "samsung,exynos-ppmu";
158 reg = <0x106a0000 0x2000>;
159 clocks = <&clock 400>;
160 clock-names = "ppmu";
164 event-name = "ppmu-event3-dmc0";
165 event-data-type = <(PPMU_RO_DATA_CNT |