Bindings/display/arm,pl11x.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Arm PrimeCell Color LCD Controller PL110/PL111
   8
   9 maintainers:
  10   - Liviu Dudau <Liviu.Dudau@arm.com>
  11   - Andre Przywara <andre.przywara@arm.com>
  12
  13 description:
  14   The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
  15   a framebuffer region in system memory, and creates timed signals for
  16   a variety of LCD panels.
  17
  18 # We need a select here so we don't match all nodes with 'arm,primecell'
  19 select:
  20   properties:
  21     compatible:
  22       contains:
  23         enum:
  24           - arm,pl110
  25           - arm,pl111
  26   required:
  27     - compatible
  28
  29 properties:
  30   compatible:
  31     items:
  32       - enum:
  33           - arm,pl110
  34           - arm,pl111
  35       - const: arm,primecell
  36
  37   reg:
  38     maxItems: 1
  39
  40   interrupt-names:
  41     oneOf:
  42       - const: combined
  43         description:
  44           The IP provides four individual interrupt lines, but also one
  45           combined line. If the integration only connects this line to the
  46           interrupt controller, this single interrupt is noted here.
  47       - items:
  48           - const: mbe        # CLCDMBEINTR
  49           - const: vcomp      # CLCDVCOMPINTR
  50           - const: lnbu       # CLCDLNBUINTR
  51           - const: fuf        # CLCDFUFINTR
  52
  53   interrupts:
  54     minItems: 1
  55     maxItems: 4
  56
  57   clock-names:
  58     items:
  59       - const: clcdclk
  60       - const: apb_pclk
  61
  62   clocks:
  63     items:
  64       - description: The CLCDCLK reference clock for the controller.
  65       - description: The HCLK AHB slave clock for the register access.
  66
  67   memory-region:
  68     maxItems: 1
  69     description:
  70       Phandle to a node describing memory to be used for the framebuffer.
  71       If not present, the framebuffer may be located anywhere in memory.
  72
  73   max-memory-bandwidth:
  74     $ref: /schemas/types.yaml#/definitions/uint32
  75     description:
  76       Maximum bandwidth in bytes per second that the cell's memory interface
  77       can handle.
  78       If not present, the memory interface is fast enough to handle all
  79       possible video modes.
  80
  81   port:
  82     $ref: /schemas/graph.yaml#/$defs/port-base
  83     additionalProperties: false
  84
  85     description:
  86       Output endpoint of the controller, connecting the LCD panel signals.
  87
  88     properties:
  89       endpoint:
  90         $ref: /schemas/graph.yaml#/$defs/endpoint-base
  91         unevaluatedProperties: false
  92
  93         properties:
  94           arm,pl11x,tft-r0g0b0-pads:
  95             $ref: /schemas/types.yaml#/definitions/uint32-array
  96             items:
  97               - description: index of CLD pad used for first red bit (R0)
  98               - description: index of CLD pad used for first green bit (G0)
  99               - description: index of CLD pad used for first blue bit (G0)
 100             deprecated: true
 101             description: |
 102               DEPRECATED. An array of three 32-bit values, defining the way
 103               CLD[23:0] pads are wired up.
 104               The first value contains the index of the "CLD" external pin (pad)
 105               used as R0 (first bit of the red component), the second value for
 106               green, the third value for blue.
 107               See also "LCD panel signal multiplexing details" paragraphs in the
 108               PL110/PL111 Technical Reference Manuals.
 109               This implicitly defines available color modes, for example:
 110               - PL111 TFT 4:4:4 panel:
 111                   arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
 112               - PL110 TFT (1:)5:5:5 panel:
 113                   arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
 114               - PL111 TFT (1:)5:5:5 panel:
 115                   arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
 116               - PL111 TFT 5:6:5 panel:
 117                   arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
 118               - PL110 and PL111 TFT 8:8:8 panel:
 119                   arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 120               - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
 121                   arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
 122
 123 additionalProperties: false
 124
 125 required:
 126   - compatible
 127   - reg
 128   - clock-names
 129   - clocks
 130   - port
 131
 132 allOf:
 133   - if:
 134       properties:
 135         interrupts:
 136           minItems: 2
 137       required:
 138         - interrupts
 139     then:
 140       required:
 141         - interrupt-names
 142
 143 examples:
 144   - |
 145     clcd@10020000 {
 146         compatible = "arm,pl111", "arm,primecell";
 147         reg = <0x10020000 0x1000>;
 148         interrupt-names = "combined";
 149         interrupts = <44>;
 150         clocks = <&oscclk1>, <&oscclk2>;
 151         clock-names = "clcdclk", "apb_pclk";
 152         max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
 153
 154         port {
 155             clcd_pads: endpoint {
 156                 remote-endpoint = <&clcd_panel>;
 157             };
 158         };
 159     };
 160
 161     panel {
 162         compatible = "arm,rtsm-display";
 163
 164         port {
 165             clcd_panel: endpoint {
 166                 remote-endpoint = <&clcd_pads>;
 167             };
 168         };
 169     };
 170 ...