Bindings/display/msm/dp-controller.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MSM Display Port Controller
   8
   9 maintainers:
  10   - Kuogee Hsieh <quic_khsieh@quicinc.com>
  11
  12 description: |
  13   Device tree bindings for DisplayPort host controller for MSM targets
  14   that are compatible with VESA DisplayPort interface specification.
  15
  16 properties:
  17   compatible:
  18     oneOf:
  19       - enum:
  20           - qcom,sc7180-dp
  21           - qcom,sc7280-dp
  22           - qcom,sc7280-edp
  23           - qcom,sc8180x-dp
  24           - qcom,sc8180x-edp
  25           - qcom,sc8280xp-dp
  26           - qcom,sc8280xp-edp
  27           - qcom,sdm845-dp
  28           - qcom,sm8350-dp
  29       - items:
  30           - enum:
  31               - qcom,sm8250-dp
  32               - qcom,sm8450-dp
  33               - qcom,sm8550-dp
  34           - const: qcom,sm8350-dp
  35
  36   reg:
  37     minItems: 4
  38     items:
  39       - description: ahb register block
  40       - description: aux register block
  41       - description: link register block
  42       - description: p0 register block
  43       - description: p1 register block
  44
  45   interrupts:
  46     maxItems: 1
  47
  48   clocks:
  49     items:
  50       - description: AHB clock to enable register access
  51       - description: Display Port AUX clock
  52       - description: Display Port Link clock
  53       - description: Link interface clock between DP and PHY
  54       - description: Display Port Pixel clock
  55
  56   clock-names:
  57     items:
  58       - const: core_iface
  59       - const: core_aux
  60       - const: ctrl_link
  61       - const: ctrl_link_iface
  62       - const: stream_pixel
  63
  64   assigned-clocks:
  65     items:
  66       - description: link clock source
  67       - description: pixel clock source
  68
  69   assigned-clock-parents:
  70     items:
  71       - description: phy 0 parent
  72       - description: phy 1 parent
  73
  74   phys:
  75     maxItems: 1
  76
  77   phy-names:
  78     items:
  79       - const: dp
  80
  81   operating-points-v2: true
  82
  83   opp-table:
  84     type: object
  85
  86   power-domains:
  87     maxItems: 1
  88
  89   aux-bus:
  90     $ref: /schemas/display/dp-aux-bus.yaml#
  91
  92   data-lanes:
  93     $ref: /schemas/types.yaml#/definitions/uint32-array
  94     deprecated: true
  95     minItems: 1
  96     maxItems: 4
  97     items:
  98       maximum: 3
  99
 100   "#sound-dai-cells":
 101     const: 0
 102
 103   vdda-0p9-supply:
 104     deprecated: true
 105   vdda-1p2-supply:
 106     deprecated: true
 107
 108   ports:
 109     $ref: /schemas/graph.yaml#/properties/ports
 110     properties:
 111       port@0:
 112         $ref: /schemas/graph.yaml#/properties/port
 113         description: Input endpoint of the controller
 114
 115       port@1:
 116         $ref: /schemas/graph.yaml#/$defs/port-base
 117         unevaluatedProperties: false
 118         description: Output endpoint of the controller
 119         properties:
 120           endpoint:
 121             $ref: /schemas/media/video-interfaces.yaml#
 122             unevaluatedProperties: false
 123             properties:
 124               data-lanes:
 125                 minItems: 1
 126                 maxItems: 4
 127                 items:
 128                   enum: [ 0, 1, 2, 3 ]
 129
 130               link-frequencies:
 131                 minItems: 1
 132                 maxItems: 4
 133                 items:
 134                   enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
 135
 136     required:
 137       - port@0
 138       - port@1
 139
 140 required:
 141   - compatible
 142   - reg
 143   - interrupts
 144   - clocks
 145   - clock-names
 146   - phys
 147   - phy-names
 148   - power-domains
 149   - ports
 150
 151 allOf:
 152   # AUX BUS does not exist on DP controllers
 153   # Audio output also is present only on DP output
 154   # p1 regions is present on DP, but not on eDP
 155   - if:
 156       properties:
 157         compatible:
 158           contains:
 159             enum:
 160               - qcom,sc7280-edp
 161               - qcom,sc8180x-edp
 162               - qcom,sc8280xp-edp
 163     then:
 164       properties:
 165         "#sound-dai-cells": false
 166     else:
 167       properties:
 168         aux-bus: false
 169         reg:
 170           minItems: 5
 171       required:
 172         - "#sound-dai-cells"
 173
 174 additionalProperties: false
 175
 176 examples:
 177   - |
 178     #include <dt-bindings/interrupt-controller/arm-gic.h>
 179     #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
 180     #include <dt-bindings/power/qcom-rpmpd.h>
 181
 182     displayport-controller@ae90000 {
 183         compatible = "qcom,sc7180-dp";
 184         reg = <0xae90000 0x200>,
 185               <0xae90200 0x200>,
 186               <0xae90400 0xc00>,
 187               <0xae91000 0x400>,
 188               <0xae91400 0x400>;
 189         interrupt-parent = <&mdss>;
 190         interrupts = <12>;
 191         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 192                  <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
 193                  <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
 194                  <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
 195                  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
 196         clock-names = "core_iface", "core_aux",
 197                       "ctrl_link",
 198                       "ctrl_link_iface", "stream_pixel";
 199
 200         assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
 201                           <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
 202
 203         assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
 204
 205         phys = <&dp_phy>;
 206         phy-names = "dp";
 207
 208         #sound-dai-cells = <0>;
 209
 210         power-domains = <&rpmhpd SC7180_CX>;
 211
 212         ports {
 213             #address-cells = <1>;
 214             #size-cells = <0>;
 215
 216             port@0 {
 217                 reg = <0>;
 218                 endpoint {
 219                     remote-endpoint = <&dpu_intf0_out>;
 220                 };
 221             };
 222
 223             port@1 {
 224                 reg = <1>;
 225                 endpoint {
 226                     remote-endpoint = <&typec>;
 227                     data-lanes = <0 1>;
 228                     link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
 229                 };
 230             };
 231         };
 232     };
 233 ...