1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 10nm PHY
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
24 - description: dsi phy lane register set
25 - description: dsi pll register set
35 Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
36 connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
38 qcom,phy-rescode-offset-top:
39 $ref: /schemas/types.yaml#/definitions/int8-array
42 Integer array of offset for pull-up legs rescode for all five lanes.
43 To offset the drive strength from the calibrated value in an increasing
44 manner, -32 is the weakest and +31 is the strongest.
49 qcom,phy-rescode-offset-bot:
50 $ref: /schemas/types.yaml#/definitions/int8-array
53 Integer array of offset for pull-down legs rescode for all five lanes.
54 To offset the drive strength from the calibrated value in a decreasing
55 manner, -32 is the weakest and +31 is the strongest.
60 qcom,phy-drive-ldo-level:
61 $ref: /schemas/types.yaml#/definitions/uint32
63 The PHY LDO has an amplitude tuning feature to adjust the LDO output
64 for the HSTX drive. Use supported levels (mV) to offset the drive level
65 from the default value.
66 enum: [ 375, 400, 425, 450, 475, 500 ]
73 unevaluatedProperties: false
77 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
78 #include <dt-bindings/clock/qcom,rpmh.h>
81 compatible = "qcom,dsi-phy-10nm";
82 reg = <0x0ae94400 0x200>,
85 reg-names = "dsi_phy",
92 vdds-supply = <&vdda_mipi_dsi0_pll>;
93 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&rpmhcc RPMH_CXO_CLK>;
95 clock-names = "iface", "ref";
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98 qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
99 qcom,phy-drive-ldo-level = <400>;