Bindings/display/msm/qcom,msm8998-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm MSM8998 Display MDSS
   8
   9 maintainers:
  10   - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
  11
  12 description:
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  15   bindings of MDSS are mentioned for MSM8998 target.
  16
  17 $ref: /schemas/display/msm/mdss-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,msm8998-mdss
  22
  23   clocks:
  24     items:
  25       - description: Display AHB clock
  26       - description: Display AXI clock
  27       - description: Display core clock
  28
  29   clock-names:
  30     items:
  31       - const: iface
  32       - const: bus
  33       - const: core
  34
  35   iommus:
  36     maxItems: 1
  37
  38 patternProperties:
  39   "^display-controller@[0-9a-f]+$":
  40     type: object
  41     additionalProperties: true
  42
  43     properties:
  44       compatible:
  45         const: qcom,msm8998-dpu
  46
  47   "^dsi@[0-9a-f]+$":
  48     type: object
  49     additionalProperties: true
  50
  51     properties:
  52       compatible:
  53         items:
  54           - const: qcom,msm8998-dsi-ctrl
  55           - const: qcom,mdss-dsi-ctrl
  56
  57   "^phy@[0-9a-f]+$":
  58     type: object
  59     additionalProperties: true
  60
  61     properties:
  62       compatible:
  63         const: qcom,dsi-phy-10nm-8998
  64
  65 required:
  66   - compatible
  67
  68 unevaluatedProperties: false
  69
  70 examples:
  71   - |
  72     #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
  73     #include <dt-bindings/clock/qcom,rpmcc.h>
  74     #include <dt-bindings/interrupt-controller/arm-gic.h>
  75     #include <dt-bindings/power/qcom-rpmpd.h>
  76
  77     display-subsystem@c900000 {
  78         compatible = "qcom,msm8998-mdss";
  79         reg = <0x0c900000 0x1000>;
  80         reg-names = "mdss";
  81
  82         clocks = <&mmcc MDSS_AHB_CLK>,
  83                  <&mmcc MDSS_AXI_CLK>,
  84                  <&mmcc MDSS_MDP_CLK>;
  85         clock-names = "iface", "bus", "core";
  86
  87         #address-cells = <1>;
  88         #interrupt-cells = <1>;
  89         #size-cells = <1>;
  90
  91         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  92         interrupt-controller;
  93         iommus = <&mmss_smmu 0>;
  94
  95         power-domains = <&mmcc MDSS_GDSC>;
  96         ranges;
  97
  98         display-controller@c901000 {
  99             compatible = "qcom,msm8998-dpu";
 100             reg = <0x0c901000 0x8f000>,
 101                   <0x0c9a8e00 0xf0>,
 102                   <0x0c9b0000 0x2008>,
 103                   <0x0c9b8000 0x1040>;
 104             reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
 105
 106             clocks = <&mmcc MDSS_AHB_CLK>,
 107                      <&mmcc MDSS_AXI_CLK>,
 108                      <&mmcc MNOC_AHB_CLK>,
 109                      <&mmcc MDSS_MDP_CLK>,
 110                      <&mmcc MDSS_VSYNC_CLK>;
 111             clock-names = "iface", "bus", "mnoc", "core", "vsync";
 112
 113             interrupt-parent = <&mdss>;
 114             interrupts = <0>;
 115             operating-points-v2 = <&mdp_opp_table>;
 116             power-domains = <&rpmpd MSM8998_VDDMX>;
 117
 118             ports {
 119                 #address-cells = <1>;
 120                 #size-cells = <0>;
 121
 122                 port@0 {
 123                     reg = <0>;
 124                     dpu_intf1_out: endpoint {
 125                         remote-endpoint = <&dsi0_in>;
 126                     };
 127                 };
 128
 129                 port@1 {
 130                     reg = <1>;
 131                     dpu_intf2_out: endpoint {
 132                         remote-endpoint = <&dsi1_in>;
 133                     };
 134                 };
 135             };
 136         };
 137
 138         dsi@c994000 {
 139             compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 140             reg = <0x0c994000 0x400>;
 141             reg-names = "dsi_ctrl";
 142
 143             interrupt-parent = <&mdss>;
 144             interrupts = <4>;
 145
 146             clocks = <&mmcc MDSS_BYTE0_CLK>,
 147                      <&mmcc MDSS_BYTE0_INTF_CLK>,
 148                      <&mmcc MDSS_PCLK0_CLK>,
 149                      <&mmcc MDSS_ESC0_CLK>,
 150                      <&mmcc MDSS_AHB_CLK>,
 151                      <&mmcc MDSS_AXI_CLK>;
 152             clock-names = "byte",
 153                           "byte_intf",
 154                           "pixel",
 155                           "core",
 156                           "iface",
 157                           "bus";
 158             assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
 159             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 160
 161             operating-points-v2 = <&dsi_opp_table>;
 162             power-domains = <&rpmpd MSM8998_VDDCX>;
 163
 164             phys = <&dsi0_phy>;
 165             phy-names = "dsi";
 166
 167             #address-cells = <1>;
 168             #size-cells = <0>;
 169
 170             ports {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173
 174                 port@0 {
 175                     reg = <0>;
 176                     dsi0_in: endpoint {
 177                         remote-endpoint = <&dpu_intf1_out>;
 178                     };
 179                 };
 180
 181                 port@1 {
 182                     reg = <1>;
 183                     dsi0_out: endpoint {
 184                     };
 185                 };
 186             };
 187         };
 188
 189         dsi0_phy: phy@c994400 {
 190             compatible = "qcom,dsi-phy-10nm-8998";
 191             reg = <0x0c994400 0x200>,
 192                   <0x0c994600 0x280>,
 193                   <0x0c994a00 0x1e0>;
 194             reg-names = "dsi_phy",
 195                         "dsi_phy_lane",
 196                         "dsi_pll";
 197
 198             #clock-cells = <1>;
 199             #phy-cells = <0>;
 200
 201             clocks = <&mmcc MDSS_AHB_CLK>,
 202                      <&rpmcc RPM_SMD_XO_CLK_SRC>;
 203             clock-names = "iface", "ref";
 204
 205             vdds-supply = <&pm8998_l1>;
 206         };
 207
 208         dsi@c996000 {
 209             compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 210             reg = <0x0c996000 0x400>;
 211             reg-names = "dsi_ctrl";
 212
 213             interrupt-parent = <&mdss>;
 214             interrupts = <5>;
 215
 216             clocks = <&mmcc MDSS_BYTE1_CLK>,
 217                      <&mmcc MDSS_BYTE1_INTF_CLK>,
 218                      <&mmcc MDSS_PCLK1_CLK>,
 219                      <&mmcc MDSS_ESC1_CLK>,
 220                      <&mmcc MDSS_AHB_CLK>,
 221                      <&mmcc MDSS_AXI_CLK>;
 222             clock-names = "byte",
 223                           "byte_intf",
 224                           "pixel",
 225                           "core",
 226                           "iface",
 227                           "bus";
 228             assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
 229             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 230
 231             operating-points-v2 = <&dsi_opp_table>;
 232             power-domains = <&rpmpd MSM8998_VDDCX>;
 233
 234             phys = <&dsi1_phy>;
 235             phy-names = "dsi";
 236
 237             #address-cells = <1>;
 238             #size-cells = <0>;
 239
 240             ports {
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243
 244                 port@0 {
 245                     reg = <0>;
 246                     dsi1_in: endpoint {
 247                         remote-endpoint = <&dpu_intf2_out>;
 248                     };
 249                 };
 250
 251                 port@1 {
 252                     reg = <1>;
 253                     dsi1_out: endpoint {
 254                     };
 255                 };
 256             };
 257         };
 258
 259         dsi1_phy: phy@c996400 {
 260             compatible = "qcom,dsi-phy-10nm-8998";
 261             reg = <0x0c996400 0x200>,
 262                   <0x0c996600 0x280>,
 263                   <0x0c996a00 0x10e>;
 264             reg-names = "dsi_phy",
 265                         "dsi_phy_lane",
 266                         "dsi_pll";
 267
 268             #clock-cells = <1>;
 269             #phy-cells = <0>;
 270
 271             clocks = <&mmcc MDSS_AHB_CLK>,
 272                      <&rpmcc RPM_SMD_XO_CLK_SRC>;
 273             clock-names = "iface", "ref";
 274
 275             vdds-supply = <&pm8998_l1>;
 276         };
 277     };
 278 ...