Bindings/display/msm/qcom,sdm670-mdss.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SDM670 Display MDSS
   8
   9 maintainers:
  10   - Richard Acayan <mailingradian@gmail.com>
  11
  12 description:
  13   SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
  14   like DPU display controller, DSI and DP interfaces etc.
  15
  16 $ref: /schemas/display/msm/mdss-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sdm670-mdss
  21
  22   clocks:
  23     items:
  24       - description: Display AHB clock from gcc
  25       - description: Display core clock
  26
  27   clock-names:
  28     items:
  29       - const: iface
  30       - const: core
  31
  32   iommus:
  33     maxItems: 2
  34
  35   interconnects:
  36     maxItems: 2
  37
  38   interconnect-names:
  39     maxItems: 2
  40
  41 patternProperties:
  42   "^display-controller@[0-9a-f]+$":
  43     type: object
  44     additionalProperties: true
  45
  46     properties:
  47       compatible:
  48         const: qcom,sdm670-dpu
  49
  50   "^displayport-controller@[0-9a-f]+$":
  51     type: object
  52     additionalProperties: true
  53
  54     properties:
  55       compatible:
  56         const: qcom,sdm670-dp
  57
  58   "^dsi@[0-9a-f]+$":
  59     type: object
  60     additionalProperties: true
  61
  62     properties:
  63       compatible:
  64         contains:
  65           const: qcom,sdm670-dsi-ctrl
  66
  67   "^phy@[0-9a-f]+$":
  68     type: object
  69     additionalProperties: true
  70
  71     properties:
  72       compatible:
  73         const: qcom,dsi-phy-10nm
  74
  75 required:
  76   - compatible
  77
  78 unevaluatedProperties: false
  79
  80 examples:
  81   - |
  82     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  83     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  84     #include <dt-bindings/clock/qcom,rpmh.h>
  85     #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
  86     #include <dt-bindings/interrupt-controller/arm-gic.h>
  87     #include <dt-bindings/power/qcom-rpmpd.h>
  88
  89     display-subsystem@ae00000 {
  90         compatible = "qcom,sdm670-mdss";
  91         reg = <0x0ae00000 0x1000>;
  92         reg-names = "mdss";
  93         power-domains = <&dispcc MDSS_GDSC>;
  94
  95         clocks = <&gcc GCC_DISP_AHB_CLK>,
  96                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
  97         clock-names = "iface", "core";
  98
  99         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 100         interrupt-controller;
 101         #interrupt-cells = <1>;
 102
 103         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
 104                         <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
 105         interconnect-names = "mdp0-mem", "mdp1-mem";
 106
 107         iommus = <&apps_smmu 0x880 0x8>,
 108                  <&apps_smmu 0xc80 0x8>;
 109
 110         #address-cells = <1>;
 111         #size-cells = <1>;
 112         ranges;
 113
 114         display-controller@ae01000 {
 115             compatible = "qcom,sdm670-dpu";
 116             reg = <0x0ae01000 0x8f000>,
 117                   <0x0aeb0000 0x2008>;
 118             reg-names = "mdp", "vbif";
 119
 120             clocks = <&gcc GCC_DISP_AXI_CLK>,
 121                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 122                      <&dispcc DISP_CC_MDSS_AXI_CLK>,
 123                      <&dispcc DISP_CC_MDSS_MDP_CLK>,
 124                      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 125             clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 126
 127             interrupt-parent = <&mdss>;
 128             interrupts = <0>;
 129             power-domains = <&rpmhpd SDM670_CX>;
 130             operating-points-v2 = <&mdp_opp_table>;
 131
 132             ports {
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135
 136                 port@0 {
 137                     reg = <0>;
 138                     dpu_intf1_out: endpoint {
 139                         remote-endpoint = <&mdss_dsi0_in>;
 140                     };
 141                 };
 142
 143                 port@1 {
 144                     reg = <1>;
 145                     dpu_intf2_out: endpoint {
 146                         remote-endpoint = <&mdss_dsi1_in>;
 147                     };
 148                 };
 149             };
 150         };
 151
 152         dsi@ae94000 {
 153             compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 154             reg = <0x0ae94000 0x400>;
 155             reg-names = "dsi_ctrl";
 156
 157             interrupt-parent = <&mdss>;
 158             interrupts = <4>;
 159
 160             clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 161                      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 162                      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 163                      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 164                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 165                      <&dispcc DISP_CC_MDSS_AXI_CLK>;
 166             clock-names = "byte",
 167                           "byte_intf",
 168                           "pixel",
 169                           "core",
 170                           "iface",
 171                           "bus";
 172             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
 173                               <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 174             assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
 175
 176             operating-points-v2 = <&dsi_opp_table>;
 177             power-domains = <&rpmhpd SDM670_CX>;
 178
 179             phys = <&mdss_dsi0_phy>;
 180             phy-names = "dsi";
 181
 182             #address-cells = <1>;
 183             #size-cells = <0>;
 184
 185             ports {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188
 189                 port@0 {
 190                     reg = <0>;
 191                     mdss_dsi0_in: endpoint {
 192                         remote-endpoint = <&dpu_intf1_out>;
 193                     };
 194                 };
 195
 196                 port@1 {
 197                     reg = <1>;
 198                     mdss_dsi0_out: endpoint {
 199                     };
 200                 };
 201             };
 202         };
 203
 204         mdss_dsi0_phy: phy@ae94400 {
 205             compatible = "qcom,dsi-phy-10nm";
 206             reg = <0x0ae94400 0x200>,
 207                   <0x0ae94600 0x280>,
 208                   <0x0ae94a00 0x1e0>;
 209             reg-names = "dsi_phy",
 210                         "dsi_phy_lane",
 211                         "dsi_pll";
 212
 213             #clock-cells = <1>;
 214             #phy-cells = <0>;
 215
 216             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 217                      <&rpmhcc RPMH_CXO_CLK>;
 218             clock-names = "iface", "ref";
 219             vdds-supply = <&vreg_dsi_phy>;
 220         };
 221
 222         dsi@ae96000 {
 223             compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 224             reg = <0x0ae96000 0x400>;
 225             reg-names = "dsi_ctrl";
 226
 227             interrupt-parent = <&mdss>;
 228             interrupts = <5>;
 229
 230             clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 231                      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 232                      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 233                      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 234                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
 235                      <&dispcc DISP_CC_MDSS_AXI_CLK>;
 236             clock-names = "byte",
 237                           "byte_intf",
 238                           "pixel",
 239                           "core",
 240                           "iface",
 241                           "bus";
 242             assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
 243                               <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 244             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 245
 246             operating-points-v2 = <&dsi_opp_table>;
 247             power-domains = <&rpmhpd SDM670_CX>;
 248
 249             phys = <&dsi1_phy>;
 250             phy-names = "dsi";
 251
 252             #address-cells = <1>;
 253             #size-cells = <0>;
 254
 255             ports {
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258
 259                 port@0 {
 260                     reg = <0>;
 261                     mdss_dsi1_in: endpoint {
 262                         remote-endpoint = <&dpu_intf2_out>;
 263                     };
 264                 };
 265
 266                 port@1 {
 267                     reg = <1>;
 268                     mdss_dsi1_out: endpoint {
 269                     };
 270                 };
 271             };
 272         };
 273
 274         mdss_dsi1_phy: phy@ae96400 {
 275             compatible = "qcom,dsi-phy-10nm";
 276             reg = <0x0ae96400 0x200>,
 277                   <0x0ae96600 0x280>,
 278                   <0x0ae96a00 0x10e>;
 279             reg-names = "dsi_phy",
 280                         "dsi_phy_lane",
 281                         "dsi_pll";
 282
 283             #clock-cells = <1>;
 284             #phy-cells = <0>;
 285
 286             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 287                      <&rpmhcc RPMH_CXO_CLK>;
 288             clock-names = "iface", "ref";
 289             vdds-supply = <&vreg_dsi_phy>;
 290         };
 291     };
 292 ...