1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
12 standard. The subsystem includes multiple functional blocks as below:
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
20 | | and STC | +-----------+ | | Controller | | +------+
21 Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
22 | | | | Mixer | --+-> | | | +------+
23 Live Audio --->| | --> | | || +-------------+ |
24 | +----------------+ +-----------+ || |
25 +---------------------------------------||-------------------+
30 The Buffer Manager interacts with external interface such as DMA engines or
31 live audio/video streams from the programmable logic. The Video Rendering
32 Pipeline blends the video and graphics layers and performs colorspace
33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34 Source Controller handles the DisplayPort protocol and connects to external
37 The subsystem supports 2 video and 2 audio streams, and various pixel formats
38 and depths up to 4K@30 resolution.
40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
45 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
49 const: xlnx,zynqmp-dpsub-1.7
65 The APB clock and at least one video clock are mandatory, the audio clock
69 - description: dp_apb_clk is the APB clock
70 - description: dp_aud_clk is the Audio clock
72 dp_vtc_pixel_clk_in is the non-live video clock (from Processing
75 dp_live_video_in_clk is the live video clock (from Programmable
82 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
83 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
88 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
89 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
99 - description: Video layer, plane 0 (RGB or luma)
100 - description: Video layer, plane 1 (U/V or U)
101 - description: Video layer, plane 2 (V)
102 - description: Graphics layer
111 description: PHYs for the DP data lanes
121 $ref: /schemas/graph.yaml#/properties/ports
123 Connections to the programmable logic and the DisplayPort PHYs. Each port
124 shall have a single endpoint.
128 $ref: /schemas/graph.yaml#/properties/port
129 description: The live video input from the programmable logic
132 $ref: /schemas/graph.yaml#/properties/port
133 description: The live graphics input from the programmable logic
136 $ref: /schemas/graph.yaml#/properties/port
137 description: The live audio input from the programmable logic
140 $ref: /schemas/graph.yaml#/properties/port
141 description: The blended video output to the programmable logic
144 $ref: /schemas/graph.yaml#/properties/port
145 description: The mixed audio output to the programmable logic
148 $ref: /schemas/graph.yaml#/properties/port
149 description: The DisplayPort output
174 additionalProperties: false
178 #include <dt-bindings/phy/phy.h>
179 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
182 compatible = "xlnx,zynqmp-dpsub-1.7";
183 reg = <0xfd4a0000 0x1000>,
187 reg-names = "dp", "blend", "av_buf", "aud";
188 interrupts = <0 119 4>;
189 interrupt-parent = <&gic>;
191 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
192 clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
194 power-domains = <&pd_dp>;
195 resets = <&reset ZYNQMP_RESET_DP>;
197 dma-names = "vid0", "vid1", "vid2", "gfx0";
198 dmas = <&xlnx_dpdma 0>,
203 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
204 <&psgtr 0 PHY_TYPE_DP 1 3>;
206 phy-names = "dp-phy0", "dp-phy1";
209 #address-cells = <1>;
229 dpsub_dp_out: endpoint {
230 remote-endpoint = <&dp_connector>;