Bindings/dma/qcom,gpi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies Inc GPI DMA controller
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description: |
  13   QCOM GPI DMA controller provides DMA capabilities for
  14   peripheral buses such as I2C, UART, and SPI.
  15
  16 allOf:
  17   - $ref: dma-controller.yaml#
  18
  19 properties:
  20   compatible:
  21     oneOf:
  22       - enum:
  23           - qcom,sdm845-gpi-dma
  24           - qcom,sm6350-gpi-dma
  25       - items:
  26           - enum:
  27               - qcom,qcm2290-gpi-dma
  28               - qcom,qdu1000-gpi-dma
  29               - qcom,sc7280-gpi-dma
  30               - qcom,sm6115-gpi-dma
  31               - qcom,sm6375-gpi-dma
  32               - qcom,sm8350-gpi-dma
  33               - qcom,sm8450-gpi-dma
  34               - qcom,sm8550-gpi-dma
  35           - const: qcom,sm6350-gpi-dma
  36       - items:
  37           - enum:
  38               - qcom,sdm670-gpi-dma
  39               - qcom,sm6125-gpi-dma
  40               - qcom,sm8150-gpi-dma
  41               - qcom,sm8250-gpi-dma
  42           - const: qcom,sdm845-gpi-dma
  43
  44   reg:
  45     maxItems: 1
  46
  47   interrupts:
  48     description:
  49       Interrupt lines for each GPI instance
  50     minItems: 1
  51     maxItems: 13
  52
  53   "#dma-cells":
  54     const: 3
  55     description: >
  56       DMA clients must use the format described in dma.txt, giving a phandle
  57       to the DMA controller plus the following 3 integer cells:
  58       - channel: if set to 0xffffffff, any available channel will be allocated
  59         for the client. Otherwise, the exact channel specified will be used.
  60       - seid: serial id of the client as defined in the SoC documentation.
  61       - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
  62
  63   iommus:
  64     maxItems: 1
  65
  66   dma-channels:
  67     maximum: 31
  68
  69   dma-channel-mask:
  70     maxItems: 1
  71
  72   dma-coherent: true
  73
  74 required:
  75   - compatible
  76   - reg
  77   - interrupts
  78   - "#dma-cells"
  79   - iommus
  80   - dma-channels
  81   - dma-channel-mask
  82
  83 additionalProperties: false
  84
  85 examples:
  86   - |
  87     #include <dt-bindings/interrupt-controller/arm-gic.h>
  88     #include <dt-bindings/dma/qcom-gpi.h>
  89     gpi_dma0: dma-controller@800000 {
  90         compatible = "qcom,sdm845-gpi-dma";
  91         #dma-cells = <3>;
  92         reg = <0x00800000 0x60000>;
  93         iommus = <&apps_smmu 0x0016 0x0>;
  94         dma-channels = <13>;
  95         dma-channel-mask = <0xfa>;
  96         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
  97                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
  98                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
  99                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 100                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 101                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 102                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 103                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 104                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 105                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 106                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 107                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 108                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 109     };
 110
 111 ...