Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Xilinx ZynqMP DMA Engine
   8
   9 description: |
  10   The Xilinx ZynqMP DMA engine supports memory to memory transfers,
  11   memory to device and device to memory transfers. It also has flow
  12   control and rate control support for slave/peripheral dma access.
  13
  14 maintainers:
  15   - Michael Tretter <m.tretter@pengutronix.de>
  16   - Harini Katakam <harini.katakam@amd.com>
  17   - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
  18
  19 allOf:
  20   - $ref: ../dma-controller.yaml#
  21
  22 properties:
  23   "#dma-cells":
  24     const: 1
  25
  26   compatible:
  27     const: xlnx,zynqmp-dma-1.0
  28
  29   reg:
  30     description: memory map for gdma/adma module access
  31     maxItems: 1
  32
  33   interrupts:
  34     description: DMA channel interrupt
  35     maxItems: 1
  36
  37   clocks:
  38     description: input clocks
  39     minItems: 2
  40     maxItems: 2
  41
  42   clock-names:
  43     items:
  44       - const: clk_main
  45       - const: clk_apb
  46
  47   xlnx,bus-width:
  48     $ref: /schemas/types.yaml#/definitions/uint32
  49     enum:
  50       - 64
  51       - 128
  52     description: AXI bus width in bits
  53
  54   iommus:
  55     maxItems: 1
  56
  57   power-domains:
  58     maxItems: 1
  59
  60   dma-coherent:
  61     description: present if dma operations are coherent
  62
  63 required:
  64   - "#dma-cells"
  65   - compatible
  66   - reg
  67   - interrupts
  68   - clocks
  69   - clock-names
  70   - xlnx,bus-width
  71
  72 additionalProperties: false
  73
  74 examples:
  75   - |
  76     #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
  77
  78     fpd_dma_chan1: dma-controller@fd500000 {
  79       compatible = "xlnx,zynqmp-dma-1.0";
  80       reg = <0xfd500000 0x1000>;
  81       interrupt-parent = <&gic>;
  82       interrupts = <0 117 0x4>;
  83       #dma-cells = <1>;
  84       clock-names = "clk_main", "clk_apb";
  85       clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
  86       xlnx,bus-width = <128>;
  87       dma-coherent;
  88     };