Bindings/interconnect/samsung,exynos-bus.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung Exynos SoC Bus and Interconnect
   8
   9 maintainers:
  10   - Chanwoo Choi <cw00.choi@samsung.com>
  11   - Krzysztof Kozlowski <krzk@kernel.org>
  12
  13 description: |
  14   The Samsung Exynos SoC has many buses for data transfer between DRAM and
  15   sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
  16   Generally, each bus of Exynos SoC includes a source clock and a power line,
  17   which are able to change the clock frequency of the bus in runtime. To
  18   monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
  19   Performance Monitoring Unit), which is able to measure the current load of
  20   sub-blocks.
  21
  22   The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  23   The each AXI bus has the owned source clock but, has not the only owned power
  24   line. The power line might be shared among one more sub-blocks.  So, we can
  25   divide into two type of device as the role of each sub-block.  There are two
  26   type of bus devices as following::
  27    - parent bus device
  28    - passive bus device
  29
  30   Basically, parent and passive bus device share the same power line.  The
  31   parent bus device can only change the voltage of shared power line and the
  32   rest bus devices (passive bus device) depend on the decision of the parent
  33   bus device. If there are three blocks which share the VDD_xxx power line,
  34   Only one block should be parent device and then the rest blocks should depend
  35   on the parent device as passive device.
  36
  37     VDD_xxx |--- A block (parent)
  38       |--- B block (passive)
  39       |--- C block (passive)
  40
  41   There are a little different composition among Exynos SoC because each Exynos
  42   SoC has different sub-blocks. Therefore, such difference should be specified
  43   in devicetree file instead of each device driver. In result, this driver is
  44   able to support the bus frequency for all Exynos SoCs.
  45
  46   Detailed correlation between sub-blocks and power line according
  47   to Exynos SoC::
  48    - In case of Exynos3250, there are two power line as following::
  49      VDD_MIF |--- DMC (Dynamic Memory Controller)
  50
  51      VDD_INT |--- LEFTBUS (parent device)
  52        |--- PERIL
  53        |--- MFC
  54        |--- G3D
  55        |--- RIGHTBUS
  56        |--- PERIR
  57        |--- FSYS
  58        |--- LCD0
  59        |--- PERIR
  60        |--- ISP
  61        |--- CAM
  62
  63      - MIF bus's frequency/voltage table
  64        -----------------------
  65        |Lv| Freq   | Voltage |
  66        -----------------------
  67        |L1| 50000  |800000   |
  68        |L2| 100000 |800000   |
  69        |L3| 134000 |800000   |
  70        |L4| 200000 |825000   |
  71        |L5| 400000 |875000   |
  72        -----------------------
  73
  74      - INT bus's frequency/voltage table
  75        ----------------------------------------------------------
  76        |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
  77        | name|       |LCD0    |       |       |       ||        |
  78        |     |       |FSYS    |       |       |       ||        |
  79        |     |       |MFC     |       |       |       ||        |
  80        ----------------------------------------------------------
  81        |Mode |*parent|passive |passive|passive|passive||        |
  82        ----------------------------------------------------------
  83        |Lv   |Frequency                               ||Voltage |
  84        ----------------------------------------------------------
  85        |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
  86        |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
  87        |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
  88        |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
  89        |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
  90        ----------------------------------------------------------
  91
  92    - In case of Exynos4210, there is one power line as following::
  93      VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
  94        |--- LEFTBUS
  95        |--- PERIL
  96        |--- MFC(L)
  97        |--- G3D
  98        |--- TV
  99        |--- LCD0
 100        |--- RIGHTBUS
 101        |--- PERIR
 102        |--- MFC(R)
 103        |--- CAM
 104        |--- FSYS
 105        |--- GPS
 106        |--- LCD0
 107        |--- LCD1
 108
 109    - In case of Exynos4x12, there are two power line as following::
 110      VDD_MIF |--- DMC (Dynamic Memory Controller)
 111
 112      VDD_INT |--- LEFTBUS (parent device)
 113        |--- PERIL
 114        |--- MFC(L)
 115        |--- G3D
 116        |--- TV
 117        |--- IMAGE
 118        |--- RIGHTBUS
 119        |--- PERIR
 120        |--- MFC(R)
 121        |--- CAM
 122        |--- FSYS
 123        |--- GPS
 124        |--- LCD0
 125        |--- ISP
 126
 127    - In case of Exynos5422, there are two power line as following::
 128      VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
 129              |--- DREX 1
 130
 131      VDD_INT |--- NoC_Core (parent device)
 132        |--- G2D
 133        |--- G3D
 134        |--- DISP1
 135        |--- NoC_WCORE
 136        |--- GSCL
 137        |--- MSCL
 138        |--- ISP
 139        |--- MFC
 140        |--- GEN
 141        |--- PERIS
 142        |--- PERIC
 143        |--- FSYS
 144        |--- FSYS2
 145
 146    - In case of Exynos5433, there is VDD_INT power line as following::
 147      VDD_INT |--- G2D (parent device)
 148        |--- MSCL
 149        |--- GSCL
 150        |--- JPEG
 151        |--- MFC
 152        |--- HEVC
 153        |--- BUS0
 154        |--- BUS1
 155        |--- BUS2
 156        |--- PERIS (Fixed clock rate)
 157        |--- PERIC (Fixed clock rate)
 158        |--- FSYS  (Fixed clock rate)
 159
 160 properties:
 161   compatible:
 162     enum:
 163       - samsung,exynos-bus
 164
 165   clocks:
 166     maxItems: 1
 167
 168   clock-names:
 169     items:
 170       - const: bus
 171
 172   devfreq:
 173     $ref: /schemas/types.yaml#/definitions/phandle
 174     description:
 175       Parent bus device. Valid and required only for the passive bus devices.
 176
 177   devfreq-events:
 178     $ref: /schemas/types.yaml#/definitions/phandle-array
 179     minItems: 1
 180     maxItems: 4
 181     description:
 182       Devfreq-event device to monitor the current utilization of buses. Valid
 183       and required only for the parent bus devices.
 184
 185   exynos,saturation-ratio:
 186     $ref: /schemas/types.yaml#/definitions/uint32
 187     description:
 188       Percentage value which is used to calibrate the performance count against
 189       total cycle count.  Valid only for the parent bus devices.
 190
 191   '#interconnect-cells':
 192     const: 0
 193
 194   interconnects:
 195     minItems: 1
 196     maxItems: 2
 197
 198   operating-points-v2: true
 199   opp-table:
 200     type: object
 201
 202   samsung,data-clock-ratio:
 203     $ref: /schemas/types.yaml#/definitions/uint32
 204     default: 8
 205     description:
 206       Ratio of the data throughput in B/s to minimum data clock frequency in
 207       Hz.
 208
 209   vdd-supply:
 210     description:
 211       Main bus power rail. Valid and required only for the parent bus devices.
 212
 213 required:
 214   - compatible
 215   - clocks
 216   - clock-names
 217   - operating-points-v2
 218
 219 additionalProperties: false
 220
 221 examples:
 222   - |
 223     #include <dt-bindings/clock/exynos3250.h>
 224
 225     bus-dmc {
 226         compatible = "samsung,exynos-bus";
 227         clocks = <&cmu_dmc CLK_DIV_DMC>;
 228         clock-names = "bus";
 229         operating-points-v2 = <&bus_dmc_opp_table>;
 230         devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
 231         vdd-supply = <&buck1_reg>;
 232
 233         bus_dmc_opp_table: opp-table {
 234             compatible = "operating-points-v2";
 235
 236             opp-50000000 {
 237                 opp-hz = /bits/ 64 <50000000>;
 238                 opp-microvolt = <800000>;
 239             };
 240             opp-100000000 {
 241                 opp-hz = /bits/ 64 <100000000>;
 242                 opp-microvolt = <800000>;
 243             };
 244             opp-134000000 {
 245                 opp-hz = /bits/ 64 <134000000>;
 246                 opp-microvolt = <800000>;
 247             };
 248             opp-200000000 {
 249                 opp-hz = /bits/ 64 <200000000>;
 250                 opp-microvolt = <825000>;
 251             };
 252             opp-400000000 {
 253                 opp-hz = /bits/ 64 <400000000>;
 254                 opp-microvolt = <875000>;
 255             };
 256         };
 257     };
 258
 259     ppmu_dmc0: ppmu@106a0000 {
 260         compatible = "samsung,exynos-ppmu";
 261         reg = <0x106a0000 0x2000>;
 262         events {
 263             ppmu_dmc0_3: ppmu-event3-dmc0 {
 264                 event-name = "ppmu-event3-dmc0";
 265             };
 266         };
 267     };
 268
 269     bus_leftbus: bus-leftbus {
 270         compatible = "samsung,exynos-bus";
 271         clocks = <&cmu CLK_DIV_GDL>;
 272         clock-names = "bus";
 273         operating-points-v2 = <&bus_leftbus_opp_table>;
 274         devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
 275         vdd-supply = <&buck3_reg>;
 276     };
 277
 278     bus-rightbus {
 279         compatible = "samsung,exynos-bus";
 280         clocks = <&cmu CLK_DIV_GDR>;
 281         clock-names = "bus";
 282         operating-points-v2 = <&bus_leftbus_opp_table>;
 283         devfreq = <&bus_leftbus>;
 284     };
 285
 286   - |
 287     dmc: bus-dmc {
 288         compatible = "samsung,exynos-bus";
 289         clocks = <&clock CLK_DIV_DMC>;
 290         clock-names = "bus";
 291         operating-points-v2 = <&bus_dmc_opp_table>;
 292         samsung,data-clock-ratio = <4>;
 293         #interconnect-cells = <0>;
 294         devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
 295         vdd-supply = <&buck1_reg>;
 296     };
 297
 298     leftbus: bus-leftbus {
 299         compatible = "samsung,exynos-bus";
 300         clocks = <&clock CLK_DIV_GDL>;
 301         clock-names = "bus";
 302         operating-points-v2 = <&bus_leftbus_opp_table>;
 303         interconnects = <&dmc>;
 304         #interconnect-cells = <0>;
 305         devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
 306         vdd-supply = <&buck3_reg>;
 307     };
 308
 309     display: bus-display {
 310         compatible = "samsung,exynos-bus";
 311         clocks = <&clock CLK_DIV_ACLK_266>;
 312         clock-names = "bus";
 313         operating-points-v2 = <&bus_display_opp_table>;
 314         interconnects = <&leftbus &dmc>;
 315         #interconnect-cells = <0>;
 316         devfreq = <&leftbus>;
 317     };